3 Without linker script patch it doesn't place vector table in final binary.
4 And clock is configured to 48MHz using internal clock reference and FLL multiplication.
7 mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c
8 Fix SystemInit: clock setup for internal clock. Inifinity has no external Xtal.
10 mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.c
11 Fix NVIC vector address of firmware 0x1000 instead of 0x0
13 mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
14 Fix memory map for Infinity bootloader
15 Flash starts at 0x1000
16 No flash config bytes sector
18 USBDevice/USBDevice/USBHAL_KL25Z.cpp
19 Fix USB clock setup, see below.
22 2015/01/04 Based on mbed-sdk @2f63fa7d78a26.
28 Clock source: Internal reference clock wth FLL
29 SIM_SOPT[USBSRC] = 1(MCGPLLCLK/MCGFLLCLK)
30 SIM_SOPT[PLLSEL] = 0(MCGFLLCLK)
33 SIM_CLKDIV2[USBDIV] = 0
34 SIM_CLKDIV2[USBFAC] = 0
41 Infinity bootloader change
42 ==========================
43 After @2c7542e(2015/01) Infinity bootloader doesn't disable watchdog timer and keyboard firmware has to do it itself. mbed disables watchdog in startup sequence but unfortunately timer is timed out bofore that.
45 We have to do that in earlier phase of mbed startup sequence.
48 mbed starup sequence files:
49 mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_M20D5.s
50 mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c
52 Infinity booloader change commit:
53 https://github.com/kiibohd/controller/commit/2c7542e2e7f0b8a99edf563dc53164fe1a439483
56 https://geekhack.org/index.php?topic=41989.msg1686616#msg1686616
61 Call SystemInit early in Reset_Handler.
63 $ diff -u ../../mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s mbed-infinity
64 --- ../../mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s 2015-03-22 10:33:22.779866000 +0900
65 +++ mbed-infinity/startup_MK20D5.s 2015-03-22 10:32:56.483866000 +0900
67 * __etext: End of code section, i.e., begin of data sections to copy from.
68 * __data_start__/__data_end__: RAM address range that data should be
69 * copied to. Both must be aligned to 4 bytes boundary. */
74 ldr r2, =__data_start__
77 .Lflash_to_ram_loop_end: