1 flabbergast's TMK/ChibiOS port
2 ==============================
8 Set up ChibiOS according to tmk_core/protocol/chibios/README.md
13 halconf.h: for HAL configuration
14 placed in project directory
15 read in chibios/os/hal/hal.mk
16 included in chibios/os/hal/include/hal.h
17 mcuconf.h: for MCU configuration
18 placed in project directory
24 PAL = Port Abstraction Layer
28 chibios/os/hal/include/pal.h
30 LLD = Low Level Driver
35 # <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
39 # - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
41 MCU_LDSCRIPT = MKL26Z64
43 # - it should exist in <chibios>/os/common/ports/ARMCMx/compilers/GCC/mk/
46 # Board: it should exist either in <chibios>/os/hal/boards/
47 # or <this_dir>/boards
48 BOARD = PJRC_TEENSY_LC
52 # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
70 --- ../../tmk_core/tool/chibios/chibios/os/common/ports/ARMCMx/compilers/GCC/ld/MKL26Z64.ld 2015-10-15 09:08:58.732904304 +0900
71 +++ ld/MKL26Z64.ld 2015-10-15 08:48:06.430215496 +0900
74 flash0 : org = 0x00000000, len = 0xc0
75 flashcfg : org = 0x00000400, len = 0x10
76 - flash : org = 0x00000410, len = 64k - 0x410
77 + flash : org = 0x00000410, len = 62k - 0x410
78 + eeprom_emu : org = 0x0000F800, len = 2k
79 ram : org = 0x1FFFF800, len = 8k
83 __ram_size__ = LENGTH(ram);
84 __ram_end__ = __ram_start__ + __ram_size__;
86 +__eeprom_workarea_start__ = ORIGIN(eeprom_emu);
87 +__eeprom_workarea_size__ = LENGTH(eeprom_emu);
88 +__eeprom_workarea_end__ = __eeprom_workarea_start__ + __eeprom_workarea_size__;
96 Configuration/Startup for Infinity 60%
97 --------------------------------------
103 FEI(FLL Engaged Internal) mode with core clock:48MHz, bus clock:48MHz, flash clock:24MHz
105 SIM_CLKDIV1[OUTDIV1] = 0 divide-by-1 for core clock
106 SIM_CLKDIV1[OUTDIV2] = 0 divide-by-1 for bus clock
107 SIM_CLKDIV1[OUTDIV4] = 1 divide-by-2 for flash clock
108 Internal reference clock:
109 MCG_C1[IREFS] = 1 Internal Reference Select for clock source for FLL
110 MCG_C1[IRCLKEN] = 1 Internal Reference Clock Enable
113 MCG_C4[DRST_DRS] = 01 FLL factor 1464 * 32.768kHz = 48MHz
115 chibios/os/hal/ports/KINETIS/K20x/hal_lld.c
116 k20x_clock_init(): called in __early_init() defined in board.c
117 disable watchdog and configure clock
120 KINETIS_NO_INIT: whether init or not
121 KINETIS_MCG_MODE: clock mode
124 hal/ports/KINETIS/K20x/hal_lld.h
127 chibios/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h
128 PALConfig pal_default_config
131 macro definitions for board infos, freq and mcu type
133 chibios/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
140 common/ports/ARMCMx/GCC/crt0_v[67]m.s
141 Reset_Handler: startup code
142 common/ports/ARMCMx/GCC/crt1.c
146 __default_exit(): weak
147 called from Reset_Handler of crt0
148 common/ports/ARMCMx/GCC/vector.c
149 common/ports/ARMCMx/GCC/ld/*.ld
151 chibios/os/common/ports/ARMCMx/compilers/GCC/
156 │ ├── MK20DX128BLDR3.ld
157 │ ├── MK20DX128BLDR4.ld
165 │ ├── startup_k20x5.mk
166 │ ├── startup_k20x7.mk
167 │ ├── startup_k20x.mk
168 │ ├── startup_kl2x.mk
169 │ └── startup_stm32l4xx.mk
176 │ ├── FREESCALE_FREEDOM_K20D50M
188 │ ├── PJRC_TEENSY_3_1
201 │ ├── ST_NUCLEO_F030R8
270 │ │ │ ├── kinetis_registry.h
271 │ │ │ ├── platform.dox
272 │ │ │ ├── platform.mk
280 │ │ │ ├── kinetis_registry.h
281 │ │ │ ├── platform.mk
295 │ │ │ ├── serial_lld.c
296 │ │ │ ├── serial_lld.h