2 ******************************************************************************
3 * @file stm32f1xx_hal_dma.h
4 * @author MCD Application Team
6 * @date 15-December-2014
7 * @brief Header file of DMA HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_DMA_H
40 #define __STM32F1xx_HAL_DMA_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
49 /** @addtogroup STM32F1xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup DMA_Exported_Types DMA Exported Types
63 * @brief DMA Configuration Structure definition
67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
68 from memory to memory or from peripheral to memory.
69 This parameter can be a value of @ref DMA_Data_transfer_direction */
71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
78 This parameter can be a value of @ref DMA_Peripheral_data_size */
80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
81 This parameter can be a value of @ref DMA_Memory_data_size */
83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
84 This parameter can be a value of @ref DMA_mode
85 @note The circular buffer mode cannot be used if the memory-to-memory
86 data transfer is configured on the selected Channel */
88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
89 This parameter can be a value of @ref DMA_Priority_level */
94 * @brief DMA Configuration enumeration values definition
98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
101 } DMA_ControlTypeDef;
104 * @brief HAL DMA State structures definition
108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
115 }HAL_DMA_StateTypeDef;
118 * @brief HAL DMA Error Code structure definition
122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
125 }HAL_DMA_LevelCompleteTypeDef;
128 * @brief DMA handle Structure definition
130 typedef struct __DMA_HandleTypeDef
132 DMA_Channel_TypeDef *Instance; /*!< Register base address */
134 DMA_InitTypeDef Init; /*!< DMA communication parameters */
136 HAL_LockTypeDef Lock; /*!< DMA locking object */
138 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
140 void *Parent; /*!< Parent object state */
142 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
144 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
146 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
148 __IO uint32_t ErrorCode; /*!< DMA Error code */
155 /* Exported constants --------------------------------------------------------*/
156 /** @defgroup DMA_Exported_Constants DMA Exported Constants
160 /** @defgroup DMA_Error_Codes DMA Error Codes
163 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
164 #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
165 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
173 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
176 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
177 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
178 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
180 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
181 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
182 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
187 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
190 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
195 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
198 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
199 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
201 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
202 ((STATE) == DMA_PINC_DISABLE))
207 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
210 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
211 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
213 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
214 ((STATE) == DMA_MINC_DISABLE))
219 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
222 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
223 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
224 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
226 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
227 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
228 ((SIZE) == DMA_PDATAALIGN_WORD))
234 /** @defgroup DMA_Memory_data_size DMA Memory data size
237 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
238 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
239 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
241 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
242 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
243 ((SIZE) == DMA_MDATAALIGN_WORD ))
248 /** @defgroup DMA_mode DMA mode
251 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
252 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
254 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
255 ((MODE) == DMA_CIRCULAR))
260 /** @defgroup DMA_Priority_level DMA Priority level
263 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
264 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
265 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
266 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
268 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
269 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
270 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
271 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
277 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
281 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
282 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
283 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
289 /** @defgroup DMA_flag_definitions DMA flag definitions
293 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
294 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
295 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
296 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
297 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
298 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
299 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
300 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
301 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
302 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
303 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
304 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
305 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
306 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
307 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
308 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
309 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
310 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
311 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
312 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
313 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
314 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
315 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
316 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
317 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
318 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
319 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
320 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
331 /* Exported macros -----------------------------------------------------------*/
332 /** @defgroup DMA_Exported_Macros DMA Exported Macros
336 /** @brief Reset DMA handle state
337 * @param __HANDLE__: DMA handle.
340 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
343 * @brief Enable the specified DMA Channel.
344 * @param __HANDLE__: DMA handle
347 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
350 * @brief Disable the specified DMA Channel.
351 * @param __HANDLE__: DMA handle
354 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
357 /* Interrupt & Flag management */
360 * @brief Enables the specified DMA Channel interrupts.
361 * @param __HANDLE__: DMA handle
362 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
363 * This parameter can be any combination of the following values:
364 * @arg DMA_IT_TC: Transfer complete interrupt mask
365 * @arg DMA_IT_HT: Half transfer complete interrupt mask
366 * @arg DMA_IT_TE: Transfer error interrupt mask
369 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
372 * @brief Disables the specified DMA Channel interrupts.
373 * @param __HANDLE__: DMA handle
374 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
375 * This parameter can be any combination of the following values:
376 * @arg DMA_IT_TC: Transfer complete interrupt mask
377 * @arg DMA_IT_HT: Half transfer complete interrupt mask
378 * @arg DMA_IT_TE: Transfer error interrupt mask
381 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
384 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
385 * @param __HANDLE__: DMA handle
386 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
387 * This parameter can be one of the following values:
388 * @arg DMA_IT_TC: Transfer complete interrupt mask
389 * @arg DMA_IT_HT: Half transfer complete interrupt mask
390 * @arg DMA_IT_TE: Transfer error interrupt mask
391 * @retval The state of DMA_IT (SET or RESET).
393 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
399 /* Include DMA HAL Extension module */
400 #include "stm32f1xx_hal_dma_ex.h"
402 /* Exported functions --------------------------------------------------------*/
403 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
407 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
410 /* Initialization and de-initialization functions *****************************/
411 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
412 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
417 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
420 /* IO operation functions *****************************************************/
421 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
422 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
423 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
424 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
425 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
430 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
433 /* Peripheral State and Error functions ***************************************/
434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
435 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
456 #endif /* __STM32F1xx_HAL_DMA_H */
458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/