2 ******************************************************************************
3 * @file stm32f1xx_hal_nor.c
4 * @author MCD Application Team
6 * @date 15-December-2014
7 * @brief NOR HAL module driver.
8 * This file provides a generic firmware to drive NOR memories mounted
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
16 This driver is a generic layered driver which contains a set of APIs used to
17 control NOR flash memories. It uses the FSMC layer functions to interface
18 with NOR devices. This driver is used as follows:
20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
21 with control and timing parameters for both normal and extended mode.
23 (+) Read NOR flash memory manufacturer code and device IDs using the function
24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
25 structure declared by the function caller.
27 (+) Access NOR flash memory by read/write data unit operations using the functions
28 HAL_NOR_Read(), HAL_NOR_Program().
30 (+) Perform NOR flash erase block/chip operations using the functions
31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
35 structure declared by the function caller.
37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
40 (+) You can monitor the NOR device HAL state by calling the function
43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
44 If a NOR flash device contains different operations and/or implementations,
45 it should be implemented separately.
47 *** NOR HAL driver macros list ***
48 =============================================
50 Below the list of most used macros in NOR HAL driver.
52 (+) __NOR_WRITE : NOR memory write data to specified address
55 ******************************************************************************
58 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 ******************************************************************************
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f1xx_hal.h"
88 /** @addtogroup STM32F1xx_HAL_Driver
92 #ifdef HAL_NOR_MODULE_ENABLED
93 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
96 * @brief NOR driver modules
99 /* Private typedef -----------------------------------------------------------*/
100 /* Private define ------------------------------------------------------------*/
101 /** @defgroup NOR_Private_Constants NOR Private Constants
105 /* Constants to define address to set to write a command */
106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
114 /* Constants to define data to program a command */
115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
130 /* Mask on NOR STATUS REGISTER */
131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
138 /* Private macro -------------------------------------------------------------*/
139 /** @defgroup NOR_Private_Macros NOR Private Macros
147 /* Private variables ---------------------------------------------------------*/
149 /** @defgroup NOR_Private_Variables NOR Private Variables
153 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
159 /* Private function prototypes -----------------------------------------------*/
160 /* Private functions ---------------------------------------------------------*/
162 /** @defgroup NOR_Exported_Functions NOR Exported Functions
166 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
167 * @brief Initialization and Configuration functions
170 ==============================================================================
171 ##### NOR Initialization and de_initialization functions #####
172 ==============================================================================
174 This section provides functions allowing to initialize/de-initialize
182 * @brief Perform the NOR memory Initialization sequence
183 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
184 * the configuration information for NOR module.
185 * @param Timing: pointer to NOR control timing structure
186 * @param ExtTiming: pointer to NOR extended mode timing structure
189 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
191 /* Check the NOR handle parameter */
197 if(hnor->State == HAL_NOR_STATE_RESET)
199 /* Allocate lock resource and initialize it */
200 hnor-> Lock = HAL_UNLOCKED;
202 /* Initialize the low level hardware (MSP) */
203 HAL_NOR_MspInit(hnor);
206 /* Initialize NOR control Interface */
207 FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
209 /* Initialize NOR timing Interface */
210 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
212 /* Initialize NOR extended mode timing Interface */
213 FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
215 /* Enable the NORSRAM device */
216 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
218 /* Initialize NOR Memory Data Width*/
219 if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
221 uwNORMemoryDataWidth = NOR_MEMORY_8B;
225 uwNORMemoryDataWidth = NOR_MEMORY_16B;
228 /* Check the NOR controller state */
229 hnor->State = HAL_NOR_STATE_READY;
235 * @brief Perform NOR memory De-Initialization sequence
236 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
237 * the configuration information for NOR module.
240 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
242 /* De-Initialize the low level hardware (MSP) */
243 HAL_NOR_MspDeInit(hnor);
245 /* Configure the NOR registers with their reset values */
246 FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
248 /* Update the NOR controller state */
249 hnor->State = HAL_NOR_STATE_RESET;
258 * @brief NOR MSP Init
259 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
260 * the configuration information for NOR module.
263 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
265 /* NOTE : This function Should not be modified, when the callback is needed,
266 the HAL_NOR_MspInit could be implemented in the user file
271 * @brief NOR MSP DeInit
272 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
273 * the configuration information for NOR module.
276 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
278 /* NOTE : This function Should not be modified, when the callback is needed,
279 the HAL_NOR_MspDeInit could be implemented in the user file
284 * @brief NOR MSP Wait fro Ready/Busy signal
285 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
286 * the configuration information for NOR module.
287 * @param Timeout: Maximum timeout value
290 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
292 /* NOTE : This function Should not be modified, when the callback is needed,
293 the HAL_NOR_MspWait could be implemented in the user file
301 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
302 * @brief Input Output and memory control functions
305 ==============================================================================
306 ##### NOR Input and Output functions #####
307 ==============================================================================
309 This section provides functions allowing to use and control the NOR memory
316 * @brief Read NOR flash IDs
317 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
318 * the configuration information for NOR module.
319 * @param pNOR_ID : pointer to NOR ID structure
322 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
324 uint32_t deviceaddress = 0;
329 /* Check the NOR controller state */
330 if(hnor->State == HAL_NOR_STATE_BUSY)
335 /* Select the NOR device address */
336 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
338 deviceaddress = NOR_MEMORY_ADRESS1;
340 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
342 deviceaddress = NOR_MEMORY_ADRESS2;
344 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
346 deviceaddress = NOR_MEMORY_ADRESS3;
348 else /* FSMC_NORSRAM_BANK4 */
350 deviceaddress = NOR_MEMORY_ADRESS4;
353 /* Update the NOR controller state */
354 hnor->State = HAL_NOR_STATE_BUSY;
356 /* Send read ID command */
357 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
358 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
359 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
361 /* Read the NOR IDs */
362 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
363 pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
364 pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
365 pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
367 /* Check the NOR controller state */
368 hnor->State = HAL_NOR_STATE_READY;
370 /* Process unlocked */
377 * @brief Returns the NOR memory to Read mode.
378 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
379 * the configuration information for NOR module.
382 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
384 uint32_t deviceaddress = 0;
389 /* Check the NOR controller state */
390 if(hnor->State == HAL_NOR_STATE_BUSY)
395 /* Select the NOR device address */
396 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
398 deviceaddress = NOR_MEMORY_ADRESS1;
400 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
402 deviceaddress = NOR_MEMORY_ADRESS2;
404 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
406 deviceaddress = NOR_MEMORY_ADRESS3;
408 else /* FSMC_NORSRAM_BANK4 */
410 deviceaddress = NOR_MEMORY_ADRESS4;
413 __NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
415 /* Check the NOR controller state */
416 hnor->State = HAL_NOR_STATE_READY;
418 /* Process unlocked */
425 * @brief Read data from NOR memory
426 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
427 * the configuration information for NOR module.
428 * @param pAddress: pointer to Device address
429 * @param pData : pointer to read data
432 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
434 uint32_t deviceaddress = 0;
439 /* Check the NOR controller state */
440 if(hnor->State == HAL_NOR_STATE_BUSY)
445 /* Select the NOR device address */
446 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
448 deviceaddress = NOR_MEMORY_ADRESS1;
450 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
452 deviceaddress = NOR_MEMORY_ADRESS2;
454 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
456 deviceaddress = NOR_MEMORY_ADRESS3;
458 else /* FSMC_NORSRAM_BANK4 */
460 deviceaddress = NOR_MEMORY_ADRESS4;
463 /* Update the NOR controller state */
464 hnor->State = HAL_NOR_STATE_BUSY;
466 /* Send read data command */
467 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
468 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
469 __NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
472 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
474 /* Check the NOR controller state */
475 hnor->State = HAL_NOR_STATE_READY;
477 /* Process unlocked */
484 * @brief Program data to NOR memory
485 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
486 * the configuration information for NOR module.
487 * @param pAddress: Device address
488 * @param pData : pointer to the data to write
491 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
493 uint32_t deviceaddress = 0;
498 /* Check the NOR controller state */
499 if(hnor->State == HAL_NOR_STATE_BUSY)
504 /* Select the NOR device address */
505 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
507 deviceaddress = NOR_MEMORY_ADRESS1;
509 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
511 deviceaddress = NOR_MEMORY_ADRESS2;
513 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
515 deviceaddress = NOR_MEMORY_ADRESS3;
517 else /* FSMC_NORSRAM_BANK4 */
519 deviceaddress = NOR_MEMORY_ADRESS4;
522 /* Update the NOR controller state */
523 hnor->State = HAL_NOR_STATE_BUSY;
525 /* Send program data command */
526 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
527 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
528 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
531 __NOR_WRITE(pAddress, *pData);
533 /* Check the NOR controller state */
534 hnor->State = HAL_NOR_STATE_READY;
536 /* Process unlocked */
543 * @brief Reads a block of data from the FSMC NOR memory.
544 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
545 * the configuration information for NOR module.
546 * @param uwAddress: NOR memory internal address to read from.
547 * @param pData: pointer to the buffer that receives the data read from the
549 * @param uwBufferSize : number of Half word to read.
552 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
554 uint32_t deviceaddress = 0;
559 /* Check the NOR controller state */
560 if(hnor->State == HAL_NOR_STATE_BUSY)
565 /* Select the NOR device address */
566 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
568 deviceaddress = NOR_MEMORY_ADRESS1;
570 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
572 deviceaddress = NOR_MEMORY_ADRESS2;
574 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
576 deviceaddress = NOR_MEMORY_ADRESS3;
578 else /* FSMC_NORSRAM_BANK4 */
580 deviceaddress = NOR_MEMORY_ADRESS4;
583 /* Update the NOR controller state */
584 hnor->State = HAL_NOR_STATE_BUSY;
586 /* Send read data command */
587 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
588 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
589 __NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
592 while( uwBufferSize > 0)
594 *pData++ = *(__IO uint16_t *)uwAddress;
599 /* Check the NOR controller state */
600 hnor->State = HAL_NOR_STATE_READY;
602 /* Process unlocked */
609 * @brief Writes a half-word buffer to the FSMC NOR memory. This function
610 * must be used only with S29GL128P NOR memory.
611 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
612 * the configuration information for NOR module.
613 * @param uwAddress: NOR memory internal address from which the data
614 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
615 * 64 bytes boundary for example).
616 * @param pData: pointer to source data buffer.
617 * @param uwBufferSize: number of Half words to write.
618 * @note The maximum buffer size allowed is NOR memory dependent
619 * (can be 64 Bytes max for example).
622 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
624 uint16_t * p_currentaddress = (uint16_t *)NULL;
625 uint16_t * p_endaddress = (uint16_t *)NULL;
626 uint32_t lastloadedaddress = 0, deviceaddress = 0;
631 /* Check the NOR controller state */
632 if(hnor->State == HAL_NOR_STATE_BUSY)
637 /* Select the NOR device address */
638 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
640 deviceaddress = NOR_MEMORY_ADRESS1;
642 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
644 deviceaddress = NOR_MEMORY_ADRESS2;
646 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
648 deviceaddress = NOR_MEMORY_ADRESS3;
650 else /* FSMC_NORSRAM_BANK4 */
652 deviceaddress = NOR_MEMORY_ADRESS4;
655 /* Update the NOR controller state */
656 hnor->State = HAL_NOR_STATE_BUSY;
658 /* Initialize variables */
659 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
660 p_endaddress = p_currentaddress + (uwBufferSize-1);
661 lastloadedaddress = (uint32_t)(uwAddress);
663 /* Issue unlock command sequence */
664 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
665 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
667 /* Write Buffer Load Command */
668 __NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
669 __NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
671 /* Load Data into NOR Buffer */
672 while(p_currentaddress <= p_endaddress)
674 /* Store last loaded address & data value (for polling) */
675 lastloadedaddress = (uint32_t)p_currentaddress;
677 __NOR_WRITE(p_currentaddress, *pData++);
682 __NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
684 /* Check the NOR controller state */
685 hnor->State = HAL_NOR_STATE_READY;
687 /* Process unlocked */
695 * @brief Erase the specified block of the NOR memory
696 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
697 * the configuration information for NOR module.
698 * @param BlockAddress : Block to erase address
699 * @param Address: Device address
702 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
704 uint32_t deviceaddress = 0;
709 /* Check the NOR controller state */
710 if(hnor->State == HAL_NOR_STATE_BUSY)
715 /* Select the NOR device address */
716 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
718 deviceaddress = NOR_MEMORY_ADRESS1;
720 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
722 deviceaddress = NOR_MEMORY_ADRESS2;
724 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
726 deviceaddress = NOR_MEMORY_ADRESS3;
728 else /* FSMC_NORSRAM_BANK4 */
730 deviceaddress = NOR_MEMORY_ADRESS4;
733 /* Update the NOR controller state */
734 hnor->State = HAL_NOR_STATE_BUSY;
736 /* Send block erase command sequence */
737 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
738 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
739 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
740 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
741 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
742 __NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
744 /* Check the NOR memory status and update the controller state */
745 hnor->State = HAL_NOR_STATE_READY;
747 /* Process unlocked */
755 * @brief Erase the entire NOR chip.
756 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
757 * the configuration information for NOR module.
758 * @param Address : Device address
761 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
763 uint32_t deviceaddress = 0;
768 /* Check the NOR controller state */
769 if(hnor->State == HAL_NOR_STATE_BUSY)
774 /* Select the NOR device address */
775 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
777 deviceaddress = NOR_MEMORY_ADRESS1;
779 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
781 deviceaddress = NOR_MEMORY_ADRESS2;
783 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
785 deviceaddress = NOR_MEMORY_ADRESS3;
787 else /* FSMC_NORSRAM_BANK4 */
789 deviceaddress = NOR_MEMORY_ADRESS4;
792 /* Update the NOR controller state */
793 hnor->State = HAL_NOR_STATE_BUSY;
795 /* Send NOR chip erase command sequence */
796 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
797 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
798 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
799 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
800 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
801 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
803 /* Check the NOR memory status and update the controller state */
804 hnor->State = HAL_NOR_STATE_READY;
806 /* Process unlocked */
813 * @brief Read NOR flash CFI IDs
814 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
815 * the configuration information for NOR module.
816 * @param pNOR_CFI : pointer to NOR CFI IDs structure
819 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
821 uint32_t deviceaddress = 0;
826 /* Check the NOR controller state */
827 if(hnor->State == HAL_NOR_STATE_BUSY)
832 /* Select the NOR device address */
833 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
835 deviceaddress = NOR_MEMORY_ADRESS1;
837 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
839 deviceaddress = NOR_MEMORY_ADRESS2;
841 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
843 deviceaddress = NOR_MEMORY_ADRESS3;
845 else /* FSMC_NORSRAM_BANK4 */
847 deviceaddress = NOR_MEMORY_ADRESS4;
850 /* Update the NOR controller state */
851 hnor->State = HAL_NOR_STATE_BUSY;
853 /* Send read CFI query command */
854 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
856 /* read the NOR CFI information */
857 pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
858 pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
859 pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
860 pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
862 /* Check the NOR controller state */
863 hnor->State = HAL_NOR_STATE_READY;
865 /* Process unlocked */
875 /** @defgroup NOR_Exported_Functions_Group3 Control functions
876 * @brief management functions
879 ==============================================================================
880 ##### NOR Control functions #####
881 ==============================================================================
883 This subsection provides a set of functions allowing to control dynamically
891 * @brief Enables dynamically NOR write operation.
892 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
893 * the configuration information for NOR module.
896 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
901 /* Enable write operation */
902 FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
904 /* Update the NOR controller state */
905 hnor->State = HAL_NOR_STATE_READY;
907 /* Process unlocked */
914 * @brief Disables dynamically NOR write operation.
915 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
916 * the configuration information for NOR module.
919 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
924 /* Update the SRAM controller state */
925 hnor->State = HAL_NOR_STATE_BUSY;
927 /* Disable write operation */
928 FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
930 /* Update the NOR controller state */
931 hnor->State = HAL_NOR_STATE_PROTECTED;
933 /* Process unlocked */
943 /** @defgroup NOR_Exported_Functions_Group4 State functions
944 * @brief Peripheral State functions
947 ==============================================================================
948 ##### NOR State functions #####
949 ==============================================================================
951 This subsection permits to get in run-time the status of the NOR controller
959 * @brief return the NOR controller state
960 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
961 * the configuration information for NOR module.
962 * @retval NOR controller state
964 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
970 * @brief Returns the NOR operation status.
971 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
972 * the configuration information for NOR module.
973 * @param Address: Device address
974 * @param Timeout: NOR progamming Timeout
975 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
976 * or HAL_NOR_STATUS_TIMEOUT
978 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
980 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
981 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
982 uint32_t tickstart = 0;
984 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
985 HAL_NOR_MspWait(hnor, Timeout);
988 tickstart = HAL_GetTick();
989 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
991 /* Check for the Timeout */
992 if(Timeout != HAL_MAX_DELAY)
994 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
996 status = HAL_NOR_STATUS_TIMEOUT;
1000 /* Read NOR status register (DQ6 and DQ5) */
1001 tmp_sr1 = *(__IO uint16_t *)Address;
1002 tmp_sr2 = *(__IO uint16_t *)Address;
1004 /* If DQ6 did not toggle between the two reads then return NOR_Success */
1005 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
1007 return HAL_NOR_STATUS_SUCCESS;
1010 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
1012 status = HAL_NOR_STATUS_ONGOING;
1015 tmp_sr1 = *(__IO uint16_t *)Address;
1016 tmp_sr2 = *(__IO uint16_t *)Address;
1018 /* If DQ6 did not toggle between the two reads then return NOR_Success */
1019 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
1021 return HAL_NOR_STATUS_SUCCESS;
1023 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
1025 return HAL_NOR_STATUS_ERROR;
1029 /* Return the operation status */
1043 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
1044 #endif /* HAL_NOR_MODULE_ENABLED */
1050 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/