2 ******************************************************************************
3 * @file stm32f1xx_hal_sram.c
4 * @author MCD Application Team
6 * @date 15-December-2014
7 * @brief SRAM HAL module driver.
8 * This file provides a generic firmware to drive SRAM memories
9 * mounted as external device.
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
16 This driver is a generic layered driver which contains a set of APIs used to
17 control SRAM memories. It uses the FSMC layer functions to interface
19 The following sequence should be followed to configure the FSMC to interface
20 with SRAM/PSRAM memories:
22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
23 SRAM_HandleTypeDef hsram; and:
25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
26 values of the structure member.
28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
29 base register instance for NOR or SRAM device
31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
32 base register instance for NOR or SRAM extended mode
34 (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
35 mode timings; for example:
36 FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
37 and fill its fields with the allowed values of the structure member.
39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
40 performs the following sequence:
42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
43 (##) Control register configuration using the FSMC NORSRAM interface function
45 (##) Timing register configuration using the FSMC NORSRAM interface function
46 FSMC_NORSRAM_Timing_Init()
47 (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
48 FSMC_NORSRAM_Extended_Timing_Init()
49 (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
51 (#) At this stage you can perform read/write accesses from/to the memory connected
52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
60 (#) You can continuously monitor the SRAM device HAL state by calling the function
64 ******************************************************************************
67 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
69 * Redistribution and use in source and binary forms, with or without modification,
70 * are permitted provided that the following conditions are met:
71 * 1. Redistributions of source code must retain the above copyright notice,
72 * this list of conditions and the following disclaimer.
73 * 2. Redistributions in binary form must reproduce the above copyright notice,
74 * this list of conditions and the following disclaimer in the documentation
75 * and/or other materials provided with the distribution.
76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
77 * may be used to endorse or promote products derived from this software
78 * without specific prior written permission.
80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
91 ******************************************************************************
94 /* Includes ------------------------------------------------------------------*/
95 #include "stm32f1xx_hal.h"
97 /** @addtogroup STM32F1xx_HAL_Driver
101 #ifdef HAL_SRAM_MODULE_ENABLED
103 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
105 /** @defgroup SRAM SRAM
106 * @brief SRAM driver modules
109 /* Private typedef -----------------------------------------------------------*/
110 /* Private define ------------------------------------------------------------*/
111 /* Private macro -------------------------------------------------------------*/
112 /* Private variables ---------------------------------------------------------*/
113 /* Private function prototypes -----------------------------------------------*/
114 /* Exported functions --------------------------------------------------------*/
116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
121 * @brief Initialization and Configuration functions.
124 ==============================================================================
125 ##### SRAM Initialization and de_initialization functions #####
126 ==============================================================================
127 [..] This section provides functions allowing to initialize/de-initialize
135 * @brief Performs the SRAM device initialization sequence
136 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
137 * the configuration information for SRAM module.
138 * @param Timing: Pointer to SRAM control timing structure
139 * @param ExtTiming: Pointer to SRAM extended mode timing structure
142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
144 /* Check the SRAM handle parameter */
150 if(hsram->State == HAL_SRAM_STATE_RESET)
152 /* Allocate lock resource and initialize it */
153 hsram-> Lock = HAL_UNLOCKED;
155 /* Initialize the low level hardware (MSP) */
156 HAL_SRAM_MspInit(hsram);
159 /* Initialize SRAM control Interface */
160 FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
162 /* Initialize SRAM timing Interface */
163 FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
165 /* Initialize SRAM extended mode timing Interface */
166 FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
168 /* Enable the NORSRAM device */
169 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
175 * @brief Performs the SRAM device De-initialization sequence.
176 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
177 * the configuration information for SRAM module.
180 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
182 /* De-Initialize the low level hardware (MSP) */
183 HAL_SRAM_MspDeInit(hsram);
185 /* Configure the SRAM registers with their reset values */
186 FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
188 hsram->State = HAL_SRAM_STATE_RESET;
197 * @brief SRAM MSP Init.
198 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
199 * the configuration information for SRAM module.
202 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
204 /* NOTE : This function Should not be modified, when the callback is needed,
205 the HAL_SRAM_MspInit could be implemented in the user file
210 * @brief SRAM MSP DeInit.
211 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
212 * the configuration information for SRAM module.
215 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
217 /* NOTE : This function Should not be modified, when the callback is needed,
218 the HAL_SRAM_MspDeInit could be implemented in the user file
223 * @brief DMA transfer complete callback.
224 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
225 * the configuration information for SRAM module.
228 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
230 /* NOTE : This function Should not be modified, when the callback is needed,
231 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
236 * @brief DMA transfer complete error callback.
237 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
238 * the configuration information for SRAM module.
241 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
243 /* NOTE : This function Should not be modified, when the callback is needed,
244 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
252 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
253 * @brief Input Output and memory control functions
256 ==============================================================================
257 ##### SRAM Input and Output functions #####
258 ==============================================================================
260 This section provides functions allowing to use and control the SRAM memory
267 * @brief Reads 8-bit buffer from SRAM memory.
268 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
269 * the configuration information for SRAM module.
270 * @param pAddress: Pointer to read start address
271 * @param pDstBuffer: Pointer to destination buffer
272 * @param BufferSize: Size of the buffer to read from memory
275 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
277 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
282 /* Update the SRAM controller state */
283 hsram->State = HAL_SRAM_STATE_BUSY;
285 /* Read data from memory */
286 for(; BufferSize != 0; BufferSize--)
288 *pDstBuffer = *(__IO uint8_t *)psramaddress;
293 /* Update the SRAM controller state */
294 hsram->State = HAL_SRAM_STATE_READY;
296 /* Process unlocked */
303 * @brief Writes 8-bit buffer to SRAM memory.
304 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
305 * the configuration information for SRAM module.
306 * @param pAddress: Pointer to write start address
307 * @param pSrcBuffer: Pointer to source buffer to write
308 * @param BufferSize: Size of the buffer to write to memory
311 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
313 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
315 /* Check the SRAM controller state */
316 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
324 /* Update the SRAM controller state */
325 hsram->State = HAL_SRAM_STATE_BUSY;
327 /* Write data to memory */
328 for(; BufferSize != 0; BufferSize--)
330 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
335 /* Update the SRAM controller state */
336 hsram->State = HAL_SRAM_STATE_READY;
338 /* Process unlocked */
345 * @brief Reads 16-bit buffer from SRAM memory.
346 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
347 * the configuration information for SRAM module.
348 * @param pAddress: Pointer to read start address
349 * @param pDstBuffer: Pointer to destination buffer
350 * @param BufferSize: Size of the buffer to read from memory
353 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
355 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
360 /* Update the SRAM controller state */
361 hsram->State = HAL_SRAM_STATE_BUSY;
363 /* Read data from memory */
364 for(; BufferSize != 0; BufferSize--)
366 *pDstBuffer = *(__IO uint16_t *)psramaddress;
371 /* Update the SRAM controller state */
372 hsram->State = HAL_SRAM_STATE_READY;
374 /* Process unlocked */
381 * @brief Writes 16-bit buffer to SRAM memory.
382 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
383 * the configuration information for SRAM module.
384 * @param pAddress: Pointer to write start address
385 * @param pSrcBuffer: Pointer to source buffer to write
386 * @param BufferSize: Size of the buffer to write to memory
389 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
391 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
393 /* Check the SRAM controller state */
394 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
402 /* Update the SRAM controller state */
403 hsram->State = HAL_SRAM_STATE_BUSY;
405 /* Write data to memory */
406 for(; BufferSize != 0; BufferSize--)
408 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
413 /* Update the SRAM controller state */
414 hsram->State = HAL_SRAM_STATE_READY;
416 /* Process unlocked */
423 * @brief Reads 32-bit buffer from SRAM memory.
424 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
425 * the configuration information for SRAM module.
426 * @param pAddress: Pointer to read start address
427 * @param pDstBuffer: Pointer to destination buffer
428 * @param BufferSize: Size of the buffer to read from memory
431 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
436 /* Update the SRAM controller state */
437 hsram->State = HAL_SRAM_STATE_BUSY;
439 /* Read data from memory */
440 for(; BufferSize != 0; BufferSize--)
442 *pDstBuffer = *(__IO uint32_t *)pAddress;
447 /* Update the SRAM controller state */
448 hsram->State = HAL_SRAM_STATE_READY;
450 /* Process unlocked */
457 * @brief Writes 32-bit buffer to SRAM memory.
458 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
459 * the configuration information for SRAM module.
460 * @param pAddress: Pointer to write start address
461 * @param pSrcBuffer: Pointer to source buffer to write
462 * @param BufferSize: Size of the buffer to write to memory
465 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
467 /* Check the SRAM controller state */
468 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
476 /* Update the SRAM controller state */
477 hsram->State = HAL_SRAM_STATE_BUSY;
479 /* Write data to memory */
480 for(; BufferSize != 0; BufferSize--)
482 *(__IO uint32_t *)pAddress = *pSrcBuffer;
487 /* Update the SRAM controller state */
488 hsram->State = HAL_SRAM_STATE_READY;
490 /* Process unlocked */
497 * @brief Reads a Words data from the SRAM memory using DMA transfer.
498 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
499 * the configuration information for SRAM module.
500 * @param pAddress: Pointer to read start address
501 * @param pDstBuffer: Pointer to destination buffer
502 * @param BufferSize: Size of the buffer to read from memory
505 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
510 /* Update the SRAM controller state */
511 hsram->State = HAL_SRAM_STATE_BUSY;
513 /* Configure DMA user callbacks */
514 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
515 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
517 /* Enable the DMA Channel */
518 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
520 /* Update the SRAM controller state */
521 hsram->State = HAL_SRAM_STATE_READY;
523 /* Process unlocked */
530 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
531 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
532 * the configuration information for SRAM module.
533 * @param pAddress: Pointer to write start address
534 * @param pSrcBuffer: Pointer to source buffer to write
535 * @param BufferSize: Size of the buffer to write to memory
538 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
540 /* Check the SRAM controller state */
541 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
549 /* Update the SRAM controller state */
550 hsram->State = HAL_SRAM_STATE_BUSY;
552 /* Configure DMA user callbacks */
553 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
554 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
556 /* Enable the DMA Channel */
557 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
559 /* Update the SRAM controller state */
560 hsram->State = HAL_SRAM_STATE_READY;
562 /* Process unlocked */
572 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
573 * @brief Control functions
576 ==============================================================================
577 ##### SRAM Control functions #####
578 ==============================================================================
580 This subsection provides a set of functions allowing to control dynamically
588 * @brief Enables dynamically SRAM write operation.
589 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
590 * the configuration information for SRAM module.
593 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
598 /* Enable write operation */
599 FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
601 /* Update the SRAM controller state */
602 hsram->State = HAL_SRAM_STATE_READY;
604 /* Process unlocked */
611 * @brief Disables dynamically SRAM write operation.
612 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
613 * the configuration information for SRAM module.
616 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
621 /* Update the SRAM controller state */
622 hsram->State = HAL_SRAM_STATE_BUSY;
624 /* Disable write operation */
625 FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
627 /* Update the SRAM controller state */
628 hsram->State = HAL_SRAM_STATE_PROTECTED;
630 /* Process unlocked */
640 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
641 * @brief Peripheral State functions
644 ==============================================================================
645 ##### SRAM State functions #####
646 ==============================================================================
648 This subsection permits to get in run-time the status of the SRAM controller
656 * @brief Returns the SRAM controller state
657 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
658 * the configuration information for SRAM module.
661 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
677 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
678 #endif /* HAL_SRAM_MODULE_ENABLED */
684 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/