2 ******************************************************************************
3 * @file stm32f1xx_hal_tim.h
4 * @author MCD Application Team
6 * @date 15-December-2014
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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14 * are permitted provided that the following conditions are met:
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_TIM_H
40 #define __STM32F1xx_HAL_TIM_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
49 /** @addtogroup STM32F1xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
62 * @brief TIM Time base Configuration Structure definition
66 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
67 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
69 uint32_t CounterMode; /*!< Specifies the counter mode.
70 This parameter can be a value of @ref TIM_Counter_Mode */
72 uint32_t Period; /*!< Specifies the period value to be loaded into the active
73 Auto-Reload Register at the next update event.
74 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
76 uint32_t ClockDivision; /*!< Specifies the clock division.
77 This parameter can be a value of @ref TIM_ClockDivision */
79 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
80 reaches zero, an update event is generated and counting restarts
81 from the RCR value (N).
82 This means in PWM mode that (N+1) corresponds to:
83 - the number of PWM periods in edge-aligned mode
84 - the number of half PWM period in center-aligned mode
85 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
86 @note This parameter is valid only for TIM1 and TIM8. */
87 } TIM_Base_InitTypeDef;
90 * @brief TIM Output Compare Configuration Structure definition
94 uint32_t OCMode; /*!< Specifies the TIM mode.
95 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
97 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
98 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
100 uint32_t OCPolarity; /*!< Specifies the output polarity.
101 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
103 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
104 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
105 @note This parameter is valid only for TIM1 and TIM8. */
107 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
108 This parameter can be a value of @ref TIM_Output_Fast_State
109 @note This parameter is valid only in PWM1 and PWM2 mode. */
112 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
113 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
114 @note This parameter is valid only for TIM1 and TIM8. */
116 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
117 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
118 @note This parameter is valid only for TIM1 and TIM8. */
119 } TIM_OC_InitTypeDef;
122 * @brief TIM One Pulse Mode Configuration Structure definition
126 uint32_t OCMode; /*!< Specifies the TIM mode.
127 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
129 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
130 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
132 uint32_t OCPolarity; /*!< Specifies the output polarity.
133 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
135 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
136 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
137 @note This parameter is valid only for TIM1 and TIM8. */
139 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
140 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
141 @note This parameter is valid only for TIM1 and TIM8. */
143 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
144 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
145 @note This parameter is valid only for TIM1 and TIM8. */
147 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
150 uint32_t ICSelection; /*!< Specifies the input.
151 This parameter can be a value of @ref TIM_Input_Capture_Selection */
153 uint32_t ICFilter; /*!< Specifies the input capture filter.
154 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
155 } TIM_OnePulse_InitTypeDef;
159 * @brief TIM Input Capture Configuration Structure definition
163 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
164 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
166 uint32_t ICSelection; /*!< Specifies the input.
167 This parameter can be a value of @ref TIM_Input_Capture_Selection */
169 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
170 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
172 uint32_t ICFilter; /*!< Specifies the input capture filter.
173 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
174 } TIM_IC_InitTypeDef;
177 * @brief TIM Encoder Configuration Structure definition
181 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
182 This parameter can be a value of @ref TIM_Encoder_Mode */
184 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
185 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
187 uint32_t IC1Selection; /*!< Specifies the input.
188 This parameter can be a value of @ref TIM_Input_Capture_Selection */
190 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
191 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
193 uint32_t IC1Filter; /*!< Specifies the input capture filter.
194 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
196 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
197 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
199 uint32_t IC2Selection; /*!< Specifies the input.
200 This parameter can be a value of @ref TIM_Input_Capture_Selection */
202 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
203 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
205 uint32_t IC2Filter; /*!< Specifies the input capture filter.
206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
207 } TIM_Encoder_InitTypeDef;
211 * @brief TIM Clock Configuration Handle Structure definition
215 uint32_t ClockSource; /*!< TIM clock sources
216 This parameter can be a value of @ref TIM_Clock_Source */
217 uint32_t ClockPolarity; /*!< TIM clock polarity
218 This parameter can be a value of @ref TIM_Clock_Polarity */
219 uint32_t ClockPrescaler; /*!< TIM clock prescaler
220 This parameter can be a value of @ref TIM_Clock_Prescaler */
221 uint32_t ClockFilter; /*!< TIM clock filter
222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
223 }TIM_ClockConfigTypeDef;
226 * @brief TIM Clear Input Configuration Handle Structure definition
230 uint32_t ClearInputState; /*!< TIM clear Input state
231 This parameter can be ENABLE or DISABLE */
232 uint32_t ClearInputSource; /*!< TIM clear Input sources
233 This parameter can be a value of @ref TIM_ClearInput_Source */
234 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
235 This parameter can be a value of @ref TIM_ClearInput_Polarity */
236 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
237 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
238 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
239 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
240 }TIM_ClearInputConfigTypeDef;
243 * @brief TIM Slave configuration Structure definition
246 uint32_t SlaveMode; /*!< Slave mode selection
247 This parameter can be a value of @ref TIM_Slave_Mode */
248 uint32_t InputTrigger; /*!< Input Trigger source
249 This parameter can be a value of @ref TIM_Trigger_Selection */
250 uint32_t TriggerPolarity; /*!< Input Trigger polarity
251 This parameter can be a value of @ref TIM_Trigger_Polarity */
252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
253 This parameter can be a value of @ref TIM_Trigger_Prescaler */
254 uint32_t TriggerFilter; /*!< Input trigger filter
255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
257 }TIM_SlaveConfigTypeDef;
260 * @brief HAL State structures definition
264 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
265 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
266 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
267 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
268 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
269 }HAL_TIM_StateTypeDef;
272 * @brief HAL Active channel structures definition
276 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
277 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
278 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
279 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
280 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
281 }HAL_TIM_ActiveChannel;
284 * @brief TIM Time Base Handle Structure definition
288 TIM_TypeDef *Instance; /*!< Register base address */
289 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
290 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
291 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
292 This array is accessed by a @ref TIM_DMA_Handle_index */
293 HAL_LockTypeDef Lock; /*!< Locking object */
294 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
301 /* Exported constants --------------------------------------------------------*/
302 /** @defgroup TIM_Exported_Constants TIM Exported Constants
306 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
309 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
310 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
311 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
316 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
319 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
320 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
325 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
328 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
329 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
330 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
331 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
336 /** @defgroup TIM_Counter_Mode TIM Counter Mode
339 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
340 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
341 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
342 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
343 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
348 /** @defgroup TIM_ClockDivision TIM ClockDivision
351 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
352 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
353 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
358 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
361 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
362 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
363 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
364 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
365 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
366 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
367 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
368 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
373 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
376 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
377 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
382 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
385 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
386 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
391 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
394 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
395 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
400 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
403 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
404 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
409 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
412 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
413 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
418 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
421 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
422 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
427 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
430 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
431 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
436 /** @defgroup TIM_Channel TIM Channel
439 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
440 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
441 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
442 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
443 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
448 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
451 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
452 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
453 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
458 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
461 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
462 connected to IC1, IC2, IC3 or IC4, respectively */
463 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
464 connected to IC2, IC1, IC4 or IC3, respectively */
465 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
470 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
473 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
474 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
475 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
476 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
481 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
484 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
485 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
490 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
493 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
494 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
495 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
500 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
503 #define TIM_IT_UPDATE (TIM_DIER_UIE)
504 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
505 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
506 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
507 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
508 #define TIM_IT_COM (TIM_DIER_COMIE)
509 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
510 #define TIM_IT_BREAK (TIM_DIER_BIE)
515 /** @defgroup TIM_Commutation_Source TIM Commutation Source
518 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
519 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
525 /** @defgroup TIM_DMA_sources TIM DMA Sources
528 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
529 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
530 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
531 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
532 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
533 #define TIM_DMA_COM (TIM_DIER_COMDE)
534 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
539 /** @defgroup TIM_Event_Source TIM Event Source
542 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
543 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
544 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
545 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
546 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
547 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
548 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
549 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
554 /** @defgroup TIM_Flag_definition TIM Flag Definition
557 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
558 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
559 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
560 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
561 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
562 #define TIM_FLAG_COM (TIM_SR_COMIF)
563 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
564 #define TIM_FLAG_BREAK (TIM_SR_BIF)
565 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
566 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
567 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
568 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
573 /** @defgroup TIM_Clock_Source TIM Clock Source
576 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
577 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
578 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
579 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
580 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
581 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
582 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
583 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
584 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
585 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
590 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
593 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
594 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
595 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
596 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
597 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
602 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
605 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
606 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
607 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
608 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
613 /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
616 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
617 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
618 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
623 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
626 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
627 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
632 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
635 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
636 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
637 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
638 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
643 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
646 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
647 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
652 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
655 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
656 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
661 /** @defgroup TIM_Lock_level TIM Lock level
664 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
665 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
666 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
667 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
672 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
675 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
676 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
681 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
684 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
685 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
689 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
692 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
693 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
698 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
701 #define TIM_TRGO_RESET ((uint32_t)0x0000)
702 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
703 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
704 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
705 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
706 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
707 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
708 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
713 /** @defgroup TIM_Slave_Mode TIM Slave Mode
716 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
717 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
718 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
719 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
720 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
725 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
728 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
729 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
734 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
737 #define TIM_TS_ITR0 ((uint32_t)0x0000)
738 #define TIM_TS_ITR1 ((uint32_t)0x0010)
739 #define TIM_TS_ITR2 ((uint32_t)0x0020)
740 #define TIM_TS_ITR3 ((uint32_t)0x0030)
741 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
742 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
743 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
744 #define TIM_TS_ETRF ((uint32_t)0x0070)
745 #define TIM_TS_NONE ((uint32_t)0xFFFF)
750 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
753 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
754 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
755 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
756 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
757 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
762 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
765 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
766 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
767 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
768 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
773 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
776 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
777 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
782 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
785 #define TIM_DMABASE_CR1 (0x00000000)
786 #define TIM_DMABASE_CR2 (0x00000001)
787 #define TIM_DMABASE_SMCR (0x00000002)
788 #define TIM_DMABASE_DIER (0x00000003)
789 #define TIM_DMABASE_SR (0x00000004)
790 #define TIM_DMABASE_EGR (0x00000005)
791 #define TIM_DMABASE_CCMR1 (0x00000006)
792 #define TIM_DMABASE_CCMR2 (0x00000007)
793 #define TIM_DMABASE_CCER (0x00000008)
794 #define TIM_DMABASE_CNT (0x00000009)
795 #define TIM_DMABASE_PSC (0x0000000A)
796 #define TIM_DMABASE_ARR (0x0000000B)
797 #define TIM_DMABASE_RCR (0x0000000C)
798 #define TIM_DMABASE_CCR1 (0x0000000D)
799 #define TIM_DMABASE_CCR2 (0x0000000E)
800 #define TIM_DMABASE_CCR3 (0x0000000F)
801 #define TIM_DMABASE_CCR4 (0x00000010)
802 #define TIM_DMABASE_BDTR (0x00000011)
803 #define TIM_DMABASE_DCR (0x00000012)
808 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
811 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
812 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
813 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
814 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
815 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
816 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
817 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
818 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
819 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
820 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
821 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
822 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
823 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
824 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
825 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
826 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
827 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
828 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
833 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
836 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
837 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
838 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
839 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
840 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
841 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
842 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
847 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
850 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
851 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
852 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
853 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
862 /* Private Constants -----------------------------------------------------------*/
863 /** @defgroup TIM_Private_Constants TIM Private Constants
867 /* The counter of a timer instance is disabled only if all the CCx
868 channels have been disabled */
869 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
871 /* The counter of a timer instance is disabled only if all the CCx and CCxN
872 channels have been disabled */
873 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
874 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
880 /* Private Macros -----------------------------------------------------------*/
881 /** @defgroup TIM_Private_Macros TIM Private Macros
885 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
886 ((MODE) == TIM_COUNTERMODE_DOWN) || \
887 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
888 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
889 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
891 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
892 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
893 ((DIV) == TIM_CLOCKDIVISION_DIV4))
895 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
896 ((MODE) == TIM_OCMODE_PWM2))
898 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
899 ((MODE) == TIM_OCMODE_ACTIVE) || \
900 ((MODE) == TIM_OCMODE_INACTIVE) || \
901 ((MODE) == TIM_OCMODE_TOGGLE) || \
902 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
903 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
905 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
906 ((STATE) == TIM_OCFAST_ENABLE))
908 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
909 ((POLARITY) == TIM_OCPOLARITY_LOW))
911 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
912 ((POLARITY) == TIM_OCNPOLARITY_LOW))
914 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
915 ((STATE) == TIM_OCIDLESTATE_RESET))
917 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
918 ((STATE) == TIM_OCNIDLESTATE_RESET))
920 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
921 ((CHANNEL) == TIM_CHANNEL_2) || \
922 ((CHANNEL) == TIM_CHANNEL_3) || \
923 ((CHANNEL) == TIM_CHANNEL_4) || \
924 ((CHANNEL) == TIM_CHANNEL_ALL))
926 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
927 ((CHANNEL) == TIM_CHANNEL_2))
929 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
930 ((CHANNEL) == TIM_CHANNEL_2) || \
931 ((CHANNEL) == TIM_CHANNEL_3))
933 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
934 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
935 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
937 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
938 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
939 ((SELECTION) == TIM_ICSELECTION_TRC))
941 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
942 ((PRESCALER) == TIM_ICPSC_DIV2) || \
943 ((PRESCALER) == TIM_ICPSC_DIV4) || \
944 ((PRESCALER) == TIM_ICPSC_DIV8))
946 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
947 ((MODE) == TIM_OPMODE_REPETITIVE))
949 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
950 ((MODE) == TIM_ENCODERMODE_TI2) || \
951 ((MODE) == TIM_ENCODERMODE_TI12))
953 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
955 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
957 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
958 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
959 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
960 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
961 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
962 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
963 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
964 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
965 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
966 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
968 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
969 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
970 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
971 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
972 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
974 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
975 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
976 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
977 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
979 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
981 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
982 ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
983 ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
985 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
986 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
988 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
989 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
990 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
991 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
993 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
995 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
996 ((STATE) == TIM_OSSR_DISABLE))
998 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
999 ((STATE) == TIM_OSSI_DISABLE))
1001 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
1002 ((LEVEL) == TIM_LOCKLEVEL_1) || \
1003 ((LEVEL) == TIM_LOCKLEVEL_2) || \
1004 ((LEVEL) == TIM_LOCKLEVEL_3))
1006 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
1007 ((STATE) == TIM_BREAK_DISABLE))
1009 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
1010 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
1012 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1013 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
1015 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
1016 ((SOURCE) == TIM_TRGO_ENABLE) || \
1017 ((SOURCE) == TIM_TRGO_UPDATE) || \
1018 ((SOURCE) == TIM_TRGO_OC1) || \
1019 ((SOURCE) == TIM_TRGO_OC1REF) || \
1020 ((SOURCE) == TIM_TRGO_OC2REF) || \
1021 ((SOURCE) == TIM_TRGO_OC3REF) || \
1022 ((SOURCE) == TIM_TRGO_OC4REF))
1024 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
1025 ((MODE) == TIM_SLAVEMODE_GATED) || \
1026 ((MODE) == TIM_SLAVEMODE_RESET) || \
1027 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
1028 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
1030 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
1031 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
1033 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1034 ((SELECTION) == TIM_TS_ITR1) || \
1035 ((SELECTION) == TIM_TS_ITR2) || \
1036 ((SELECTION) == TIM_TS_ITR3) || \
1037 ((SELECTION) == TIM_TS_TI1F_ED) || \
1038 ((SELECTION) == TIM_TS_TI1FP1) || \
1039 ((SELECTION) == TIM_TS_TI2FP2) || \
1040 ((SELECTION) == TIM_TS_ETRF))
1042 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1043 ((SELECTION) == TIM_TS_ITR1) || \
1044 ((SELECTION) == TIM_TS_ITR2) || \
1045 ((SELECTION) == TIM_TS_ITR3) || \
1046 ((SELECTION) == TIM_TS_NONE))
1048 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1049 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1050 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
1051 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
1052 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1054 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
1055 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
1056 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
1057 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
1059 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
1061 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
1062 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
1064 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
1065 ((BASE) == TIM_DMABASE_CR2) || \
1066 ((BASE) == TIM_DMABASE_SMCR) || \
1067 ((BASE) == TIM_DMABASE_DIER) || \
1068 ((BASE) == TIM_DMABASE_SR) || \
1069 ((BASE) == TIM_DMABASE_EGR) || \
1070 ((BASE) == TIM_DMABASE_CCMR1) || \
1071 ((BASE) == TIM_DMABASE_CCMR2) || \
1072 ((BASE) == TIM_DMABASE_CCER) || \
1073 ((BASE) == TIM_DMABASE_CNT) || \
1074 ((BASE) == TIM_DMABASE_PSC) || \
1075 ((BASE) == TIM_DMABASE_ARR) || \
1076 ((BASE) == TIM_DMABASE_RCR) || \
1077 ((BASE) == TIM_DMABASE_CCR1) || \
1078 ((BASE) == TIM_DMABASE_CCR2) || \
1079 ((BASE) == TIM_DMABASE_CCR3) || \
1080 ((BASE) == TIM_DMABASE_CCR4) || \
1081 ((BASE) == TIM_DMABASE_BDTR) || \
1082 ((BASE) == TIM_DMABASE_DCR))
1084 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1085 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1086 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1087 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1088 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1089 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1090 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1091 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1092 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1093 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1094 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1095 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1096 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1097 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1098 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1099 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1100 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1101 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
1103 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
1105 /** @brief Set TIM IC prescaler
1106 * @param __HANDLE__: TIM handle
1107 * @param __CHANNEL__: specifies TIM Channel
1108 * @param __ICPSC__: specifies the prescaler value.
1111 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1112 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1113 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
1114 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1115 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
1117 /** @brief Reset TIM IC prescaler
1118 * @param __HANDLE__: TIM handle
1119 * @param __CHANNEL__: specifies TIM Channel
1122 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1123 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
1124 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
1125 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
1126 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
1129 /** @brief Set TIM IC polarity
1130 * @param __HANDLE__: TIM handle
1131 * @param __CHANNEL__: specifies TIM Channel
1132 * @param __POLARITY__: specifies TIM Channel Polarity
1135 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1136 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1137 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
1138 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
1139 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
1141 /** @brief Reset TIM IC polarity
1142 * @param __HANDLE__: TIM handle
1143 * @param __CHANNEL__: specifies TIM Channel
1146 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1147 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1148 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1149 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1150 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
1156 /* Private Functions --------------------------------------------------------*/
1157 /** @addtogroup TIM_Private_Functions
1160 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1161 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1162 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1163 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1164 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1165 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1166 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1171 /* Exported macros -----------------------------------------------------------*/
1172 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1176 /** @brief Reset TIM handle state
1177 * @param __HANDLE__: TIM handle.
1180 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1183 * @brief Enable the TIM peripheral.
1184 * @param __HANDLE__: TIM handle
1187 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1190 * @brief Enable the TIM main Output.
1191 * @param __HANDLE__: TIM handle
1194 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1197 * @brief Disable the TIM peripheral.
1198 * @param __HANDLE__: TIM handle
1201 #define __HAL_TIM_DISABLE(__HANDLE__) \
1203 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
1205 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
1207 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1211 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
1212 channels have been disabled */
1214 * @brief Disable the TIM main Output.
1215 * @param __HANDLE__: TIM handle
1217 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
1219 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1221 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
1223 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
1225 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1231 * @brief Enables the specified TIM interrupt.
1232 * @param __HANDLE__: specifies the TIM Handle.
1233 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
1234 * This parameter can be one of the following values:
1235 * @arg TIM_IT_UPDATE: Update interrupt
1236 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1237 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1238 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1239 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1240 * @arg TIM_IT_COM: Commutation interrupt
1241 * @arg TIM_IT_TRIGGER: Trigger interrupt
1242 * @arg TIM_IT_BREAK: Break interrupt
1245 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1248 * @brief Disables the specified TIM interrupt.
1249 * @param __HANDLE__: specifies the TIM Handle.
1250 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
1251 * This parameter can be one of the following values:
1252 * @arg TIM_IT_UPDATE: Update interrupt
1253 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1254 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1255 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1256 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1257 * @arg TIM_IT_COM: Commutation interrupt
1258 * @arg TIM_IT_TRIGGER: Trigger interrupt
1259 * @arg TIM_IT_BREAK: Break interrupt
1262 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1265 * @brief Enables the specified DMA request.
1266 * @param __HANDLE__: specifies the TIM Handle.
1267 * @param __DMA__: specifies the TIM DMA request to enable.
1268 * This parameter can be one of the following values:
1269 * @arg TIM_DMA_UPDATE: Update DMA request
1270 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1271 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1272 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1273 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1274 * @arg TIM_DMA_COM: Commutation DMA request
1275 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1278 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1281 * @brief Disables the specified DMA request.
1282 * @param __HANDLE__: specifies the TIM Handle.
1283 * @param __DMA__: specifies the TIM DMA request to disable.
1284 * This parameter can be one of the following values:
1285 * @arg TIM_DMA_UPDATE: Update DMA request
1286 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1287 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1288 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1289 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1290 * @arg TIM_DMA_COM: Commutation DMA request
1291 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1294 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1297 * @brief Checks whether the specified TIM interrupt flag is set or not.
1298 * @param __HANDLE__: specifies the TIM Handle.
1299 * @param __FLAG__: specifies the TIM interrupt flag to check.
1300 * This parameter can be one of the following values:
1301 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1302 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1303 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1304 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1305 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1306 * @arg TIM_FLAG_COM: Commutation interrupt flag
1307 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1308 * @arg TIM_FLAG_BREAK: Break interrupt flag
1309 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1310 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1311 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1312 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1313 * @retval The new state of __FLAG__ (TRUE or FALSE).
1315 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1318 * @brief Clears the specified TIM interrupt flag.
1319 * @param __HANDLE__: specifies the TIM Handle.
1320 * @param __FLAG__: specifies the TIM interrupt flag to clear.
1321 * This parameter can be one of the following values:
1322 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1323 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1324 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1325 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1326 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1327 * @arg TIM_FLAG_COM: Commutation interrupt flag
1328 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1329 * @arg TIM_FLAG_BREAK: Break interrupt flag
1330 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1331 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1332 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1333 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1334 * @retval The new state of __FLAG__ (TRUE or FALSE).
1336 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1339 * @brief Checks whether the specified TIM interrupt has occurred or not.
1340 * @param __HANDLE__: TIM handle
1341 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
1342 * @retval The state of TIM_IT (SET or RESET).
1344 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1347 * @brief Clear the TIM interrupt pending bits
1348 * @param __HANDLE__: TIM handle
1349 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1352 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1355 * @brief Indicates whether or not the TIM Counter is used as downcounter
1356 * @param __HANDLE__: TIM handle.
1357 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1358 * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
1361 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
1364 * @brief Sets the TIM active prescaler register value on update event.
1365 * @param __HANDLE__: TIM handle.
1366 * @param __PRESC__: specifies the active prescaler register new value.
1369 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1372 * @brief Sets the TIM Capture Compare Register value on runtime without
1373 * calling another time ConfigChannel function.
1374 * @param __HANDLE__: TIM handle.
1375 * @param __CHANNEL__ : TIM Channels to be configured.
1376 * This parameter can be one of the following values:
1377 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1378 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1379 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1380 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1381 * @param __COMPARE__: specifies the Capture Compare register new value.
1384 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1385 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
1388 * @brief Gets the TIM Capture Compare Register value on runtime
1389 * @param __HANDLE__: TIM handle.
1390 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
1391 * This parameter can be one of the following values:
1392 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1393 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1394 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1395 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1398 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1399 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
1402 * @brief Sets the TIM Counter Register value on runtime.
1403 * @param __HANDLE__: TIM handle.
1404 * @param __COUNTER__: specifies the Counter register new value.
1407 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1410 * @brief Gets the TIM Counter Register value on runtime.
1411 * @param __HANDLE__: TIM handle.
1414 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
1415 ((__HANDLE__)->Instance->CNT)
1418 * @brief Sets the TIM Autoreload Register value on runtime without calling
1419 * another time any Init function.
1420 * @param __HANDLE__: TIM handle.
1421 * @param __AUTORELOAD__: specifies the Counter register new value.
1424 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1426 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1427 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1431 * @brief Gets the TIM Autoreload Register value on runtime
1432 * @param __HANDLE__: TIM handle.
1435 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
1436 ((__HANDLE__)->Instance->ARR)
1439 * @brief Sets the TIM Clock Division value on runtime without calling
1440 * another time any Init function.
1441 * @param __HANDLE__: TIM handle.
1442 * @param __CKD__: specifies the clock division value.
1443 * This parameter can be one of the following value:
1444 * @arg TIM_CLOCKDIVISION_DIV1
1445 * @arg TIM_CLOCKDIVISION_DIV2
1446 * @arg TIM_CLOCKDIVISION_DIV4
1449 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1451 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1452 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1453 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1457 * @brief Gets the TIM Clock Division value on runtime
1458 * @param __HANDLE__: TIM handle.
1461 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
1462 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1465 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1466 * another time HAL_TIM_IC_ConfigChannel() function.
1467 * @param __HANDLE__: TIM handle.
1468 * @param __CHANNEL__ : TIM Channels to be configured.
1469 * This parameter can be one of the following values:
1470 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1471 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1472 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1473 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1474 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1475 * This parameter can be one of the following values:
1476 * @arg TIM_ICPSC_DIV1: no prescaler
1477 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1478 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1479 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1482 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1484 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1485 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1489 * @brief Gets the TIM Input Capture prescaler on runtime
1490 * @param __HANDLE__: TIM handle.
1491 * @param __CHANNEL__: TIM Channels to be configured.
1492 * This parameter can be one of the following values:
1493 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1494 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1495 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1496 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1499 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1500 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1501 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1502 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1503 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1506 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
1507 * @param __HANDLE__: TIM handle.
1508 * @note When the USR bit of the TIMx_CR1 register is set, only counter
1509 * overflow/underflow generates an update interrupt or DMA request (if
1513 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1514 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1517 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
1518 * @param __HANDLE__: TIM handle.
1519 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
1520 * following events generate an update interrupt or DMA request (if
1522 * (+) Counter overflow/underflow
1523 * (+) Setting the UG bit
1524 * (+) Update generation through the slave mode controller
1527 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1528 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1531 * @brief Sets the TIM Capture x input polarity on runtime.
1532 * @param __HANDLE__: TIM handle.
1533 * @param __CHANNEL__: TIM Channels to be configured.
1534 * This parameter can be one of the following values:
1535 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1536 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1537 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1538 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1539 * @param __POLARITY__: Polarity for TIx source
1540 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1541 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1542 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1543 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
1546 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1548 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1549 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1556 /* Include TIM HAL Extension module */
1557 #include "stm32f1xx_hal_tim_ex.h"
1559 /* Exported functions --------------------------------------------------------*/
1560 /** @addtogroup TIM_Exported_Functions
1564 /** @addtogroup TIM_Exported_Functions_Group1
1567 /* Time Base functions ********************************************************/
1568 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1569 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1570 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1571 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1572 /* Blocking mode: Polling */
1573 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1574 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1575 /* Non-Blocking mode: Interrupt */
1576 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1577 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1578 /* Non-Blocking mode: DMA */
1579 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1580 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1585 /** @addtogroup TIM_Exported_Functions_Group2
1588 /* Timer Output Compare functions **********************************************/
1589 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1590 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1591 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1592 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1593 /* Blocking mode: Polling */
1594 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1595 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1596 /* Non-Blocking mode: Interrupt */
1597 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1598 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1599 /* Non-Blocking mode: DMA */
1600 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1601 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1607 /** @addtogroup TIM_Exported_Functions_Group3
1610 /* Timer PWM functions *********************************************************/
1611 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1612 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1613 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1614 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1615 /* Blocking mode: Polling */
1616 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1617 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1618 /* Non-Blocking mode: Interrupt */
1619 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1620 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1621 /* Non-Blocking mode: DMA */
1622 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1623 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1628 /** @addtogroup TIM_Exported_Functions_Group4
1631 /* Timer Input Capture functions ***********************************************/
1632 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1633 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1634 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1635 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1636 /* Blocking mode: Polling */
1637 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1638 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1639 /* Non-Blocking mode: Interrupt */
1640 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1641 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1642 /* Non-Blocking mode: DMA */
1643 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1644 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1649 /** @addtogroup TIM_Exported_Functions_Group5
1652 /* Timer One Pulse functions ***************************************************/
1653 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1654 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1655 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1656 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1657 /* Blocking mode: Polling */
1658 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1659 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1660 /* Non-Blocking mode: Interrupt */
1661 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1662 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1667 /** @addtogroup TIM_Exported_Functions_Group6
1670 /* Timer Encoder functions *****************************************************/
1671 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1672 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1673 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1674 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1675 /* Blocking mode: Polling */
1676 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1677 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1678 /* Non-Blocking mode: Interrupt */
1679 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1680 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1681 /* Non-Blocking mode: DMA */
1682 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1683 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1689 /** @addtogroup TIM_Exported_Functions_Group7
1692 /* Interrupt Handler functions **********************************************/
1693 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1698 /** @addtogroup TIM_Exported_Functions_Group8
1701 /* Control functions *********************************************************/
1702 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1703 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1704 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1705 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1706 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1707 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1708 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1709 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1710 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1711 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1712 uint32_t *BurstBuffer, uint32_t BurstLength);
1713 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1714 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1715 uint32_t *BurstBuffer, uint32_t BurstLength);
1716 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1717 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1718 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1724 /** @addtogroup TIM_Exported_Functions_Group9
1727 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1728 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1729 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1730 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1731 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1732 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1733 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1738 /** @addtogroup TIM_Exported_Functions_Group10
1741 /* Peripheral State functions **************************************************/
1742 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1743 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1744 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1745 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1746 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1747 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1769 #endif /* __STM32F1xx_HAL_TIM_H */
1771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/