1 /*******************************************************************************
2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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24 * Products, Inc. Branding Policy.
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31 *******************************************************************************
34 #ifndef _MXC_SPI_REGS_H
35 #define _MXC_SPI_REGS_H
49 /* Offset Register Description
50 ====== ============================================ */
52 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
53 __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
54 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
55 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
56 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
57 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
58 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
59 __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
63 * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
68 __O uint16_t txfifo_16;
69 __O uint32_t txfifo_32;
71 } mxc_spi_txfifo_regs_t;
74 * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
79 __I uint16_t rxfifo_16;
80 __I uint32_t rxfifo_32;
82 } mxc_spi_rxfifo_regs_t;
85 Register offsets for module SPI.
87 #define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
88 #define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
89 #define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
90 #define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
91 #define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
92 #define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
93 #define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
95 #define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
96 #define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
99 Field positions and masks for module SPI.
101 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
102 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
103 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
104 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
105 #define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
106 #define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
107 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
108 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
109 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
110 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
111 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
112 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
113 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
114 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
115 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
116 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
117 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
118 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
119 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
120 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
122 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
123 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
124 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
125 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
127 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
128 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
129 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
130 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
131 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
132 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
133 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
134 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
135 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
136 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
137 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
138 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
139 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
140 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
141 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
142 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
143 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
144 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
145 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
146 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
148 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
149 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
150 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
151 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
152 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
153 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
154 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
155 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
157 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
158 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
159 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
160 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
161 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
162 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
163 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
164 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
166 #define MXC_F_SPI_INTFL_TX_STALLED_POS 0
167 #define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
168 #define MXC_F_SPI_INTFL_RX_STALLED_POS 1
169 #define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
170 #define MXC_F_SPI_INTFL_TX_READY_POS 2
171 #define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
172 #define MXC_F_SPI_INTFL_RX_DONE_POS 3
173 #define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
174 #define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
175 #define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
176 #define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
177 #define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
179 #define MXC_F_SPI_INTEN_TX_STALLED_POS 0
180 #define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
181 #define MXC_F_SPI_INTEN_RX_STALLED_POS 1
182 #define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
183 #define MXC_F_SPI_INTEN_TX_READY_POS 2
184 #define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
185 #define MXC_F_SPI_INTEN_RX_DONE_POS 3
186 #define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
187 #define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
188 #define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
189 #define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
190 #define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
192 #define MXC_F_SPI_FIFO_DIR_POS 0
193 #define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
194 #define MXC_F_SPI_FIFO_UNIT_POS 2
195 #define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
196 #define MXC_F_SPI_FIFO_SIZE_POS 4
197 #define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
198 #define MXC_F_SPI_FIFO_WIDTH_POS 9
199 #define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
200 #define MXC_F_SPI_FIFO_ALT_POS 11
201 #define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
202 #define MXC_F_SPI_FIFO_FLOW_POS 12
203 #define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
204 #define MXC_F_SPI_FIFO_DASS_POS 13
205 #define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
215 #endif /* _MXC_SPI_REGS_H */