1 /******************************************************************************
2 * @file system_LPC11Uxx.c
3 * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
4 * for the NXP LPC13xx Device Series
6 * @date 24. November 2010
9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
13 * processor based microcontrollers. This file can be freely distributed
14 * within development tools that are supporting such ARM based processors.
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 ******************************************************************************/
30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
33 /*--------------------- Clock Configuration ----------------------------------
35 // <e> Clock Configuration
36 // <h> System Oscillator Control Register (SYSOSCCTRL)
37 // <o1.0> BYPASS: System Oscillator Bypass Enable
38 // <i> If enabled then PLL input (sys_osc_clk) is fed
39 // <i> directly from XTALIN and XTALOUT pins.
40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
41 // <i> Determines frequency range for Low-power oscillator.
46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
69 // <h> System PLL Control Register (SYSPLLCTRL)
70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
73 // <o3.0..4> MSEL: Feedback Divider Selection
76 // <o3.5..6> PSEL: Post Divider Selection
83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
84 // <o4.0..1> SEL: System PLL Clock Source
85 // <0=> IRC Oscillator
86 // <1=> System Oscillator
91 // <h> Main Clock Source Select Register (MAINCLKSEL)
92 // <o5.0..1> SEL: Clock Source for Main Clock
93 // <0=> IRC Oscillator
94 // <1=> Input Clock to System PLL
95 // <2=> WDT Oscillator
96 // <3=> System PLL Clock Out
99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
100 // <o6.0..7> DIV: System AHB Clock Divider
101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
102 // <i> 0 = is disabled
106 // <h> USB PLL Control Register (USBPLLCTRL)
107 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
108 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
109 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
110 // <o7.0..4> MSEL: Feedback Divider Selection
113 // <o7.5..6> PSEL: Post Divider Selection
120 // <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
121 // <o8.0..1> SEL: USB PLL Clock Source
122 // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
123 // <0=> IRC Oscillator
124 // <1=> System Oscillator
129 // <h> USB Clock Source Select Register (USBCLKSEL)
130 // <o9.0..1> SEL: System PLL Clock Source
137 // <h> USB Clock Divider Register (USBCLKDIV)
138 // <o10.0..7> DIV: USB Clock Divider
139 // <i> Divides USB clock to 48 MHz.
140 // <i> 0 = is disabled
145 #define CLOCK_SETUP 1
146 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
147 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
148 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
149 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
150 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
151 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
152 #define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
153 #define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
154 #define USBCLKSEL_Val 0x00000000 // Reset: 0x000
155 #define USBCLKDIV_Val 0x00000001 // Reset: 0x001
158 //-------- <<< end of configuration section >>> ------------------------------
161 /*----------------------------------------------------------------------------
162 Check the register settings
163 *----------------------------------------------------------------------------*/
164 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
165 #define CHECK_RSVD(val, mask) (val & mask)
167 /* Clock Configuration -------------------------------------------------------*/
168 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
169 #error "SYSOSCCTRL: Invalid values of reserved bits!"
172 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
173 #error "WDTOSCCTRL: Invalid values of reserved bits!"
176 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
177 #error "SYSPLLCLKSEL: Value out of range!"
180 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
181 #error "SYSPLLCTRL: Invalid values of reserved bits!"
184 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
185 #error "MAINCLKSEL: Invalid values of reserved bits!"
188 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
189 #error "SYSAHBCLKDIV: Value out of range!"
192 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
193 #error "USBPLLCLKSEL: Value out of range!"
196 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
197 #error "USBPLLCTRL: Invalid values of reserved bits!"
200 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
201 #error "USBCLKSEL: Value out of range!"
204 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
205 #error "USBCLKDIV: Value out of range!"
209 /*----------------------------------------------------------------------------
211 *----------------------------------------------------------------------------*/
213 /*----------------------------------------------------------------------------
215 *----------------------------------------------------------------------------*/
216 #define __XTAL (12000000UL) /* Oscillator frequency */
217 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
218 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
221 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
222 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
224 #if (CLOCK_SETUP) /* Clock Setup */
226 #define __WDT_OSC_CLK ( 0) /* undefined */
227 #elif (__FREQSEL == 1)
228 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
229 #elif (__FREQSEL == 2)
230 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
231 #elif (__FREQSEL == 3)
232 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
233 #elif (__FREQSEL == 4)
234 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
235 #elif (__FREQSEL == 5)
236 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
237 #elif (__FREQSEL == 6)
238 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
239 #elif (__FREQSEL == 7)
240 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
241 #elif (__FREQSEL == 8)
242 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
243 #elif (__FREQSEL == 9)
244 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
245 #elif (__FREQSEL == 10)
246 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
247 #elif (__FREQSEL == 11)
248 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
249 #elif (__FREQSEL == 12)
250 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
251 #elif (__FREQSEL == 13)
252 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
253 #elif (__FREQSEL == 14)
254 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
256 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
259 /* sys_pllclkin calculation */
260 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
261 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
262 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
263 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
265 #define __SYS_PLLCLKIN (0)
268 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
270 /* main clock calculation */
271 #if ((MAINCLKSEL_Val & 0x03) == 0)
272 #define __MAIN_CLOCK (__IRC_OSC_CLK)
273 #elif ((MAINCLKSEL_Val & 0x03) == 1)
274 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
275 #elif ((MAINCLKSEL_Val & 0x03) == 2)
277 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
279 #define __MAIN_CLOCK (__WDT_OSC_CLK)
281 #elif ((MAINCLKSEL_Val & 0x03) == 3)
282 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
284 #define __MAIN_CLOCK (0)
287 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
290 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
291 #endif // CLOCK_SETUP
294 /*----------------------------------------------------------------------------
295 Clock Variable definitions
296 *----------------------------------------------------------------------------*/
297 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
300 /*----------------------------------------------------------------------------
302 *----------------------------------------------------------------------------*/
303 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
305 uint32_t wdt_osc = 0;
307 /* Determine clock frequency according to clock register values */
308 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
309 case 0: wdt_osc = 0; break;
310 case 1: wdt_osc = 500000; break;
311 case 2: wdt_osc = 800000; break;
312 case 3: wdt_osc = 1100000; break;
313 case 4: wdt_osc = 1400000; break;
314 case 5: wdt_osc = 1600000; break;
315 case 6: wdt_osc = 1800000; break;
316 case 7: wdt_osc = 2000000; break;
317 case 8: wdt_osc = 2200000; break;
318 case 9: wdt_osc = 2400000; break;
319 case 10: wdt_osc = 2600000; break;
320 case 11: wdt_osc = 2700000; break;
321 case 12: wdt_osc = 2900000; break;
322 case 13: wdt_osc = 3100000; break;
323 case 14: wdt_osc = 3200000; break;
324 case 15: wdt_osc = 3400000; break;
326 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
328 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
329 case 0: /* Internal RC oscillator */
330 SystemCoreClock = __IRC_OSC_CLK;
332 case 1: /* Input Clock to System PLL */
333 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
334 case 0: /* Internal RC oscillator */
335 SystemCoreClock = __IRC_OSC_CLK;
337 case 1: /* System oscillator */
338 SystemCoreClock = __SYS_OSC_CLK;
340 case 2: /* Reserved */
341 case 3: /* Reserved */
346 case 2: /* WDT Oscillator */
347 SystemCoreClock = wdt_osc;
349 case 3: /* System PLL Clock Out */
350 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
351 case 0: /* Internal RC oscillator */
352 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
353 SystemCoreClock = __IRC_OSC_CLK;
355 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
358 case 1: /* System oscillator */
359 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
360 SystemCoreClock = __SYS_OSC_CLK;
362 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
365 case 2: /* Reserved */
366 case 3: /* Reserved */
373 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
378 * Initialize the system
383 * @brief Setup the microcontroller system.
384 * Initialize the System.
386 void SystemInit (void) {
389 #if (CLOCK_SETUP) /* Clock Setup */
391 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
392 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
393 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
394 for (i = 0; i < 200; i++) __NOP();
397 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
398 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
399 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
400 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
401 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
402 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
403 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
404 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
405 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
408 #if (((MAINCLKSEL_Val & 0x03) == 2) )
409 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
410 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
411 for (i = 0; i < 200; i++) __NOP();
414 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
415 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
416 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
417 LPC_SYSCON->MAINCLKUEN = 0x01;
418 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
420 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
422 #if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
423 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
425 #if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
426 LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
427 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
428 LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
429 LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
430 LPC_SYSCON->USBPLLCLKUEN = 0x01;
431 while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
432 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
433 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
434 LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
437 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
438 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
440 #else /* USB clock is not used */
441 LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
442 LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
447 /* System clock to the IOCON needs to be enabled or
448 most of the I/O related peripherals won't work. */
449 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);