1 /* mbed Microcontroller Library
2 * CMSIS-style functionality to support dynamic vectors
3 *******************************************************************************
4 * Copyright (c) 2011 ARM Limited. All rights reserved.
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8 * modification, are permitted provided that the following conditions are met:
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11 * this list of conditions and the following disclaimer.
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13 * this list of conditions and the following disclaimer in the documentation
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16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 *******************************************************************************
32 #include "cmsis_nvic.h"
34 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
35 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
36 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
37 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
39 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
40 * above the vector table before 0x200 will actually go to RAM. So we need to provide
41 * a solution where the compiler gets the right results based on the memory map
43 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
44 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
45 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
47 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
48 * - No flash accesses will go to ram, as there will be nothing there
49 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
50 * - RAM overhead: 0, FLASH overhead: 320 bytes
52 * Option 2 is the one to go for, as RAM is the most valuable resource
55 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
57 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
59 // Space for dynamic vectors, initialised to allocate in R/W
60 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
62 // Copy and switch to dynamic vectors if first time called
63 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
64 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
65 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
66 vectors[i] = old_vectors[i];
68 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
72 vectors[IRQn + 16] = vector;
75 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
76 // We can always read vectors at 0x0, as the addresses are remapped
77 uint32_t *vectors = (uint32_t*)0;
80 return vectors[IRQn + 16];