2 * LPC43xx/LPC18xx MCU header
4 * Copyright(C) NXP Semiconductors, 2012
7 * Software that is described herein is for illustrative purposes only
8 * which provides customers with programming information regarding the
9 * LPC products. This software is supplied "AS IS" without any warranties of
10 * any kind, and NXP Semiconductors and its licensor disclaim any and
11 * all warranties, express or implied, including all implied warranties of
12 * merchantability, fitness for a particular purpose and non-infringement of
13 * intellectual property rights. NXP Semiconductors assumes no responsibility
14 * or liability for the use of the software, conveys no license or rights under any
15 * patent, copyright, mask work right, or any other intellectual property rights in
16 * or to any products. NXP Semiconductors reserves the right to make changes
17 * in the software without notification. NXP Semiconductors also makes no
18 * representation or warranty that such application will be suitable for the
19 * specified use without further testing or modification.
21 * Permission to use, copy, modify, and distribute this software and its
22 * documentation is hereby granted, under NXP Semiconductors' and its
23 * licensor's relevant copyrights in the software, without fee, provided that it
24 * is used in conjunction with NXP Semiconductors microcontrollers. This
25 * copyright, permission, and disclaimer notice must appear in all copies of
28 * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
29 * 05/15/13 Micromint USA <support@micromint.com>
39 /* Treat __CORE_Mx as CORE_Mx */
40 #if defined(__CORTEX_M0) && !defined(CORE_M0)
43 #if defined(__CORTEX_M3) && !defined(CORE_M3)
46 /* Default to M4 core if no core explicitly declared */
47 #if !defined(CORE_M0) && !defined(CORE_M3)
51 /* Define LPC18XX or LPC43XX according to core type */
52 #if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
55 #if defined(CORE_M3) && !defined(__LPC18XX__)
59 /* Start of section using anonymous unions */
60 #if defined(__ARMCC_VERSION)
61 // Kill warning "#pragma push with no matching #pragma pop"
62 #pragma diag_suppress 2525
65 #elif defined(__CWCC__)
67 #pragma cpp_extensions on
68 #elif defined(__IAR_SYSTEMS_ICC__)
69 //#pragma push // FIXME not usable for IAR
70 #pragma language=extended
71 #else /* defined(__GNUC__) and others */
72 /* Assume anonymous unions are enabled by default */
76 /* ---------------------------------------------------------------------------
77 * LPC43xx (M4 Core) Cortex CMSIS definitions
80 #define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
81 #define __MPU_PRESENT 1 /* MPU present or not */
82 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
83 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
84 #define __FPU_PRESENT 1 /* FPU present or not */
85 #define CHIP_LPC43XX /* LPCOPEN compatibility */
87 /* ---------------------------------------------------------------------------
88 * LPC43xx peripheral interrupt numbers
92 /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
93 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
94 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
95 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
96 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
97 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
98 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
99 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
100 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
101 PendSV_IRQn = -2,/* 14 Pendable request for system service */
102 SysTick_IRQn = -1,/* 15 System Tick Timer */
104 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
105 DAC_IRQn = 0,/* 0 DAC */
106 M0CORE_IRQn = 1,/* 1 M0a */
107 DMA_IRQn = 2,/* 2 DMA */
108 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
110 ETHERNET_IRQn = 5,/* 5 ETHERNET */
111 SDIO_IRQn = 6,/* 6 SDIO */
112 LCD_IRQn = 7,/* 7 LCD */
113 USB0_IRQn = 8,/* 8 USB0 */
114 USB1_IRQn = 9,/* 9 USB1 */
115 SCT_IRQn = 10,/* 10 SCT */
116 RITIMER_IRQn = 11,/* 11 RITIMER */
117 TIMER0_IRQn = 12,/* 12 TIMER0 */
118 TIMER1_IRQn = 13,/* 13 TIMER1 */
119 TIMER2_IRQn = 14,/* 14 TIMER2 */
120 TIMER3_IRQn = 15,/* 15 TIMER3 */
121 MCPWM_IRQn = 16,/* 16 MCPWM */
122 ADC0_IRQn = 17,/* 17 ADC0 */
123 I2C0_IRQn = 18,/* 18 I2C0 */
124 I2C1_IRQn = 19,/* 19 I2C1 */
125 SPI_INT_IRQn = 20,/* 20 SPI_INT */
126 ADC1_IRQn = 21,/* 21 ADC1 */
127 SSP0_IRQn = 22,/* 22 SSP0 */
128 SSP1_IRQn = 23,/* 23 SSP1 */
129 USART0_IRQn = 24,/* 24 USART0 */
130 UART1_IRQn = 25,/* 25 UART1 */
131 USART2_IRQn = 26,/* 26 USART2 */
132 USART3_IRQn = 27,/* 27 USART3 */
133 I2S0_IRQn = 28,/* 28 I2S0 */
134 I2S1_IRQn = 29,/* 29 I2S1 */
136 SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
137 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
138 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
139 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
140 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
141 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
142 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
143 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
144 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
145 GINT0_IRQn = 40,/* 40 GINT0 */
146 GINT1_IRQn = 41,/* 41 GINT1 */
147 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
148 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
150 RESERVED7_IRQn = 45,/* 45 VADC */
151 ATIMER_IRQn = 46,/* 46 ATIMER */
152 RTC_IRQn = 47,/* 47 RTC */
154 WWDT_IRQn = 49,/* 49 WWDT */
156 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
157 QEI_IRQn = 52,/* 52 QEI */
160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
162 #elif defined(CORE_M3)
163 /* ---------------------------------------------------------------------------
164 * LPC18xx (M3 Core) Cortex CMSIS definitions
166 #define __MPU_PRESENT 1 /* MPU present or not */
167 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
168 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
169 #define __FPU_PRESENT 0 /* FPU present or not */
170 #define CHIP_LPC18XX /* LPCOPEN compatibility */
172 /* ---------------------------------------------------------------------------
173 * LPC18xx peripheral interrupt numbers
177 /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
178 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
179 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
180 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
181 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
182 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
183 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
184 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
185 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
186 PendSV_IRQn = -2,/* 14 Pendable request for system service */
187 SysTick_IRQn = -1,/* 15 System Tick Timer */
189 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
190 DAC_IRQn = 0,/* 0 DAC */
192 DMA_IRQn = 2,/* 2 DMA */
193 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
195 ETHERNET_IRQn = 5,/* 5 ETHERNET */
196 SDIO_IRQn = 6,/* 6 SDIO */
197 LCD_IRQn = 7,/* 7 LCD */
198 USB0_IRQn = 8,/* 8 USB0 */
199 USB1_IRQn = 9,/* 9 USB1 */
200 SCT_IRQn = 10,/* 10 SCT */
201 RITIMER_IRQn = 11,/* 11 RITIMER */
202 TIMER0_IRQn = 12,/* 12 TIMER0 */
203 TIMER1_IRQn = 13,/* 13 TIMER1 */
204 TIMER2_IRQn = 14,/* 14 TIMER2 */
205 TIMER3_IRQn = 15,/* 15 TIMER3 */
206 MCPWM_IRQn = 16,/* 16 MCPWM */
207 ADC0_IRQn = 17,/* 17 ADC0 */
208 I2C0_IRQn = 18,/* 18 I2C0 */
209 I2C1_IRQn = 19,/* 19 I2C1 */
211 ADC1_IRQn = 21,/* 21 ADC1 */
212 SSP0_IRQn = 22,/* 22 SSP0 */
213 SSP1_IRQn = 23,/* 23 SSP1 */
214 USART0_IRQn = 24,/* 24 USART0 */
215 UART1_IRQn = 25,/* 25 UART1 */
216 USART2_IRQn = 26,/* 26 USART2 */
217 USART3_IRQn = 27,/* 27 USART3 */
218 I2S0_IRQn = 28,/* 28 I2S0 */
219 I2S1_IRQn = 29,/* 29 I2S1 */
222 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
223 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
224 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
225 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
226 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
227 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
228 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
229 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
230 GINT0_IRQn = 40,/* 40 GINT0 */
231 GINT1_IRQn = 41,/* 41 GINT1 */
232 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
233 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
235 RESERVED7_IRQn = 45,/* 45 VADC */
236 ATIMER_IRQn = 46,/* 46 ATIMER */
237 RTC_IRQn = 47,/* 47 RTC */
239 WWDT_IRQn = 49,/* 49 WWDT */
241 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
242 QEI_IRQn = 52,/* 52 QEI */
245 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
247 #elif defined(CORE_M0)
248 /* ---------------------------------------------------------------------------
249 * LPC43xx (M0 Core) Cortex CMSIS definitions
252 #define __MPU_PRESENT 0 /* MPU present or not */
253 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
254 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
255 #define __FPU_PRESENT 0 /* FPU present or not */
256 #define CHIP_LPC43XX /* LPCOPEN compatibility */
258 /* ---------------------------------------------------------------------------
259 * LPC43xx (M0 Core) peripheral interrupt numbers
263 /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
264 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
265 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
266 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
267 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
268 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
269 PendSV_IRQn = -2,/* 14 Pendable request for system service */
270 SysTick_IRQn = -1,/* 15 System Tick Timer */
272 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
273 DAC_IRQn = 0,/* 0 DAC */
274 M0_M4CORE_IRQn = 1,/* 1 M0a */
275 DMA_IRQn = 2,/* 2 DMA r */
276 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
277 FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
278 ETHERNET_IRQn = 5,/* 5 ETHERNET */
279 SDIO_IRQn = 6,/* 6 SDIO */
280 LCD_IRQn = 7,/* 7 LCD */
281 USB0_IRQn = 8,/* 8 USB0 */
282 USB1_IRQn = 9,/* 9 USB1 */
283 SCT_IRQn = 10,/* 10 SCT */
284 RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
285 TIMER0_IRQn = 12,/* 12 TIMER0 */
286 GINT1_IRQn = 13,/* 13 GINT1 */
287 PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
288 TIMER3_IRQn = 15,/* 15 TIMER3 */
289 MCPWM_IRQn = 16,/* 16 MCPWM */
290 ADC0_IRQn = 17,/* 17 ADC0 */
291 I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
292 SGPIO_INT_IRQn = 19,/* 19 SGPIO */
293 SPI_INT_IRQn = 20,/* 20 SPI_INT */
294 ADC1_IRQn = 21,/* 21 ADC1 */
295 SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
296 EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
297 USART0_IRQn = 24,/* 24 USART0 */
298 UART1_IRQn = 25,/* 25 UART1 */
299 USART2_IRQn = 26,/* 26 USART2 */
300 USART3_IRQn = 27,/* 27 USART3 */
301 I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
302 C_CAN0_IRQn = 29,/* 29 C_CAN0 */
303 I2S1_IRQn = 29,/* 29 I2S1 */
308 #include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
310 #error Please #define CORE_M0, CORE_M3 or CORE_M4
313 #include "system_LPC43xx.h"
315 /* ---------------------------------------------------------------------------
316 * State Configurable Timer register block structure
318 #define LPC_SCT_BASE 0x40000000
319 #define CONFIG_SCT_nEV (16) /* Number of events */
320 #define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
321 #define CONFIG_SCT_nOU (16) /* Number of outputs */
324 __IO uint32_t CONFIG; /* Configuration Register */
326 __IO uint32_t CTRL_U; /* Control Register */
328 __IO uint16_t CTRL_L; /* Low control register */
329 __IO uint16_t CTRL_H; /* High control register */
334 __IO uint16_t LIMIT_L; /* limit register for counter L */
335 __IO uint16_t LIMIT_H; /* limit register for counter H */
336 __IO uint16_t HALT_L; /* halt register for counter L */
337 __IO uint16_t HALT_H; /* halt register for counter H */
338 __IO uint16_t STOP_L; /* stop register for counter L */
339 __IO uint16_t STOP_H; /* stop register for counter H */
340 __IO uint16_t START_L; /* start register for counter L */
341 __IO uint16_t START_H; /* start register for counter H */
342 uint32_t RESERVED1[10]; /* 0x03C reserved */
344 __IO uint32_t COUNT_U; /* counter register */
346 __IO uint16_t COUNT_L; /* counter register for counter L */
347 __IO uint16_t COUNT_H; /* counter register for counter H */
352 __IO uint16_t STATE_L; /* state register for counter L */
353 __IO uint16_t STATE_H; /* state register for counter H */
354 __I uint32_t INPUT; /* input register */
355 __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
356 __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
357 __IO uint32_t OUTPUT; /* output register */
358 __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
359 __IO uint32_t RES; /* conflict resolution register */
360 __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
361 __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
362 uint32_t RESERVED2[35];
363 __IO uint32_t EVEN; /* event enable register */
364 __IO uint32_t EVFLAG; /* event flag register */
365 __IO uint32_t CONEN; /* conflict enable register */
366 __IO uint32_t CONFLAG; /* conflict flag register */
368 __IO union { /* ... Match / Capture value */
369 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
371 uint16_t L; /* SCTMATCH[i].L Access to L value */
372 uint16_t H; /* SCTMATCH[i].H Access to H value */
375 } MATCH[CONFIG_SCT_nRG];
378 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
380 uint16_t L; /* SCTCAP[i].L Access to L value */
381 uint16_t H; /* SCTCAP[i].H Access to H value */
384 } CAP[CONFIG_SCT_nRG];
388 uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
390 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
391 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
394 uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
396 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
397 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
400 uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
402 __IO union { /* 0x200-... Match Reload / Capture Control value */
403 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
405 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
406 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
409 } MATCHREL[CONFIG_SCT_nRG];
412 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
414 uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
415 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
418 } CAPCTRL[CONFIG_SCT_nRG];
422 uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
424 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
425 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
428 uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
430 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
431 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
434 uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
435 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
436 uint32_t STATE; /* Event State Register */
437 uint32_t CTRL; /* Event Control Register */
438 } EVENT[CONFIG_SCT_nEV];
440 uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
441 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
442 uint32_t SET; /* Output n Set Register */
443 uint32_t CLR; /* Output n Clear Register */
444 } OUT[CONFIG_SCT_nOU];
446 uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
447 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
450 /* Macro defines for SCT configuration register */
451 #define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
452 #define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
454 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
455 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
456 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
457 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
459 #define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
460 #define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
462 /* Macro defines for SCT control register */
463 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
464 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
466 #define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
467 #define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
468 #define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
469 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
470 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
472 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
473 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
474 #define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
475 #define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
476 #define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
477 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
478 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
480 /* Macro defines for SCT Conflict resolution register */
481 #define SCT_RES_NOCHANGE (0)
482 #define SCT_RES_SET_OUTPUT (1)
483 #define SCT_RES_CLEAR_OUTPUT (2)
484 #define SCT_RES_TOGGLE_OUTPUT (3)
486 /* ---------------------------------------------------------------------------
487 * GPDMA Channel register block structure
489 #define LPC_GPDMA_BASE 0x40002000
492 __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
493 __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
494 __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
495 __IO uint32_t CONTROL; /* DMA Channel Control Register */
496 __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
497 __I uint32_t RESERVED1[3];
500 #define GPDMA_CHANNELS 8
502 /* ---------------------------------------------------------------------------
503 * GPDMA register block
505 typedef struct { /* GPDMA Structure */
506 __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
507 __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
508 __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
509 __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
510 __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
511 __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
512 __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
513 __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
514 __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
515 __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
516 __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
517 __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
518 __IO uint32_t CONFIG; /* DMA Configuration Register */
519 __IO uint32_t SYNC; /* DMA Synchronization Register */
520 __I uint32_t RESERVED0[50];
521 LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
524 /* ---------------------------------------------------------------------------
525 * SPIFI register block structure
527 #define LPC_SPIFI_BASE 0x40003000
529 typedef struct { /* SPIFI Structure */
530 __IO uint32_t CTRL; /* Control register */
531 __IO uint32_t CMD; /* Command register */
532 __IO uint32_t ADDR; /* Address register */
533 __IO uint32_t IDATA; /* Intermediate data register */
534 __IO uint32_t CLIMIT; /* Cache limit register */
537 __IO uint16_t DATA_HWORD;
538 __IO uint8_t DATA_BYTE;
539 }; /* Data register */
540 __IO uint32_t MCMD; /* Memory command register */
541 __IO uint32_t STAT; /* Status register */
544 /* ---------------------------------------------------------------------------
545 * SD/MMC & SDIO register block structure
547 #define LPC_SDMMC_BASE 0x40004000
549 typedef struct { /* SDMMC Structure */
550 __IO uint32_t CTRL; /* Control Register */
551 __IO uint32_t PWREN; /* Power Enable Register */
552 __IO uint32_t CLKDIV; /* Clock Divider Register */
553 __IO uint32_t CLKSRC; /* SD Clock Source Register */
554 __IO uint32_t CLKENA; /* Clock Enable Register */
555 __IO uint32_t TMOUT; /* Timeout Register */
556 __IO uint32_t CTYPE; /* Card Type Register */
557 __IO uint32_t BLKSIZ; /* Block Size Register */
558 __IO uint32_t BYTCNT; /* Byte Count Register */
559 __IO uint32_t INTMASK; /* Interrupt Mask Register */
560 __IO uint32_t CMDARG; /* Command Argument Register */
561 __IO uint32_t CMD; /* Command Register */
562 __I uint32_t RESP0; /* Response Register 0 */
563 __I uint32_t RESP1; /* Response Register 1 */
564 __I uint32_t RESP2; /* Response Register 2 */
565 __I uint32_t RESP3; /* Response Register 3 */
566 __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
567 __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
568 __I uint32_t STATUS; /* Status Register */
569 __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
570 __I uint32_t CDETECT; /* Card Detect Register */
571 __I uint32_t WRTPRT; /* Write Protect Register */
572 __IO uint32_t GPIO; /* General Purpose Input/Output Register */
573 __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
574 __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
575 __IO uint32_t DEBNCE; /* Debounce Count Register */
576 __IO uint32_t USRID; /* User ID Register */
577 __I uint32_t VERID; /* Version ID Register */
578 __I uint32_t RESERVED0;
579 __IO uint32_t UHS_REG; /* UHS-1 Register */
580 __IO uint32_t RST_N; /* Hardware Reset */
581 __I uint32_t RESERVED1;
582 __IO uint32_t BMOD; /* Bus Mode Register */
583 __O uint32_t PLDMND; /* Poll Demand Register */
584 __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
585 __IO uint32_t IDSTS; /* Internal DMAC Status Register */
586 __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
587 __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
588 __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
591 /* ---------------------------------------------------------------------------
592 * External Memory Controller (EMC) register block structure
594 #define LPC_EMC_BASE 0x40005000
596 typedef struct { /* EMC Structure */
597 __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
598 __I uint32_t STATUS; /* Provides EMC status information. */
599 __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
600 __I uint32_t RESERVED0[5];
601 __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
602 __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
603 __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
604 __I uint32_t RESERVED1;
605 __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
606 __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
607 __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
608 __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
609 __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
610 __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
611 __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
612 __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
613 __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
614 __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
615 __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
616 __I uint32_t RESERVED2[9];
617 __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
618 __I uint32_t RESERVED3[31];
619 __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
620 __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
621 __I uint32_t RESERVED4[6];
622 __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
623 __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
624 __I uint32_t RESERVED5[6];
625 __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
626 __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
627 __I uint32_t RESERVED6[6];
628 __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
629 __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
630 __I uint32_t RESERVED7[38];
631 __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
632 __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
633 __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
634 __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
635 __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
636 __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
637 __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
638 __I uint32_t RESERVED8;
639 __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
640 __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
641 __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
642 __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
643 __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
644 __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
645 __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
646 __I uint32_t RESERVED9;
647 __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
648 __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
649 __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
650 __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
651 __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
652 __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
653 __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
654 __I uint32_t RESERVED10;
655 __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
656 __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
657 __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
658 __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
659 __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
660 __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
661 __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
664 /* ---------------------------------------------------------------------------
665 * USB High-Speed register block structure
667 #define LPC_USB0_BASE 0x40006000
668 #define LPC_USB1_BASE 0x40007000
670 typedef struct { /* USB Structure */
671 __I uint32_t RESERVED0[64];
672 __I uint32_t CAPLENGTH; /* Capability register length */
673 __I uint32_t HCSPARAMS; /* Host controller structural parameters */
674 __I uint32_t HCCPARAMS; /* Host controller capability parameters */
675 __I uint32_t RESERVED1[5];
676 __I uint32_t DCIVERSION; /* Device interface version number */
677 __I uint32_t RESERVED2[7];
679 __IO uint32_t USBCMD_H; /* USB command (host mode) */
680 __IO uint32_t USBCMD_D; /* USB command (device mode) */
684 __IO uint32_t USBSTS_H; /* USB status (host mode) */
685 __IO uint32_t USBSTS_D; /* USB status (device mode) */
689 __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
690 __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
694 __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
695 __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
698 __I uint32_t RESERVED3;
700 __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
701 __IO uint32_t DEVICEADDR; /* USB device address */
705 __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
706 __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
709 __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
710 __IO uint32_t BURSTSIZE; /* Programmable burst size */
711 __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
712 __I uint32_t RESERVED4[2];
713 __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
714 __IO uint32_t BINTERVAL; /* Length of virtual frame */
715 __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
716 __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
717 __I uint32_t RESERVED5;
719 __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
720 __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
723 __I uint32_t RESERVED6[7];
724 __IO uint32_t OTGSC; /* OTG status and control */
726 __IO uint32_t USBMODE_H; /* USB mode (host mode) */
727 __IO uint32_t USBMODE_D; /* USB mode (device mode) */
730 __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
731 __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
732 __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
733 __I uint32_t ENDPTSTAT; /* Endpoint status */
734 __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
735 __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
738 /* ---------------------------------------------------------------------------
739 * LCD Controller register block structure
741 #define LPC_LCD_BASE 0x40008000
743 typedef struct { /* LCD Structure */
744 __IO uint32_t TIMH; /* Horizontal Timing Control register */
745 __IO uint32_t TIMV; /* Vertical Timing Control register */
746 __IO uint32_t POL; /* Clock and Signal Polarity Control register */
747 __IO uint32_t LE; /* Line End Control register */
748 __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
749 __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
750 __IO uint32_t CTRL; /* LCD Control register */
751 __IO uint32_t INTMSK; /* Interrupt Mask register */
752 __I uint32_t INTRAW; /* Raw Interrupt Status register */
753 __I uint32_t INTSTAT; /* Masked Interrupt Status register */
754 __O uint32_t INTCLR; /* Interrupt Clear register */
755 __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
756 __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
757 __I uint32_t RESERVED0[115];
758 __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
759 __I uint32_t RESERVED1[256];
760 __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
761 __IO uint32_t CRSR_CTRL; /* Cursor Control register */
762 __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
763 __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
764 __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
765 __IO uint32_t CRSR_XY; /* Cursor XY Position register */
766 __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
767 __I uint32_t RESERVED2[2];
768 __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
769 __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
770 __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
771 __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
774 /* ---------------------------------------------------------------------------
775 * EEPROM register block structure
777 #define LPC_EEPROM_BASE 0x4000E000
779 typedef struct { /* EEPROM Structure */
780 __IO uint32_t CMD; /* EEPROM command register */
782 __IO uint32_t RWSTATE; /* EEPROM read wait state register */
783 __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
784 __IO uint32_t WSTATE; /* EEPROM wait state register */
785 __IO uint32_t CLKDIV; /* EEPROM clock divider register */
786 __IO uint32_t PWRDWN; /* EEPROM power-down register */
787 uint32_t RESERVED2[1007];
788 __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
789 __O uint32_t INTENSET; /* EEPROM interrupt enable set */
790 __I uint32_t INTSTAT; /* EEPROM interrupt status */
791 __I uint32_t INTEN; /* EEPROM interrupt enable */
792 __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
793 __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
796 /* ---------------------------------------------------------------------------
797 * 10/100 MII & RMII Ethernet with timestamping register block structure
799 #define LPC_ETHERNET_BASE 0x40010000
801 typedef struct { /* ETHERNET Structure */
802 __IO uint32_t MAC_CONFIG; /* MAC configuration register */
803 __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
804 __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
805 __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
806 __IO uint32_t MAC_MII_ADDR; /* MII address register */
807 __IO uint32_t MAC_MII_DATA; /* MII data register */
808 __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
809 __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
810 __I uint32_t RESERVED0;
811 __I uint32_t MAC_DEBUG; /* Debug register */
812 __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
813 __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
814 __I uint32_t RESERVED1[2];
815 __I uint32_t MAC_INTR; /* Interrupt status register */
816 __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
817 __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
818 __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
819 __I uint32_t RESERVED2[430];
820 __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
821 __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
822 __I uint32_t SECONDS; /* System time seconds register */
823 __I uint32_t NANOSECONDS; /* System time nanoseconds register */
824 __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
825 __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
826 __IO uint32_t ADDEND; /* Time stamp addend register */
827 __IO uint32_t TARGETSECONDS; /* Target time seconds register */
828 __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
829 __IO uint32_t HIGHWORD; /* System time higher word seconds register */
830 __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
831 __IO uint32_t PPSCTRL; /* PPS control register */
832 __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
833 __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
834 __I uint32_t RESERVED3[562];
835 __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
836 __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
837 __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
838 __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
839 __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
840 __IO uint32_t DMA_STAT; /* Status register */
841 __IO uint32_t DMA_OP_MODE; /* Operation mode register */
842 __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
843 __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
844 __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
845 __I uint32_t RESERVED4[8];
846 __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
847 __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
848 __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
849 __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
852 /* ---------------------------------------------------------------------------
853 * Alarm Timer register block structure
855 #define LPC_ATIMER_BASE 0x40040000
857 typedef struct { /* ATIMER Structure */
858 __IO uint32_t DOWNCOUNTER; /* Downcounter register */
859 __IO uint32_t PRESET; /* Preset value register */
860 __I uint32_t RESERVED0[1012];
861 __O uint32_t CLR_EN; /* Interrupt clear enable register */
862 __O uint32_t SET_EN; /* Interrupt set enable register */
863 __I uint32_t STATUS; /* Status register */
864 __I uint32_t ENABLE; /* Enable register */
865 __O uint32_t CLR_STAT; /* Clear register */
866 __O uint32_t SET_STAT; /* Set register */
869 /* ---------------------------------------------------------------------------
870 * Register File register block structure
872 #define LPC_REGFILE_BASE 0x40041000
875 __IO uint32_t REGFILE[64]; /* General purpose storage register */
878 /* ---------------------------------------------------------------------------
879 * Power Management Controller register block structure
881 #define LPC_PMC_BASE 0x40042000
883 typedef struct { /* PMC Structure */
884 __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
885 __I uint32_t RESERVED0[6];
886 __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
889 /* ---------------------------------------------------------------------------
890 * CREG Register Block
892 #define LPC_CREG_BASE 0x40043000
894 typedef struct { /* CREG Structure */
895 __I uint32_t RESERVED0;
896 __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
897 __I uint32_t RESERVED1[62];
898 __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
899 #if defined(CHIP_LPC18XX)
900 __I uint32_t RESERVED2[5];
902 __I uint32_t RESERVED2;
903 __I uint32_t CREG1; /* Configuration Register 1 */
904 __I uint32_t CREG2; /* Configuration Register 2 */
905 __I uint32_t CREG3; /* Configuration Register 3 */
906 __I uint32_t CREG4; /* Configuration Register 4 */
908 __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
909 __IO uint32_t DMAMUX; /* DMA muxing control */
910 __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
911 __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
912 __IO uint32_t ETBCFG; /* ETB RAM configuration */
913 __IO uint32_t CREG6; /* Chip configuration register 6. */
914 #if defined(CHIP_LPC18XX)
915 __I uint32_t RESERVED4[52];
917 __IO uint32_t M4TXEVENT; /* M4 IPC event register */
918 __I uint32_t RESERVED4[51];
920 __I uint32_t CHIPID; /* Part ID */
921 #if defined(CHIP_LPC18XX)
922 __I uint32_t RESERVED5[191];
924 __I uint32_t RESERVED5[127];
925 __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
926 __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
927 __I uint32_t RESERVED6[62];
929 __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
930 __I uint32_t RESERVED7[63];
931 __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
934 /* ---------------------------------------------------------------------------
935 * Event Router register structure
937 #define LPC_EVRT_BASE 0x40044000
939 typedef struct { /* EVENTROUTER Structure */
940 __IO uint32_t HILO; /* Level configuration register */
941 __IO uint32_t EDGE; /* Edge configuration */
942 __I uint32_t RESERVED0[1012];
943 __O uint32_t CLR_EN; /* Event clear enable register */
944 __O uint32_t SET_EN; /* Event set enable register */
945 __I uint32_t STATUS; /* Status register */
946 __I uint32_t ENABLE; /* Enable register */
947 __O uint32_t CLR_STAT; /* Clear register */
948 __O uint32_t SET_STAT; /* Set register */
951 /* ---------------------------------------------------------------------------
952 * Real Time Clock register block structure
954 #define LPC_RTC_BASE 0x40046000
955 #define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
957 typedef enum RTC_TIMEINDEX {
958 RTC_TIMETYPE_SECOND, /* Second */
959 RTC_TIMETYPE_MINUTE, /* Month */
960 RTC_TIMETYPE_HOUR, /* Hour */
961 RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
962 RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
963 RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
964 RTC_TIMETYPE_MONTH, /* Month */
965 RTC_TIMETYPE_YEAR, /* Year */
970 typedef enum LPC_RTC_EV_CHANNEL {
971 RTC_EV_CHANNEL_1 = 0,
975 } LPC_RTC_EV_CHANNEL_T;
976 #endif /*RTC_EV_SUPPORT*/
978 typedef struct { /* RTC Structure */
979 __IO uint32_t ILR; /* Interrupt Location Register */
980 __I uint32_t RESERVED0;
981 __IO uint32_t CCR; /* Clock Control Register */
982 __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
983 __IO uint32_t AMR; /* Alarm Mask Register */
984 __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
985 __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
986 __IO uint32_t CALIBRATION; /* Calibration Value Register */
987 __I uint32_t RESERVED1[7];
988 __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
990 __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
991 __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
992 __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
993 __I uint32_t RESERVED2;
994 __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
995 __I uint32_t RESERVED3;
996 __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
997 #endif /*RTC_EV_SUPPORT*/
1000 /* ---------------------------------------------------------------------------
1001 * LPC18XX/43XX CGU register block structure
1003 #define LPC_CGU_BASE 0x40050000
1004 #define LPC_CCU1_BASE 0x40051000
1005 #define LPC_CCU2_BASE 0x40052000
1007 * Input clocks for the CGU and can come from both external (crystal) and
1008 * internal (PLL) sources. Can be routed to the base clocks.
1010 typedef enum CGU_CLKIN {
1011 CLKIN_32K, /* External 32KHz input */
1012 CLKIN_IRC, /* Internal IRC (12MHz) input */
1013 CLKIN_ENET_RX, /* External ENET_RX pin input */
1014 CLKIN_ENET_TX, /* External ENET_TX pin input */
1015 CLKIN_CLKIN, /* External GPCLKIN pin input */
1017 CLKIN_CRYSTAL, /* External (main) crystal pin input */
1018 CLKIN_USBPLL, /* Internal USB PLL input */
1019 CLKIN_AUDIOPLL, /* Internal Audio PLL input */
1020 CLKIN_MAINPLL, /* Internal Main PLL input */
1023 CLKIN_IDIVA, /* Internal divider A input */
1024 CLKIN_IDIVB, /* Internal divider B input */
1025 CLKIN_IDIVC, /* Internal divider C input */
1026 CLKIN_IDIVD, /* Internal divider D input */
1027 CLKIN_IDIVE, /* Internal divider E input */
1028 CLKINPUT_PD /* External 32KHz input */
1031 #define CLKIN_PLL0USB CLKIN_USBPLL
1032 #define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
1033 #define CLKIN_PLL1 CLKIN_MAINPLL
1036 * CGU base clocks are clocks that are associated with a single input clock
1037 * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
1038 * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
1039 * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
1040 * CLK_PERIPH_SGPIO periphral clocks.
1042 typedef enum CGU_BASE_CLK {
1043 CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
1044 CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
1045 #if defined(CHIP_LPC43XX)
1046 CLK_BASE_PERIPH, /* Base clock for SGPIO */
1050 CLK_BASE_USB1, /* Base USB clock for USB1 */
1051 CLK_BASE_MX, /* Base clock for CPU core */
1052 CLK_BASE_SPIFI, /* Base clock for SPIFI */
1053 #if defined(CHIP_LPC43XX)
1054 CLK_BASE_SPI, /* Base clock for SPI */
1058 CLK_BASE_PHY_RX, /* Base clock for PHY RX */
1059 CLK_BASE_PHY_TX, /* Base clock for PHY TX */
1060 CLK_BASE_APB1, /* Base clock for APB1 group */
1061 CLK_BASE_APB3, /* Base clock for APB3 group */
1062 CLK_BASE_LCD, /* Base clock for LCD pixel clock */
1063 #if defined(CHIP_LPC43XX)
1064 CLK_BASE_VADC, /* Base clock for VADC */
1068 CLK_BASE_SDIO, /* Base clock for SDIO */
1069 CLK_BASE_SSP0, /* Base clock for SSP0 */
1070 CLK_BASE_SSP1, /* Base clock for SSP1 */
1071 CLK_BASE_UART0, /* Base clock for UART0 */
1072 CLK_BASE_UART1, /* Base clock for UART1 */
1073 CLK_BASE_UART2, /* Base clock for UART2 */
1074 CLK_BASE_UART3, /* Base clock for UART3 */
1075 CLK_BASE_OUT, /* Base clock for CLKOUT pin */
1080 CLK_BASE_APLL, /* Base clock for audio PLL */
1081 CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
1082 CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
1084 CLK_BASE_NONE = CLK_BASE_LAST
1088 * CGU dividers provide an extra clock state where a specific clock can be
1089 * divided before being routed to a peripheral group. A divider accepts an
1090 * input clock and then divides it. To use the divided clock for a base clock
1091 * group, use the divider as the input clock for the base clock (for example,
1092 * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
1094 typedef enum CGU_IDIV {
1095 CLK_IDIV_A, /* CGU clock divider A */
1096 CLK_IDIV_B, /* CGU clock divider B */
1097 CLK_IDIV_C, /* CGU clock divider A */
1098 CLK_IDIV_D, /* CGU clock divider D */
1099 CLK_IDIV_E, /* CGU clock divider E */
1104 * Peripheral clocks are individual clocks routed to peripherals. Although
1105 * multiple peripherals may share a same base clock, each peripheral's clock
1106 * can be enabled or disabled individually. Some peripheral clocks also have
1107 * additional dividers associated with them.
1109 typedef enum CCU_CLK {
1111 CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
1112 CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
1113 CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
1114 CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
1115 CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
1116 CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
1117 CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
1118 CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
1119 CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
1120 CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
1121 CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
1122 CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
1123 CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
1124 CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
1125 CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
1126 CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
1127 CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
1128 CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
1129 CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
1130 CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
1131 CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
1132 CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
1133 RESERVED_ALIGN = CLK_MX_MXCORE + 3,
1134 CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
1135 CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
1136 CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
1137 CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
1138 CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
1139 #if defined(CHIP_LPC43XX)
1140 CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
1141 CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
1146 CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
1147 CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
1148 CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
1149 CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
1150 CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
1151 CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
1152 CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
1153 CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
1154 CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
1155 CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
1156 CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
1157 CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
1158 CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
1159 CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
1160 CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
1161 CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
1162 #if defined(CHIP_LPC43XX)
1163 CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
1165 CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
1166 CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
1168 CLK_RESERVED3 = 192,
1173 CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
1174 CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
1175 #if defined(CHIP_LPC43XX)
1176 CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
1177 CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
1179 CLK_RESERVED7 = 320,
1186 CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
1187 RESERVED_ALIGNB = CLK_CCU2_START + 31,
1188 CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
1189 RESERVED_ALIGNC = CLK_CCU2_START + 63,
1190 CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
1191 RESERVED_ALIGND = CLK_CCU2_START + 95,
1192 CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
1193 RESERVED_ALIGNE = CLK_CCU2_START + 127,
1194 CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
1195 RESERVED_ALIGNF = CLK_CCU2_START + 159,
1196 CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
1197 RESERVED_ALIGNG = CLK_CCU2_START + 191,
1198 CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
1199 RESERVED_ALIGNH = CLK_CCU2_START + 223,
1200 CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
1205 * Audio or USB PLL selection
1207 typedef enum CGU_USB_AUDIO_PLL {
1210 } CGU_USB_AUDIO_PLL_T;
1213 * PLL register block
1216 __I uint32_t PLL_STAT; /* PLL status register */
1217 __IO uint32_t PLL_CTRL; /* PLL control register */
1218 __IO uint32_t PLL_MDIV; /* PLL M-divider register */
1219 __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
1222 typedef struct { /* (@ 0x40050000) CGU Structure */
1223 __I uint32_t RESERVED0[5];
1224 __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
1225 __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
1226 CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
1227 __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
1228 __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
1229 __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
1230 __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
1231 __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
1234 /* ---------------------------------------------------------------------------
1235 * CCU clock config/status register pair
1238 __IO uint32_t CFG; /* CCU clock configuration register */
1239 __I uint32_t STAT; /* CCU clock status register */
1242 /* ---------------------------------------------------------------------------
1243 * CCU1 register block structure
1245 typedef struct { /* (@ 0x40051000) CCU1 Structure */
1246 __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
1247 __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
1248 __I uint32_t RESERVED0[62];
1249 CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
1252 /* ---------------------------------------------------------------------------
1253 * CCU2 register block structure
1255 typedef struct { /* (@ 0x40052000) CCU2 Structure */
1256 __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
1257 __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
1258 __I uint32_t RESERVED0[62];
1259 CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
1262 /* ---------------------------------------------------------------------------
1263 * RGU register structure
1265 #define LPC_RGU_BASE 0x40053000
1267 typedef enum RGU_RST {
1283 RGU_FLASHA_RST = 25,
1284 RGU_EEPROM_RST = 27,
1287 RGU_TIMER0_RST = 32,
1318 typedef struct { /* RGU Structure */
1319 __I uint32_t RESERVED0[64];
1320 __O uint32_t RESET_CTRL0; /* Reset control register 0 */
1321 __O uint32_t RESET_CTRL1; /* Reset control register 1 */
1322 __I uint32_t RESERVED1[2];
1323 __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
1324 __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
1325 __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
1326 __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
1327 __I uint32_t RESERVED2[12];
1328 __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
1329 __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
1330 __I uint32_t RESERVED3[170];
1331 __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
1334 /* ---------------------------------------------------------------------------
1335 * Windowed Watchdog register block structure
1337 #define LPC_WWDT_BASE 0x40080000
1339 typedef struct { /* WWDT Structure */
1340 __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
1341 __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
1342 __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
1343 __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
1344 #ifdef WATCHDOG_CLKSEL_SUPPORT
1345 __IO uint32_t CLKSEL; /* Watchdog clock select register. */
1347 __I uint32_t RESERVED0;
1349 #ifdef WATCHDOG_WINDOW_SUPPORT
1350 __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
1351 __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
1355 /* ---------------------------------------------------------------------------
1356 * USART register block structure
1358 #define LPC_USART0_BASE 0x40081000
1359 #define LPC_UART1_BASE 0x40082000
1360 #define LPC_USART2_BASE 0x400C1000
1361 #define LPC_USART3_BASE 0x400C2000
1363 typedef struct { /* USARTn Structure */
1366 __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
1367 __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
1368 __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
1372 __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
1373 __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
1377 __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
1378 __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
1381 __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
1382 __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
1383 __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
1384 __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
1385 __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
1386 __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
1387 __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
1388 __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
1389 __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
1390 __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
1391 uint32_t RESERVED0[3];
1392 __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
1393 __I uint32_t RESERVED1[1];
1394 __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
1395 __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
1396 __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
1397 __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
1399 __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
1400 __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
1403 __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
1406 /* ---------------------------------------------------------------------------
1407 * SSP register block structure
1409 #define LPC_SSP0_BASE 0x40083000
1410 #define LPC_SSP1_BASE 0x400C5000
1412 typedef struct { /* SSPn Structure */
1413 __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
1414 __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
1415 __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
1416 __I uint32_t SR; /* Status Register */
1417 __IO uint32_t CPSR; /* Clock Prescale Register */
1418 __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
1419 __I uint32_t RIS; /* Raw Interrupt Status Register */
1420 __I uint32_t MIS; /* Masked Interrupt Status Register */
1421 __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
1422 __IO uint32_t DMACR; /* SSPn DMA control register */
1425 /* ---------------------------------------------------------------------------
1426 * 32-bit Standard timer register block structure
1428 #define LPC_TIMER0_BASE 0x40084000
1429 #define LPC_TIMER1_BASE 0x40085000
1430 #define LPC_TIMER2_BASE 0x400C3000
1431 #define LPC_TIMER3_BASE 0x400C4000
1433 typedef struct { /* TIMERn Structure */
1434 __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
1435 __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
1436 __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
1437 __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
1438 __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
1439 __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
1440 __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
1441 __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
1442 __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
1443 __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
1444 __I uint32_t RESERVED0[12];
1445 __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
1448 /* ---------------------------------------------------------------------------
1449 * System Control Unit register block
1451 #define LPC_SCU_BASE 0x40086000
1454 __IO uint32_t SFSP[16][32];
1455 __I uint32_t RESERVED0[256];
1456 __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
1457 __I uint32_t RESERVED16[28];
1458 __IO uint32_t SFSUSB; /* Pin configuration register for USB */
1459 __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
1460 __IO uint32_t ENAIO[3]; /* Analog function select registers */
1461 __I uint32_t RESERVED17[27];
1462 __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
1463 __I uint32_t RESERVED18[63];
1464 __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
1465 __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
1469 * SCU function and mode selection definitions
1470 * See the User Manual for specific modes and functions supoprted by the
1471 * various LPC18xx/43xx devices. Functionality can vary per device.
1473 #define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
1474 #define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
1475 #define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
1476 #define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
1477 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
1478 #define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
1479 #define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
1480 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
1481 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
1482 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
1483 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
1485 #define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
1486 #define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
1487 #define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
1488 #define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
1489 #define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
1490 #define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
1491 #define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
1492 #define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
1494 /* Common SCU configurations */
1495 #define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
1496 #define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
1497 #define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
1498 #define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
1500 /* Calculate SCU offset and register address from group and pin number */
1501 #define SCU_OFF(group, num) ((group << 7) + (num << 2))
1502 #define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
1505 * SCU function and mode selection definitions (old)
1506 * For backwards compatibility.
1508 #define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
1509 #define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
1510 #define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
1511 #define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
1512 #define MD_EHS (0x1 << 5) /* Enable fast slew rate */
1513 #define MD_EZI (0x1 << 6) /* Input buffer enable */
1514 #define MD_ZI (0x1 << 7) /* Disable input glitch filter */
1515 #define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
1516 #define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
1517 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
1518 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
1519 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
1521 #define FUNC0 0x0 /* Pin function 0 */
1522 #define FUNC1 0x1 /* Pin function 1 */
1523 #define FUNC2 0x2 /* Pin function 2 */
1524 #define FUNC3 0x3 /* Pin function 3 */
1525 #define FUNC4 0x4 /* Pin function 4 */
1526 #define FUNC5 0x5 /* Pin function 5 */
1527 #define FUNC6 0x6 /* Pin function 6 */
1528 #define FUNC7 0x7 /* Pin function 7 */
1530 #define PORT_OFFSET 0x80 /* Port offset definition */
1531 #define PIN_OFFSET 0x04 /* Pin offset definition */
1533 /* Returns the SFSP register address in the SCU for a pin and port,
1534 recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
1535 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
1536 (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
1538 /* Returns the address in the SCU for a SFSCLK clock register,
1539 recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
1540 #define LPC_SCU_CLK(LPC_SCU_BASE, c) \
1541 (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
1543 /* ---------------------------------------------------------------------------
1544 * GPIO pin interrupt register block structure
1546 #define LPC_GPIO_PIN_INT_BASE 0x40087000
1548 typedef struct { /* GPIO_PIN_INT Structure */
1549 __IO uint32_t ISEL; /* Pin Interrupt Mode register */
1550 __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
1551 __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
1552 __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
1553 __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
1554 __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
1555 __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
1556 __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
1557 __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
1558 __IO uint32_t IST; /* Pin Interrupt Status register */
1561 typedef enum LPC_GPIOPININT_MODE {
1562 GPIOPININT_RISING_EDGE = 0x01,
1563 GPIOPININT_FALLING_EDGE = 0x02,
1564 GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
1565 GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
1566 } LPC_GPIOPININT_MODE_T;
1568 /* ---------------------------------------------------------------------------
1569 * GPIO grouped interrupt register block structure
1571 #define LPC_GPIO_GROUP_INT0_BASE 0x40088000
1572 #define LPC_GPIO_GROUP_INT1_BASE 0x40089000
1574 typedef struct { /* GPIO_GROUP_INTn Structure */
1575 __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
1576 __I uint32_t RESERVED0[7];
1577 __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
1578 __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
1579 } LPC_GPIOGROUPINT_T;
1581 /* ---------------------------------------------------------------------------
1582 * Motor Control PWM register block structure
1584 #define LPC_MCPWM_BASE 0x400A0000
1586 typedef struct { /* MCPWM Structure */
1587 __I uint32_t CON; /* PWM Control read address */
1588 __O uint32_t CON_SET; /* PWM Control set address */
1589 __O uint32_t CON_CLR; /* PWM Control clear address */
1590 __I uint32_t CAPCON; /* Capture Control read address */
1591 __O uint32_t CAPCON_SET; /* Capture Control set address */
1592 __O uint32_t CAPCON_CLR; /* Event Control clear address */
1593 __IO uint32_t TC[3]; /* Timer Counter register */
1594 __IO uint32_t LIM[3]; /* Limit register */
1595 __IO uint32_t MAT[3]; /* Match register */
1596 __IO uint32_t DT; /* Dead time register */
1597 __IO uint32_t CCP; /* Communication Pattern register */
1598 __I uint32_t CAP[3]; /* Capture register */
1599 __I uint32_t INTEN; /* Interrupt Enable read address */
1600 __O uint32_t INTEN_SET; /* Interrupt Enable set address */
1601 __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
1602 __I uint32_t CNTCON; /* Count Control read address */
1603 __O uint32_t CNTCON_SET; /* Count Control set address */
1604 __O uint32_t CNTCON_CLR; /* Count Control clear address */
1605 __I uint32_t INTF; /* Interrupt flags read address */
1606 __O uint32_t INTF_SET; /* Interrupt flags set address */
1607 __O uint32_t INTF_CLR; /* Interrupt flags clear address */
1608 __O uint32_t CAP_CLR; /* Capture clear address */
1611 /* ---------------------------------------------------------------------------
1612 * I2C register block structure
1614 #define LPC_I2C0_BASE 0x400A1000
1615 #define LPC_I2C1_BASE 0x400E0000
1617 typedef struct { /* I2C0 Structure */
1618 __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
1619 __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
1620 __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
1621 __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
1622 __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
1623 __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
1624 __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
1625 __IO uint32_t MMCTRL; /* Monitor mode control register. */
1626 __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
1627 __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
1628 __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
1629 __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
1630 __IO uint32_t MASK[4]; /* I2C Slave address mask register */
1633 /* ---------------------------------------------------------------------------
1634 * I2S register block structure
1636 #define LPC_I2S0_BASE 0x400A2000
1637 #define LPC_I2S1_BASE 0x400A3000
1639 typedef struct { /* I2S Structure */
1640 __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
1641 __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
1642 __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
1643 __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
1644 __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
1645 __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
1646 __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
1647 __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
1648 __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
1649 __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
1650 __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
1651 __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
1652 __IO uint32_t TXMODE; /* I2S Transmit mode control */
1653 __IO uint32_t RXMODE; /* I2S Receive mode control */
1656 /* ---------------------------------------------------------------------------
1657 * CCAN Controller Area Network register block structure
1659 #define LPC_C_CAN1_BASE 0x400A4000
1660 #define LPC_C_CAN0_BASE 0x400E2000
1662 typedef struct { /* C_CAN message interface Structure */
1663 __IO uint32_t IF_CMDREQ; /* Message interface command request */
1665 __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
1666 __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
1669 __IO uint32_t IF_MSK1; /* Message interface mask 1 */
1670 __IO uint32_t IF_MSK2; /* Message interface mask 2 */
1671 __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
1672 __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
1673 __IO uint32_t IF_MCTRL; /* Message interface message control */
1674 __IO uint32_t IF_DA1; /* Message interface data A1 */
1675 __IO uint32_t IF_DA2; /* Message interface data A2 */
1676 __IO uint32_t IF_DB1; /* Message interface data B1 */
1677 __IO uint32_t IF_DB2; /* Message interface data B2 */
1678 __I uint32_t RESERVED[13];
1681 typedef struct { /* C_CAN Structure */
1682 __IO uint32_t CNTL; /* CAN control */
1683 __IO uint32_t STAT; /* Status register */
1684 __I uint32_t EC; /* Error counter */
1685 __IO uint32_t BT; /* Bit timing register */
1686 __I uint32_t INT; /* Interrupt register */
1687 __IO uint32_t TEST; /* Test register */
1688 __IO uint32_t BRPE; /* Baud rate prescaler extension register */
1689 __I uint32_t RESERVED0;
1690 LPC_CCAN_IF_T IF[2];
1691 __I uint32_t RESERVED2[8];
1692 __I uint32_t TXREQ1; /* Transmission request 1 */
1693 __I uint32_t TXREQ2; /* Transmission request 2 */
1694 __I uint32_t RESERVED3[6];
1695 __I uint32_t ND1; /* New data 1 */
1696 __I uint32_t ND2; /* New data 2 */
1697 __I uint32_t RESERVED4[6];
1698 __I uint32_t IR1; /* Interrupt pending 1 */
1699 __I uint32_t IR2; /* Interrupt pending 2 */
1700 __I uint32_t RESERVED5[6];
1701 __I uint32_t MSGV1; /* Message valid 1 */
1702 __I uint32_t MSGV2; /* Message valid 2 */
1703 __I uint32_t RESERVED6[6];
1704 __IO uint32_t CLKDIV; /* CAN clock divider register */
1707 /* ---------------------------------------------------------------------------
1708 * Repetitive Interrupt Timer register block structure
1710 #define LPC_RITIMER_BASE 0x400C0000
1712 typedef struct { /* RITIMER Structure */
1713 __IO uint32_t COMPVAL; /* Compare register */
1714 __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
1715 __IO uint32_t CTRL; /* Control register. */
1716 __IO uint32_t COUNTER; /* 32-bit counter */
1719 /* ---------------------------------------------------------------------------
1720 * Quadrature Encoder Interface register block structure
1722 #define LPC_QEI_BASE 0x400C6000
1724 typedef struct { /* QEI Structure */
1725 __O uint32_t CON; /* Control register */
1726 __I uint32_t STAT; /* Encoder status register */
1727 __IO uint32_t CONF; /* Configuration register */
1728 __I uint32_t POS; /* Position register */
1729 __IO uint32_t MAXPOS; /* Maximum position register */
1730 __IO uint32_t CMPOS0; /* position compare register 0 */
1731 __IO uint32_t CMPOS1; /* position compare register 1 */
1732 __IO uint32_t CMPOS2; /* position compare register 2 */
1733 __I uint32_t INXCNT; /* Index count register */
1734 __IO uint32_t INXCMP0; /* Index compare register 0 */
1735 __IO uint32_t LOAD; /* Velocity timer reload register */
1736 __I uint32_t TIME; /* Velocity timer register */
1737 __I uint32_t VEL; /* Velocity counter register */
1738 __I uint32_t CAP; /* Velocity capture register */
1739 __IO uint32_t VELCOMP; /* Velocity compare register */
1740 __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
1741 __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
1742 __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
1743 __IO uint32_t WINDOW; /* Index acceptance window register */
1744 __IO uint32_t INXCMP1; /* Index compare register 1 */
1745 __IO uint32_t INXCMP2; /* Index compare register 2 */
1746 __I uint32_t RESERVED0[993];
1747 __O uint32_t IEC; /* Interrupt enable clear register */
1748 __O uint32_t IES; /* Interrupt enable set register */
1749 __I uint32_t INTSTAT; /* Interrupt status register */
1750 __I uint32_t IE; /* Interrupt enable register */
1751 __O uint32_t CLR; /* Interrupt status clear register */
1752 __O uint32_t SET; /* Interrupt status set register */
1755 /* ---------------------------------------------------------------------------
1756 * Global Input Multiplexer Array (GIMA) register block structure
1758 #define LPC_GIMA_BASE 0x400C7000
1760 typedef struct { /* GIMA Structure */
1761 __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
1762 __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
1763 __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
1764 __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
1765 __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
1766 __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
1767 __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
1768 __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
1771 /* ---------------------------------------------------------------------------
1772 * DAC register block structure
1774 #define LPC_DAC_BASE 0x400E1000
1776 typedef struct { /* DAC Structure */
1777 __IO uint32_t CR; /* DAC register. Holds the conversion data. */
1778 __IO uint32_t CTRL; /* DAC control register. */
1779 __IO uint32_t CNTVAL; /* DAC counter value register. */
1782 /* After the selected settling time after this field is written with a
1783 * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
1784 * is VALUE/1024 ? VREF
1786 #define DAC_RANGE 0x3FF
1787 #define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
1788 #define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
1789 #define DAC_VALUE(n) DAC_SET(n)
1790 /* If this bit = 0: The settling time of the DAC is 1 microsecond max,
1791 * and the maximum current is 700 microAmpere
1792 * If this bit = 1: The settling time of the DAC is 2.5 microsecond
1793 * and the maximum current is 350 microAmpere
1795 #define DAC_BIAS_EN ((uint32_t) (1 << 16))
1796 /* Value to reload interrupt DMA counter */
1797 #define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
1799 #define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
1800 #define DAC_CNT_ENA ((uint32_t) (1 << 2))
1801 #define DAC_DMA_ENA ((uint32_t) (1 << 3))
1802 #define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
1804 /* Current option in DAC configuration option */
1805 typedef enum DAC_CURRENT_OPT {
1806 DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
1807 allows for a maximum update rate of 1 MHz */
1808 DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
1809 allows for a maximum update rate of 400 kHz */
1810 } DAC_CURRENT_OPT_T;
1812 /* ---------------------------------------------------------------------------
1813 * ADC register block structure
1815 #define LPC_ADC0_BASE 0x400E3000
1816 #define LPC_ADC1_BASE 0x400E4000
1817 #define ADC_ACC_10BITS
1819 /* ---------------------------------------------------------------------------
1820 * 10 or 12-bit ADC register block structure
1822 typedef struct { /* ADCn Structure */
1823 __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
1824 __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
1825 __I uint32_t RESERVED0;
1826 __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
1827 __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
1828 __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
1831 /* ADC register support bitfields and mask */
1832 #define ADC_RANGE 0x3FF
1833 #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
1834 #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
1835 #define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
1836 #define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
1837 #define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
1838 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
1839 #define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
1840 #define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
1841 #define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
1842 #define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
1843 #define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
1844 #define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
1845 #define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
1846 #define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
1847 #define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
1848 #define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
1849 #define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
1850 #define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
1852 /* ADC status register used for IP drivers */
1853 typedef enum ADC_STATUS {
1854 ADC_DR_DONE_STAT, /* ADC data register staus */
1855 ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
1856 ADC_DR_ADINT_STAT /* ADC interrupt status */
1859 /** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
1860 typedef enum ADC_START_MODE {
1862 ADC_START_NOW, /* Start conversion now */
1863 ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
1864 ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
1865 ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
1866 ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
1867 ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
1870 /* ---------------------------------------------------------------------------
1871 * GPIO port register block structure
1873 #define LPC_GPIO_PORT_BASE 0x400F4000
1874 #define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
1875 #define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
1876 #define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
1877 #define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
1878 #define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
1879 #define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
1880 #define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
1881 #define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
1883 typedef struct { /* GPIO_PORT Structure */
1884 __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
1885 __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
1886 __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
1887 __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
1888 __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
1889 __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
1890 __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
1891 __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
1892 __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
1895 /* Calculate GPIO offset and port register address from group and pin number */
1896 #define GPIO_OFF(port, pin) ((port << 5) + pin)
1897 #define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
1899 /* ---------------------------------------------------------------------------
1900 * SPI register block structure
1902 #define LPC_SPI_BASE 0x40100000
1904 typedef struct { /* SPI Structure */
1905 __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
1906 __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
1907 __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
1908 __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
1909 __I uint32_t RESERVED0[3];
1910 __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
1913 /* SPI CFG Register BitMask */
1914 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
1915 /* Enable of controlling the number of bits per transfer */
1916 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
1917 /* Mask of field of bit controlling */
1918 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
1919 /* Set the number of bits per a transfer */
1920 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
1921 /* SPI Clock Phase Select*/
1922 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
1923 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
1924 /* SPI Clock Polarity Select*/
1925 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
1926 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
1927 /* SPI Slave Mode Select */
1928 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
1929 /* SPI Master Mode Select */
1930 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
1931 /* SPI MSB First mode enable */
1932 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
1933 /* SPI LSB First mode enable */
1934 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
1935 /* SPI interrupt enable */
1936 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
1937 /* SPI STAT Register BitMask */
1938 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
1939 /* Slave abort Flag */
1940 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
1941 /* Mode fault Flag */
1942 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
1943 /* Read overrun flag*/
1944 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
1945 /* Write collision flag. */
1946 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
1947 /* SPI transfer complete flag. */
1948 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
1949 /* SPI error flag */
1950 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
1951 /* Enable SPI Test Mode */
1952 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
1953 /* SPI interrupt flag */
1954 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
1956 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
1959 typedef enum LPC_SPI_MODE {
1960 SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
1961 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
1965 typedef enum LPC_SPI_CLOCK_MODE {
1966 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
1967 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
1968 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
1969 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
1970 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
1971 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
1972 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
1973 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
1974 } LPC_SPI_CLOCK_MODE_T;
1976 /* SPI Data Order Mode*/
1977 typedef enum LPC_SPI_DATA_ORDER {
1978 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
1979 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
1980 } LPC_SPI_DATA_ORDER_T;
1982 /* ---------------------------------------------------------------------------
1983 * Serial GPIO register block structure
1985 #define LPC_SGPIO_BASE 0x40101000
1987 typedef struct { /* SGPIO Structure */
1988 __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
1989 __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
1990 __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
1991 __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
1992 __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
1993 __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
1994 __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
1995 __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
1996 __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
1997 __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
1998 __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
1999 __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
2000 __I uint32_t GPIO_INREG; /* GPIO input status register */
2001 __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
2002 __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
2003 __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
2004 __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
2005 __I uint32_t RESERVED0[823];
2006 __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
2007 __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
2008 __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
2009 __I uint32_t STATUS_0; /* Shift clock interrupt status */
2010 __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
2011 __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
2012 __I uint32_t RESERVED1[2];
2013 __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
2014 __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
2015 __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
2016 __I uint32_t STATUS_1; /* Capture clock interrupt status */
2017 __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
2018 __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
2019 __I uint32_t RESERVED2[2];
2020 __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
2021 __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
2022 __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
2023 __I uint32_t STATUS_2; /* Pattern match interrupt status */
2024 __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
2025 __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
2026 __I uint32_t RESERVED3[2];
2027 __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
2028 __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
2029 __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
2030 __I uint32_t STATUS_3; /* Input bit match interrupt status */
2031 __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
2032 __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
2035 /* End of section using anonymous unions */
2036 #if defined(__ARMCC_VERSION)
2038 #elif defined(__CWCC__)
2040 #elif defined(__IAR_SYSTEMS_ICC__)
2041 //#pragma pop // FIXME not usable for IAR
2042 #else /* defined(__GNUC__) and others */
2043 /* Leave anonymous unions enabled */
2046 /* ---------------------------------------------------------------------------
2047 * LPC43xx Peripheral register set declarations
2049 #define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
2050 #define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
2051 #define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
2052 #define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
2053 #define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
2054 #define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
2055 #define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
2056 #define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
2057 #define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
2058 #define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
2059 #define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
2060 #define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
2061 #define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
2062 #define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
2063 #define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
2064 #define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
2065 #define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
2066 #define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
2067 #define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
2068 #define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
2069 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
2070 #define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
2071 #define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
2072 #define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
2073 #define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
2074 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
2075 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
2076 #define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
2077 #define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
2078 #define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
2079 #define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
2080 #define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
2081 #define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
2082 #define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
2083 #define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
2084 #define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
2085 #define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
2086 #define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
2087 #define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
2088 #define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
2089 #define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
2090 #define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
2091 #define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
2092 #define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
2093 #define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
2094 #define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
2095 #define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
2096 #define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
2097 #define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
2098 #define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
2099 #define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
2100 #define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
2101 #define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
2102 #define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
2103 #define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
2104 #define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
2105 #define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
2106 #define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
2107 #define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
2113 #endif /* __LPC43XX_H */