1 /****************************************************************************
2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
3 * Project: NXP LPC8xx software example
6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
7 * NXP LPC800 Device Series
9 ****************************************************************************
10 * Software that is described herein is for illustrative purposes only
11 * which provides customers with programming information regarding the
12 * products. This software is supplied "AS IS" without any warranties.
13 * NXP Semiconductors assumes no responsibility or liability for the
14 * use of the software, conveys no license or title under any patent,
15 * copyright, or mask work right to the product. NXP Semiconductors
16 * reserves the right to make changes in the software without
17 * notification. NXP Semiconductors also make no representation or
18 * warranty that such application will be suitable for the specified
19 * use without further testing or modification.
21 * Permission to use, copy, modify, and distribute this software and its
22 * documentation is hereby granted, under NXP Semiconductors'
23 * relevant copyright in the software, without fee, provided that it
24 * is used in conjunction with NXP Semiconductors microcontrollers. This
25 * copyright, permission, and disclaimer notice must appear in all copies of
27 ****************************************************************************/
35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
36 This file defines all structures and symbols for LPC8xx:
37 - Registers and bitfields
38 - peripheral base address
44 /******************************************************************************/
45 /* Processor and Core Peripherals */
46 /******************************************************************************/
47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
48 Configuration of the Cortex-M0+ Processor and Core Peripherals
53 * ==========================================================================
54 * ---------- Interrupt Number Definition -----------------------------------
55 * ==========================================================================
59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
68 SPI0_IRQn = 0, /*!< SPI0 */
69 SPI1_IRQn = 1, /*!< SPI1 */
70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
71 UART0_IRQn = 3, /*!< USART0 */
72 UART1_IRQn = 4, /*!< USART1 */
73 UART2_IRQn = 5, /*!< USART2 */
74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
76 I2C_IRQn = 8, /*!< I2C */
77 SCT_IRQn = 9, /*!< SCT */
78 MRT_IRQn = 10, /*!< MRT */
79 CMP_IRQn = 11, /*!< CMP */
80 WDT_IRQn = 12, /*!< WDT */
81 BOD_IRQn = 13, /*!< BOD */
82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
83 WKT_IRQn = 15, /*!< WKT Interrupt */
84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
103 * ==========================================================================
104 * ----------- Processor and Core Peripheral Section ------------------------
105 * ==========================================================================
108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
109 #define __MPU_PRESENT 0 /*!< MPU present or not */
110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
114 /*@}*/ /* end of group LPC8xx_CMSIS */
117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
118 #include "system_LPC8xx.h" /* System Header */
121 /******************************************************************************/
122 /* Device Specific Peripheral Registers structures */
123 /******************************************************************************/
125 #if defined ( __CC_ARM )
129 /*------------- System Control (SYSCON) --------------------------------------*/
130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
139 uint32_t RESERVED0[4];
141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
143 uint32_t RESERVED1[2];
144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
145 uint32_t RESERVED2[3];
146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
148 uint32_t RESERVED3[10];
150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
153 uint32_t RESERVED4[1];
155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
156 uint32_t RESERVED5[4];
157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
158 uint32_t RESERVED6[18];
160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
166 uint32_t RESERVED8[1];
167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
169 uint32_t RESERVED9[12];
170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
173 uint32_t RESERVED10[6];
174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
177 uint32_t RESERVED11[27];
178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
179 uint32_t RESERVED12[3];
180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
181 uint32_t RESERVED13[6];
182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
185 uint32_t RESERVED14[110];
186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
187 } LPC_SYSCON_TypeDef;
188 /*@}*/ /* end of group LPC8xx_SYSCON */
192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
216 /*@}*/ /* end of group LPC8xx_IOCON */
219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
222 __I uint32_t RESERVED0[4];
223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
224 __I uint32_t RESERVED1[3];
225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
227 __I uint32_t RESERVED2;
229 } LPC_FLASHCTRL_TypeDef;
230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
233 /*------------- Power Management Unit (PMU) --------------------------*/
234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
246 /*@}*/ /* end of group LPC8xx_PMU */
249 /*------------- Switch Matrix Port --------------------------*/
250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
256 __IO uint32_t PINASSIGN[9];
258 __IO uint32_t PINASSIGN0;
259 __IO uint32_t PINASSIGN1;
260 __IO uint32_t PINASSIGN2;
261 __IO uint32_t PINASSIGN3;
262 __IO uint32_t PINASSIGN4;
263 __IO uint32_t PINASSIGN5;
264 __IO uint32_t PINASSIGN6;
265 __IO uint32_t PINASSIGN7;
266 __IO uint32_t PINASSIGN8;
269 __I uint32_t RESERVED0[103];
270 __IO uint32_t PINENABLE0;
272 /*@}*/ /* end of group LPC8xx_SWM */
275 // ------------------------------------------------------------------------------------------------
276 // ----- GPIO_PORT -----
277 // ------------------------------------------------------------------------------------------------
280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
285 __I uint16_t RESERVED0[2039];
286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
287 uint32_t RESERVED1[1006];
288 __IO uint32_t DIR0; /* 0x2000 */
289 uint32_t RESERVED2[31];
290 __IO uint32_t MASK0; /* 0x2080 */
291 uint32_t RESERVED3[31];
292 __IO uint32_t PIN0; /* 0x2100 */
293 uint32_t RESERVED4[31];
294 __IO uint32_t MPIN0; /* 0x2180 */
295 uint32_t RESERVED5[31];
296 __IO uint32_t SET0; /* 0x2200 */
297 uint32_t RESERVED6[31];
298 __O uint32_t CLR0; /* 0x2280 */
299 uint32_t RESERVED7[31];
300 __O uint32_t NOT0; /* 0x2300 */
302 } LPC_GPIO_PORT_TypeDef;
305 // ------------------------------------------------------------------------------------------------
306 // ----- PIN_INT -----
307 // ------------------------------------------------------------------------------------------------
310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
327 } LPC_PIN_INT_TypeDef;
330 /*------------- CRC Engine (CRC) -----------------------------------------*/
331 /** @addtogroup LPC8xx_CRC
340 __O uint32_t WR_DATA_DWORD;
341 __O uint16_t WR_DATA_WORD;
342 uint16_t RESERVED_WORD;
343 __O uint8_t WR_DATA_BYTE;
344 uint8_t RESERVED_BYTE[3];
347 /*@}*/ /* end of group LPC8xx_CRC */
349 /*------------- Comparator (CMP) --------------------------------------------------*/
350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
357 /*@}*/ /* end of group LPC8xx_CMP */
360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
361 /** @addtogroup LPC8xx_WKT
364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
366 uint32_t Reserved[2];
367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
369 /*@}*/ /* end of group LPC8xx_WKT */
371 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
372 //New, Copied from lpc824
374 * @brief Multi-Rate Timer (MRT) (MRT)
376 typedef struct { /*!< (@ 0x40004000) MRT Structure */
377 __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
378 is loaded into the TIMER0 register. */
379 __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
380 value of the down-counter. */
381 __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
383 __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
384 __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
385 is loaded into the TIMER0 register. */
386 __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
387 value of the down-counter. */
388 __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
390 __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
391 __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
392 is loaded into the TIMER0 register. */
393 __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
394 value of the down-counter. */
395 __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
397 __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
398 __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
399 is loaded into the TIMER0 register. */
400 __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
401 value of the down-counter. */
402 __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
404 __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
405 __I uint32_t RESERVED0[45];
406 __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
407 the number of the first idle channel. */
408 __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
411 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
412 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
416 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
420 __IO uint32_t CFG; /* 0x00 */
423 __IO uint32_t INTENSET;
424 __O uint32_t INTENCLR; /* 0x10 */
426 __I uint32_t RXDATA_STAT;
427 __IO uint32_t TXDATA;
428 __IO uint32_t BRG; /* 0x20 */
429 __IO uint32_t INTSTAT;
432 /*@}*/ /* end of group LPC8xx_USART */
435 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
436 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
441 __IO uint32_t CFG; /* 0x00 */
444 __IO uint32_t INTENSET;
445 __O uint32_t INTENCLR; /* 0x10 */
447 __IO uint32_t TXDATCTL;
449 __IO uint32_t TXCTRL; /* 0x20 */
451 __I uint32_t INTSTAT;
453 /*@}*/ /* end of group LPC8xx_SPI */
456 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
457 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
462 __IO uint32_t CFG; /* 0x00 */
464 __IO uint32_t INTENSET;
465 __O uint32_t INTENCLR;
466 __IO uint32_t TIMEOUT; /* 0x10 */
468 __IO uint32_t INTSTAT;
469 uint32_t Reserved0[1];
470 __IO uint32_t MSTCTL; /* 0x20 */
471 __IO uint32_t MSTTIME;
472 __IO uint32_t MSTDAT;
473 uint32_t Reserved1[5];
474 __IO uint32_t SLVCTL; /* 0x40 */
475 __IO uint32_t SLVDAT;
476 __IO uint32_t SLVADR0;
477 __IO uint32_t SLVADR1;
478 __IO uint32_t SLVADR2; /* 0x50 */
479 __IO uint32_t SLVADR3;
480 __IO uint32_t SLVQUAL0;
481 uint32_t Reserved2[9];
482 __I uint32_t MONRXDAT; /* 0x80 */
485 /*@}*/ /* end of group LPC8xx_I2C */
488 * @brief State Configurable Timer (SCT) (SCT)
492 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
495 #define CONFIG_SCT_nEV (6) /* Number of events */
496 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
497 #define CONFIG_SCT_nOU (4) /* Number of outputs */
501 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
503 __IO uint32_t CTRL_U; /* 0x004 Control Register */
505 __IO uint16_t CTRL_L; /* 0x004 low control register */
506 __IO uint16_t CTRL_H; /* 0x006 high control register */
509 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
510 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
511 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
512 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
513 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
514 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
515 __IO uint16_t START_L; /* 0x014 start register for counter L */
516 __IO uint16_t START_H; /* 0x016 start register for counter H */
517 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
519 __IO uint32_t COUNT_U; /* 0x040 counter register */
521 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
522 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
525 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
526 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
527 __I uint32_t INPUT; /* 0x048 input register */
528 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
529 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
530 __IO uint32_t OUTPUT; /* 0x050 output register */
531 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
532 __IO uint32_t RES; /* 0x058 conflict resolution register */
533 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
534 __IO uint32_t EVEN; /* 0x0F0 event enable register */
535 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
536 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
537 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
540 __IO union { /* 0x100-... Match / Capture value */
541 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
543 uint16_t L; /* SCTMATCH[i].L Access to L value */
544 uint16_t H; /* SCTMATCH[i].H Access to H value */
546 } MATCH[CONFIG_SCT_nRG];
548 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
550 uint16_t L; /* SCTCAP[i].L Access to H value */
551 uint16_t H; /* SCTCAP[i].H Access to H value */
553 } CAP[CONFIG_SCT_nRG];
557 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
560 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
561 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
563 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
565 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
566 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
569 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
573 __IO union { /* 0x200-... Match Reload / Capture Control value */
574 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
576 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
577 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
579 } MATCHREL[CONFIG_SCT_nRG];
581 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
583 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
584 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
586 } CAPCTRL[CONFIG_SCT_nRG];
589 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
592 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
593 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
595 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
597 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
598 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
600 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
602 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
603 uint32_t STATE; /* Event State Register */
604 uint32_t CTRL; /* Event Control Register */
605 } EVENT[CONFIG_SCT_nEV];
607 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
609 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
610 uint32_t SET; /* Output n Set Register */
611 uint32_t CLR; /* Output n Clear Register */
612 } OUT[CONFIG_SCT_nOU];
614 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
616 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
619 /*@}*/ /* end of group LPC8xx_SCT */
622 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
623 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
628 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
629 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
630 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
631 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
632 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
633 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
634 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
636 /*@}*/ /* end of group LPC8xx_WDT */
639 #if defined ( __CC_ARM )
640 #pragma no_anon_unions
643 /******************************************************************************/
644 /* Peripheral memory map */
645 /******************************************************************************/
647 #define LPC_FLASH_BASE (0x00000000UL)
648 #define LPC_RAM_BASE (0x10000000UL)
649 #define LPC_ROM_BASE (0x1FFF0000UL)
650 #define LPC_APB0_BASE (0x40000000UL)
651 #define LPC_AHB_BASE (0x50000000UL)
653 /* APB0 peripherals */
654 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
655 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
656 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
657 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
658 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
659 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
661 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
662 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
663 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
664 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
665 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
666 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
667 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
668 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
669 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
671 /* AHB peripherals */
672 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
673 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
675 #define LPC_GPIO_PORT_BASE (0xA0000000)
676 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
678 /******************************************************************************/
679 /* Peripheral declaration */
680 /******************************************************************************/
681 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
682 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
685 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
686 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
687 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
688 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
690 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
691 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
692 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
693 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
694 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
695 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
696 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
697 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
698 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
700 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
701 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
703 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
704 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
710 #endif /* __LPC8xx_H__ */