2 ******************************************************************************
3 * @file stm32f0xx_hal_dma_ex.h
4 * @author MCD Application Team
6 * @date 11-December-2014
7 * @brief Header file of DMA HAL Extension module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F0xx_HAL_DMA_EX_H
40 #define __STM32F0xx_HAL_DMA_EX_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f0xx_hal_def.h"
49 /** @addtogroup STM32F0xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
58 /* Exported constants --------------------------------------------------------*/
59 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
60 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
63 #define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
64 #define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
65 #define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
66 #define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
67 #define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
68 #if !defined(STM32F030xC)
69 #define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
70 #define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
71 #define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
72 #define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
73 #define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
74 #define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
75 #define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
76 #endif /* !defined(STM32F030xC) */
78 /****************** DMA1 remap bit field definition********************/
79 /* DMA1 - Channel 1 */
80 #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
81 #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
82 #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
83 #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
84 #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
85 #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
86 #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
87 #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
88 #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
89 #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
90 #if !defined(STM32F030xC)
91 #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
92 #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
93 #endif /* !defined(STM32F030xC) */
95 /* DMA1 - Channel 2 */
96 #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
97 #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
98 #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
99 #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
100 #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
101 #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
102 #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
103 #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
104 #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
105 #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
106 #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
107 #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
108 #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
109 #if !defined(STM32F030xC)
110 #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
111 #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
112 #endif /* !defined(STM32F030xC) */
114 /* DMA1 - Channel 3 */
115 #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
116 #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
117 #if !defined(STM32F030xC)
118 #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
119 #endif /* !defined(STM32F030xC) */
120 #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
121 #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
122 #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
123 #if !defined(STM32F030xC)
124 #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
125 #endif /* !defined(STM32F030xC) */
126 #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
127 #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
128 #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
129 #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
130 #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
131 #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
132 #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
133 #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
134 #if !defined(STM32F030xC)
135 #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
136 #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
137 #endif /* !defined(STM32F030xC) */
139 /* DMA1 - Channel 4 */
140 #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
141 #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
142 #if !defined(STM32F030xC)
143 #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
144 #endif /* !defined(STM32F030xC) */
145 #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
146 #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
147 #if !defined(STM32F030xC)
148 #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
149 #endif /* !defined(STM32F030xC) */
150 #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
151 #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
152 #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
153 #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
154 #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
155 #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
156 #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
157 #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
158 #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
159 #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
160 #if !defined(STM32F030xC)
161 #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
162 #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
163 #endif /* !defined(STM32F030xC) */
165 /* DMA1 - Channel 5 */
166 #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
167 #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
168 #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
169 #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
170 #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
171 #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
172 #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
173 #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
174 #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
175 #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
176 #if !defined(STM32F030xC)
177 #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
178 #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
179 #endif /* !defined(STM32F030xC) */
181 #if !defined(STM32F030xC)
182 /* DMA1 - Channel 6 */
183 #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
184 #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
185 #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
186 #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
187 #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
188 #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
189 #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
190 #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
191 #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
192 #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
193 #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
194 #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
195 #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
196 #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
197 #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
198 #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
199 #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
200 #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
201 /* DMA1 - Channel 7 */
202 #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
203 #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
204 #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
205 #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
206 #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
207 #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
208 #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
209 #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
210 #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
211 #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
212 #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
213 #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
214 #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
215 #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
216 #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
218 /****************** DMA2 remap bit field definition********************/
219 /* DMA2 - Channel 1 */
220 #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
221 #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
222 #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
223 #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
224 #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
225 #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
226 #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
227 #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
228 #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
229 #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
230 /* DMA2 - Channel 2 */
231 #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
232 #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
233 #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
234 #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
235 #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
236 #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
237 #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
238 #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
239 #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
240 #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
241 /* DMA2 - Channel 3 */
242 #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
243 #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
244 #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
245 #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
246 #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
247 #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
248 #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
249 #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
250 #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
251 #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
252 #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
253 #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
254 /* DMA2 - Channel 4 */
255 #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
256 #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
257 #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
258 #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
259 #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
260 #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
261 #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
262 #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
263 #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
264 #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
265 #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
266 #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
267 /* DMA2 - Channel 5 */
268 #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
269 #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
270 #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
271 #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
272 #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
273 #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
274 #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
275 #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
276 #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
277 #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
278 #endif /* !defined(STM32F030xC) */
280 #if defined(STM32F091xC) || defined(STM32F098xx)
281 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
282 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
283 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
284 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
285 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
286 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
287 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
288 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
289 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
290 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
291 ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
292 ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
293 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
294 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
295 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
296 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
297 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
298 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
299 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
300 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
301 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
302 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
303 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
304 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
305 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
306 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
307 ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
308 ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
309 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
310 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
311 ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
312 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
313 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
314 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
315 ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
316 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
317 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
318 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
319 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
320 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
321 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
322 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
323 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
324 ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
325 ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
326 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
327 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
328 ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
329 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
330 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
331 ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
332 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
333 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
334 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
335 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
336 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
337 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
338 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
339 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
340 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
341 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
342 ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
343 ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
344 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
345 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
346 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
347 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
348 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
349 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
350 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
351 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
352 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
353 ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
354 ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
355 ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
356 ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
357 ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
358 ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
359 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
360 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
361 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
362 ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
363 ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
364 ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
365 ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
366 ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
367 ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
368 ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
369 ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
370 ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
371 ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
372 ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
373 ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
374 ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
375 ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
376 ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
377 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
378 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
379 ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
380 ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
381 ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
382 ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
383 ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
384 ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
385 ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
386 ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
387 ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
388 ((REQUEST) == HAL_DMA1_CH7_USART8_TX))
390 #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
391 ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
392 ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
393 ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
394 ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
395 ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
396 ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
397 ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
398 ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
399 ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
400 ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
401 ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
402 ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
403 ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
404 ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
405 ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
406 ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
407 ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
408 ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
409 ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
410 ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
411 ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
412 ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
413 ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
414 ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
415 ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
416 ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
417 ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
418 ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
419 ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
420 ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
421 ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
422 ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
423 ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
424 ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
425 ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
426 ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
427 ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
428 ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
429 ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
430 ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
431 ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
432 ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
433 ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
434 ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
435 ((REQUEST) == HAL_DMA2_CH5_ADC) ||\
436 ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
437 ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
438 ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
439 ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
440 ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
441 ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
442 ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
443 ((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
444 #endif /* STM32F091xC || STM32F098xx */
446 #if defined(STM32F030xC)
447 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
448 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
449 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
450 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
451 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
452 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
453 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
454 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
455 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
456 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
457 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
458 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
459 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
460 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
461 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
462 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
463 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
464 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
465 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
466 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
467 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
468 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
469 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
470 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
471 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
472 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
473 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
474 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
475 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
476 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
477 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
478 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
479 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
480 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
481 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
482 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
483 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
484 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
485 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
486 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
487 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
488 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
489 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
490 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
491 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
492 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
493 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
494 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
495 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
496 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
497 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
498 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
499 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
500 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
501 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
502 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
503 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
504 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
505 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
506 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
507 ((REQUEST) == HAL_DMA1_CH5_USART6_RX))
508 #endif /* STM32F030xC */
513 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
515 /* Exported macros -----------------------------------------------------------*/
517 /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
520 /* Interrupt & Flag management */
522 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
524 * @brief Returns the current DMA Channel transfer complete flag.
525 * @param __HANDLE__: DMA handle
526 * @retval The specified transfer complete flag index.
528 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
529 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
538 * @brief Returns the current DMA Channel half transfer complete flag.
539 * @param __HANDLE__: DMA handle
540 * @retval The specified half transfer complete flag index.
542 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
543 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
552 * @brief Returns the current DMA Channel transfer error flag.
553 * @param __HANDLE__: DMA handle
554 * @retval The specified transfer error flag index.
556 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
557 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
566 * @brief Get the DMA Channel pending flags.
567 * @param __HANDLE__: DMA handle
568 * @param __FLAG__: Get the specified flag.
569 * This parameter can be any combination of the following values:
570 * @arg DMA_FLAG_TCx: Transfer complete flag
571 * @arg DMA_FLAG_HTx: Half transfer complete flag
572 * @arg DMA_FLAG_TEx: Transfer error flag
573 * Where x can be 1_7 to select the DMA Channel flag.
574 * @retval The state of FLAG (SET or RESET).
577 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
580 * @brief Clears the DMA Channel pending flags.
581 * @param __HANDLE__: DMA handle
582 * @param __FLAG__: specifies the flag to clear.
583 * This parameter can be any combination of the following values:
584 * @arg DMA_FLAG_TCx: Transfer complete flag
585 * @arg DMA_FLAG_HTx: Half transfer complete flag
586 * @arg DMA_FLAG_TEx: Transfer error flag
587 * Where x can be 1_7 to select the DMA Channel flag.
590 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
592 #elif defined(STM32F091xC) || defined(STM32F098xx)
594 * @brief Returns the current DMA Channel transfer complete flag.
595 * @param __HANDLE__: DMA handle
596 * @retval The specified transfer complete flag index.
598 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
599 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
601 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
602 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
603 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
604 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
605 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
606 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
607 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
608 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
609 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
613 * @brief Returns the current DMA Channel half transfer complete flag.
614 * @param __HANDLE__: DMA handle
615 * @retval The specified half transfer complete flag index.
617 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
618 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
622 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
623 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
624 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
625 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
626 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
627 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
628 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
632 * @brief Returns the current DMA Channel transfer error flag.
633 * @param __HANDLE__: DMA handle
634 * @retval The specified transfer error flag index.
636 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
637 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
641 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
642 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
643 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
644 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
645 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
646 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
647 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
651 * @brief Get the DMA Channel pending flags.
652 * @param __HANDLE__: DMA handle
653 * @param __FLAG__: Get the specified flag.
654 * This parameter can be any combination of the following values:
655 * @arg DMA_FLAG_TCx: Transfer complete flag
656 * @arg DMA_FLAG_HTx: Half transfer complete flag
657 * @arg DMA_FLAG_TEx: Transfer error flag
658 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
659 * @retval The state of FLAG (SET or RESET).
662 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
663 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
664 (DMA1->ISR & (__FLAG__)))
667 * @brief Clears the DMA Channel pending flags.
668 * @param __HANDLE__: DMA handle
669 * @param __FLAG__: specifies the flag to clear.
670 * This parameter can be any combination of the following values:
671 * @arg DMA_FLAG_TCx: Transfer complete flag
672 * @arg DMA_FLAG_HTx: Half transfer complete flag
673 * @arg DMA_FLAG_TEx: Transfer error flag
674 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
677 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
678 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
679 (DMA1->IFCR = (__FLAG__)))
681 #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
683 * @brief Returns the current DMA Channel transfer complete flag.
684 * @param __HANDLE__: DMA handle
685 * @retval The specified transfer complete flag index.
687 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
688 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
689 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
690 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
691 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
695 * @brief Returns the current DMA Channel half transfer complete flag.
696 * @param __HANDLE__: DMA handle
697 * @retval The specified half transfer complete flag index.
699 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
700 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
701 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
702 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
703 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
707 * @brief Returns the current DMA Channel transfer error flag.
708 * @param __HANDLE__: DMA handle
709 * @retval The specified transfer error flag index.
711 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
712 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
713 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
714 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
715 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
719 * @brief Get the DMA Channel pending flags.
720 * @param __HANDLE__: DMA handle
721 * @param __FLAG__: Get the specified flag.
722 * This parameter can be any combination of the following values:
723 * @arg DMA_FLAG_TCx: Transfer complete flag
724 * @arg DMA_FLAG_HTx: Half transfer complete flag
725 * @arg DMA_FLAG_TEx: Transfer error flag
726 * Where x can be 1_5 to select the DMA Channel flag.
727 * @retval The state of FLAG (SET or RESET).
730 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
733 * @brief Clears the DMA Channel pending flags.
734 * @param __HANDLE__: DMA handle
735 * @param __FLAG__: specifies the flag to clear.
736 * This parameter can be any combination of the following values:
737 * @arg DMA_FLAG_TCx: Transfer complete flag
738 * @arg DMA_FLAG_HTx: Half transfer complete flag
739 * @arg DMA_FLAG_TEx: Transfer error flag
740 * Where x can be 1_5 to select the DMA Channel flag.
743 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
748 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
749 #define __HAL_DMA1_REMAP(__REQUEST__) \
750 do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
751 DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
752 DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
755 #if defined(STM32F091xC) || defined(STM32F098xx)
756 #define __HAL_DMA2_REMAP(__REQUEST__) \
757 do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
758 DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
759 DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
761 #endif /* STM32F091xC || STM32F098xx */
763 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
781 #endif /* __STM32F0xx_HAL_DMA_EX_H */
783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/