2 ******************************************************************************
3 * @file stm32f0xx_hal_rcc.c
4 * @author MCD Application Team
6 * @date 11-December-2014
7 * @brief RCC HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Reset and Clock Control (RCC) peripheral:
10 * + Initialization and de-initialization functions
11 * + Peripheral Control functions
14 ==============================================================================
15 ##### RCC specific features #####
16 ==============================================================================
18 After reset the device is running from Internal High Speed oscillator
19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
20 and all peripherals are off except internal SRAM, Flash and JTAG.
21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
22 all peripherals mapped on these busses are running at HSI speed.
23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
24 (+) All GPIOs are in input floating state, except the JTAG pins which
25 are assigned to be used for debug purpose.
26 [..] Once the device started from reset, the user application has to:
27 (+) Configure the clock source to be used to drive the System clock
28 (if the application needs higher frequency/performance)
29 (+) Configure the System clock frequency and Flash settings
30 (+) Configure the AHB and APB busses prescalers
31 (+) Enable the clock for the peripheral(s) to be used
32 (+) Configure the clock source(s) for peripherals which clocks are not
33 derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
35 ##### RCC Limitations #####
36 ==============================================================================
38 A delay between an RCC peripheral clock enable and the effective peripheral
39 enabling should be taken into account in order to manage the peripheral read/write
41 (+) This delay depends on the peripheral mapping.
42 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
43 after the clock enable bit is set on the hardware register
44 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
45 after the clock enable bit is set on the hardware register
49 (#) Enable the peripheral clock sometimes before the peripheral read/write
51 (#) For AHB peripheral, insert two dummy read to the peripheral register.
52 (#) For APB peripheral, insert a dummy read to the peripheral register.
55 ******************************************************************************
58 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 ******************************************************************************
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f0xx_hal.h"
88 /** @addtogroup STM32F0xx_HAL_Driver
92 /** @defgroup RCC RCC HAL module driver
93 * @brief RCC HAL module driver
97 #ifdef HAL_RCC_MODULE_ENABLED
99 /* Private typedef -----------------------------------------------------------*/
100 /* Private define ------------------------------------------------------------*/
101 /** @defgroup RCC_Private_Define RCC Private Define
104 #define RCC_CFGR_HPRE_BITNUMBER 4
105 #define RCC_CFGR_PPRE_BITNUMBER 8
110 /* Private macro -------------------------------------------------------------*/
111 /** @defgroup RCC_Private_Macros RCC Private Macros
114 #define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
115 #define MCO_GPIO_PORT GPIOA
116 #define MCO_PIN GPIO_PIN_8
121 /* Private variables ---------------------------------------------------------*/
122 /** @defgroup RCC_Private_Variables RCC Private Variables
125 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
130 /* Private function prototypes -----------------------------------------------*/
131 /* Exported functions ---------------------------------------------------------*/
133 /** @defgroup RCC_Exported_Functions RCC Exported Functions
137 /** @defgroup RCC_Exported_Functions_Group1 Initialization/de-initialization function
138 * @brief Initialization and Configuration functions
141 ===============================================================================
142 ##### Initialization and de-initialization function #####
143 ===============================================================================
145 This section provide functions allowing to configure the internal/external oscillators
146 (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK,
149 [..] Internal/external clock and PLL configuration
150 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
151 the PLL as System clock source.
152 The HSI clock can be used also to clock the USART and I2C peripherals.
154 (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
157 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
160 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
161 through the PLL as System clock source. Can be used also as RTC clock source.
163 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
165 (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
166 (++) The first output is used to generate the high speed system clock (up to 48 MHz)
167 (++) The second output is used to generate the clock for the USB FS (48 MHz)
168 (++) The third output may be used to generate the clock for the TIM, I2C and USART
169 peripherals (up to 48 MHz)
171 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
172 and if a HSE clock failure occurs(HSE used directly or through PLL as System
173 clock source), the System clockis automatically switched to HSI and an interrupt
174 is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
175 (Non-Maskable Interrupt) exception vector.
177 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
178 clock (divided by 2) output on pin (such as PA8 pin).
180 [..] System, AHB and APB busses clocks configuration
181 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
183 The AHB clock (HCLK) is derived from System clock through configurable
184 prescaler and used to clock the CPU, memory and peripherals mapped
185 on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
186 from AHB clock through configurable prescalers and used to clock
187 the peripherals mapped on these busses. You can use
188 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
190 (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
191 (++) The FLASH program/erase clock which is always HSI 8MHz clock.
192 (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
193 (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
194 (++) The I2C clock which can be derived as well from HSI 8MHz clock.
195 (++) The ADC clock which is derived from PLL output.
196 (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
197 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
198 frequency must be higher or equal to the RTC clock frequency.
199 (++) IWDG clock which is always the LSI clock.
201 (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
202 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
203 +-----------------------------------------------+
204 | Latency | SYSCLK clock frequency (MHz) |
205 |---------------|-------------------------------|
206 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
207 |---------------|-------------------------------|
208 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
209 +-----------------------------------------------+
211 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
212 prefetch is disabled.
219 * @brief Resets the RCC clock configuration to the default reset state.
220 * @note The default reset state of the clock configuration is given below:
221 * - HSI ON and used as system clock source
223 * - AHB, APB1 prescaler set to 1.
225 * - All interrupts disabled
226 * @note This function doesn't modify the configuration of the
227 * - Peripheral clocks
228 * - LSI, LSE and RTC clocks
231 void HAL_RCC_DeInit(void)
233 /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
234 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
236 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
237 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);
239 /* Reset HSEON, CSSON, PLLON bits */
240 CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
242 /* Reset HSEBYP bit */
243 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
245 /* Reset CFGR register */
246 CLEAR_REG(RCC->CFGR);
248 /* Reset CFGR2 register */
249 CLEAR_REG(RCC->CFGR2);
251 /* Reset CFGR3 register */
252 CLEAR_REG(RCC->CFGR3);
254 /* Disable all interrupts */
259 * @brief Initializes the RCC Oscillators according to the specified parameters in the
260 * RCC_OscInitTypeDef.
261 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
262 * contains the configuration information for the RCC Oscillators.
263 * @note The PLL is not disabled when used as system clock.
266 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
268 /* Note : This function is defined into this file for library reference. */
269 /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
270 /* handle the possible oscillators present in STM32F0xx devices */
272 /* Return error status as not implemented here */
277 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
278 * parameters in the RCC_ClkInitStruct.
279 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
280 * contains the configuration information for the RCC peripheral.
281 * @param FLatency: FLASH Latency
282 * This parameter can be one of the following values:
283 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
284 * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
286 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
287 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
289 * @note The HSI is used (enabled by hardware) as system clock source after
290 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
291 * of failure of the HSE used directly or indirectly as system clock
292 * (if the Clock Security System CSS is enabled).
294 * @note A switch from one clock source to another occurs only if the target
295 * clock source is ready (clock stable after startup delay or PLL locked).
296 * If a clock source which is not yet ready is selected, the switch will
297 * occur when the clock source will be ready.
300 __weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
302 /* Note : This function is defined into this file for library reference. */
303 /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
304 /* handle the possible oscillators present in STM32F0xx devices */
306 /* Return error status as not implemented here */
314 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control function
315 * @brief RCC clocks control functions
318 ===============================================================================
319 ##### Peripheral Control function #####
320 ===============================================================================
322 This subsection provides a set of functions allowing to control the RCC Clocks
330 * @brief Selects the clock source to output on MCO pin(such as PA8).
331 * @note MCO pin (such as PA8) should be configured in alternate function mode.
332 * @param RCC_MCOx: specifies the output direction for the clock source.
333 * This parameter can be one of the following values:
334 * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8).
335 * @param RCC_MCOSource: specifies the clock source to output.
336 * This parameter can be one of the following values:
337 * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source
338 * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source
339 * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source
340 * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source
341 * @arg RCC_MCOSOURCE_PLLCLK_NODIV: main PLL clock not divided selected as MCO source (not applicable to STM32F05x devices)
342 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source
343 * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source
344 * @param RCC_MCODiv: specifies the MCOx prescaler.
345 * This parameter can be one of the following values:
346 * @arg RCC_MCO_NODIV: no division applied to MCO clock
349 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
351 GPIO_InitTypeDef gpio;
352 /* Check the parameters */
353 assert_param(IS_RCC_MCO(RCC_MCOx));
354 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
356 assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource));
358 /* MCO Clock Enable */
361 /* Configue the MCO pin in alternate function mode */
363 gpio.Mode = GPIO_MODE_AF_PP;
364 gpio.Speed = GPIO_SPEED_HIGH;
365 gpio.Pull = GPIO_NOPULL;
366 gpio.Alternate = GPIO_AF0_MCO;
367 HAL_GPIO_Init(MCO_GPIO_PORT, &gpio);
369 /* Configure the MCO clock source */
370 __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv);
374 * @brief Enables the Clock Security System.
375 * @note If a failure is detected on the HSE oscillator clock, this oscillator
376 * is automatically disabled and an interrupt is generated to inform the
377 * software about the failure (Clock Security System Interrupt, CSSI),
378 * allowing the MCU to perform rescue operations. The CSSI is linked to
379 * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
382 void HAL_RCC_EnableCSS(void)
384 SET_BIT(RCC->CR, RCC_CR_CSSON);
388 * @brief Disables the Clock Security System.
391 void HAL_RCC_DisableCSS(void)
393 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
397 * @brief Returns the SYSCLK frequency
398 * @note The system frequency computed by this function is not the real
399 * frequency in the chip. It is calculated based on the predefined
400 * constant and the selected clock source:
401 * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*)
402 * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*)
403 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
404 * divided by PREDIV factor(**)
405 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
406 * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based
407 * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
409 * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file
410 * (default values 8 MHz and 48MHz).
411 * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
412 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
413 * frequency of the crystal used. Otherwise, this function may
416 * @note The result of this function could be not correct when using fractional
417 * value for HSE crystal.
419 * @note This function can be used by the user application to compute the
420 * baudrate for the communication peripherals or configure other parameters.
422 * @note Each time SYSCLK changes, this function must be called to update the
423 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
425 * @retval SYSCLK frequency
427 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
429 /* Note : This function is defined into this file for library reference. */
430 /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
431 /* handle the possible oscillators present in STM32F0xx devices */
433 /* Return error status as not implemented here */
438 * @brief Returns the HCLK frequency
439 * @note Each time HCLK changes, this function must be called to update the
440 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
442 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
443 * and updated within this function
445 * @retval HCLK frequency
447 uint32_t HAL_RCC_GetHCLKFreq(void)
449 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
450 return SystemCoreClock;
454 * @brief Returns the PCLK1 frequency
455 * @note Each time PCLK1 changes, this function must be called to update the
456 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
457 * @retval PCLK1 frequency
459 uint32_t HAL_RCC_GetPCLK1Freq(void)
461 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
462 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
466 * @brief Configures the RCC_OscInitStruct according to the internal
467 * RCC configuration registers.
468 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
469 * will be configured.
472 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
474 /* Set all possible values for the Oscillator type parameter ---------------*/
475 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
477 /* Get the HSE configuration -----------------------------------------------*/
478 if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
480 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
482 else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
484 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
488 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
491 /* Get the HSI configuration -----------------------------------------------*/
492 if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
494 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
498 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
501 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
503 /* Get the LSE configuration -----------------------------------------------*/
504 if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
506 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
508 else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
510 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
514 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
517 /* Get the LSI configuration -----------------------------------------------*/
518 if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
520 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
524 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
527 /* Get the PLL configuration -----------------------------------------------*/
528 if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
530 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
534 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
536 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
537 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
538 RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
540 /* Get the HSI14 configuration -----------------------------------------------*/
541 if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
543 RCC_OscInitStruct->HSI14State = RCC_HSI_ON;
547 RCC_OscInitStruct->HSI14State = RCC_HSI_OFF;
550 RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber);
552 /* Get the HSI48 configuration if any-----------------------------------------*/
553 RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
557 * @brief Get the RCC_ClkInitStruct according to the internal
558 * RCC configuration registers.
559 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
560 * contains the current clock configuration.
561 * @param pFLatency: Pointer on the Flash Latency.
564 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
566 /* Set all possible values for the Clock type parameter --------------------*/
567 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
569 /* Get the SYSCLK configuration --------------------------------------------*/
570 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
572 /* Get the HCLK configuration ----------------------------------------------*/
573 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
575 /* Get the APB1 configuration ----------------------------------------------*/
576 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
578 /* Get the Flash Wait State (Latency) configuration ------------------------*/
579 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
583 * @brief This function handles the RCC CSS interrupt request.
584 * @note This API should be called under the NMI_Handler().
587 void HAL_RCC_NMI_IRQHandler(void)
589 /* Check RCC CSSF flag */
590 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
592 /* RCC Clock Security System interrupt user callback */
593 HAL_RCC_CCSCallback();
595 /* Clear RCC CSS pending bit */
596 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
601 * @brief RCC Clock Security System interrupt callback
604 __weak void HAL_RCC_CCSCallback(void)
606 /* NOTE : This function Should not be modified, when the callback is needed,
607 the HAL_RCC_CCSCallback could be implemented in the user file
619 #endif /* HAL_RCC_MODULE_ENABLED */
628 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/