2 ******************************************************************************
3 * @file stm32f0xx_hal_rcc_ex.h
4 * @author MCD Application Team
6 * @date 11-December-2014
7 * @brief Header file of RCC HAL Extension module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F0xx_HAL_RCC_EX_H
40 #define __STM32F0xx_HAL_RCC_EX_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f0xx_hal_def.h"
49 /** @addtogroup STM32F0xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
64 * @brief RCC extended clocks structure definition
66 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
70 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
71 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
73 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
74 This parameter can be a value of @ref RCC_RTC_Clock_Source */
76 uint32_t Usart1ClockSelection; /*!< USART1 clock source
77 This parameter can be a value of @ref RCC_USART1_Clock_Source */
79 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
80 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
82 }RCC_PeriphCLKInitTypeDef;
83 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
86 #if defined(STM32F070x6) || defined(STM32F070xB)
89 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
90 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
92 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
93 This parameter can be a value of @ref RCC_RTC_Clock_Source */
95 uint32_t Usart1ClockSelection; /*!< USART1 clock source
96 This parameter can be a value of @ref RCC_USART1_Clock_Source */
98 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
99 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
101 uint32_t UsbClockSelection; /*!< USB clock source
102 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
104 }RCC_PeriphCLKInitTypeDef;
105 #endif /* STM32F070x6 || STM32F070xB */
107 #if defined(STM32F042x6) || defined(STM32F048xx)
110 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
111 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
113 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
114 This parameter can be a value of @ref RCC_RTC_Clock_Source */
116 uint32_t Usart1ClockSelection; /*!< USART1 clock source
117 This parameter can be a value of @ref RCC_USART1_Clock_Source */
119 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
120 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
122 uint32_t CecClockSelection; /*!< HDMI CEC clock source
123 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
125 uint32_t UsbClockSelection; /*!< USB clock source
126 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
128 }RCC_PeriphCLKInitTypeDef;
129 #endif /* STM32F042x6 || STM32F048xx */
131 #if defined(STM32F051x8) || defined(STM32F058xx)
134 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
135 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
137 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
138 This parameter can be a value of @ref RCC_RTC_Clock_Source */
140 uint32_t Usart1ClockSelection; /*!< USART1 clock source
141 This parameter can be a value of @ref RCC_USART1_Clock_Source */
143 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
144 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
146 uint32_t CecClockSelection; /*!< HDMI CEC clock source
147 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
149 }RCC_PeriphCLKInitTypeDef;
150 #endif /* STM32F051x8 || STM32F058xx */
152 #if defined(STM32F071xB)
155 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
156 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
158 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
159 This parameter can be a value of @ref RCC_RTC_Clock_Source */
161 uint32_t Usart1ClockSelection; /*!< USART1 clock source
162 This parameter can be a value of @ref RCC_USART1_Clock_Source */
164 uint32_t Usart2ClockSelection; /*!< USART2 clock source
165 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
167 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
168 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
170 uint32_t CecClockSelection; /*!< HDMI CEC clock source
171 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
173 }RCC_PeriphCLKInitTypeDef;
174 #endif /* STM32F071xB */
176 #if defined(STM32F072xB) || defined(STM32F078xx)
179 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
180 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
182 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
183 This parameter can be a value of @ref RCC_RTC_Clock_Source */
185 uint32_t Usart1ClockSelection; /*!< USART1 clock source
186 This parameter can be a value of @ref RCC_USART1_Clock_Source */
188 uint32_t Usart2ClockSelection; /*!< USART2 clock source
189 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
191 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
192 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
194 uint32_t CecClockSelection; /*!< HDMI CEC clock source
195 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
197 uint32_t UsbClockSelection; /*!< USB clock source
198 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
200 }RCC_PeriphCLKInitTypeDef;
201 #endif /* STM32F072xB || STM32F078xx */
204 #if defined(STM32F091xC) || defined(STM32F098xx)
207 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
208 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
210 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
211 This parameter can be a value of @ref RCC_RTC_Clock_Source */
213 uint32_t Usart1ClockSelection; /*!< USART1 clock source
214 This parameter can be a value of @ref RCC_USART1_Clock_Source */
216 uint32_t Usart2ClockSelection; /*!< USART2 clock source
217 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
219 uint32_t Usart3ClockSelection; /*!< USART3 clock source
220 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
222 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
223 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
225 uint32_t CecClockSelection; /*!< HDMI CEC clock source
226 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
228 }RCC_PeriphCLKInitTypeDef;
229 #endif /* STM32F091xC || STM32F098xx */
231 #if defined(STM32F042x6) || defined(STM32F048xx) || \
232 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
233 defined(STM32F091xC) || defined(STM32F098xx)
236 * @brief RCC_CRS Init structure definition
240 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
241 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
243 uint32_t Source; /*!< Specifies the SYNC signal source.
244 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
246 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
247 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
249 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
250 It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
251 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
253 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
254 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
256 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
257 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
262 * @brief RCC_CRS Synchronization structure definition
266 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
267 This parameter must be a number between 0 and 0xFFFF*/
269 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
270 This parameter must be a number between 0 and 0x3F */
272 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
273 value latched in the time of the last SYNC event.
274 This parameter must be a number between 0 and 0xFFFF */
276 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
277 frequency error counter latched in the time of the last SYNC event.
278 It shows whether the actual frequency is below or above the target.
279 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
281 }RCC_CRSSynchroInfoTypeDef;
283 #endif /* STM32F042x6 || STM32F048xx */
284 /* STM32F071xB || STM32F072xB || STM32F078xx || */
285 /* STM32F091xC || STM32F098xx */
291 /* Exported constants --------------------------------------------------------*/
293 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
297 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
300 #if defined(STM32F042x6) || defined(STM32F048xx) || \
301 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
302 defined(STM32F091xC) || defined(STM32F098xx)
304 #define RCC_CRS_NONE ((uint32_t)0x00000000)
305 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
306 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
307 #define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
308 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
309 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
310 #define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
312 #endif /* STM32F042x6 || STM32F048xx */
313 /* STM32F071xB || STM32F072xB || STM32F078xx || */
314 /* STM32F091xC || STM32F098xx */
319 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
322 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
324 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
325 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
326 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
328 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
330 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
333 #if defined(STM32F070x6) || defined(STM32F070xB)
334 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
335 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
336 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
337 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
339 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
340 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
341 #endif /* STM32F070x6 || STM32F070xB */
343 #if defined(STM32F042x6) || defined(STM32F048xx)
344 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
345 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
346 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
347 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
348 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
350 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
351 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
353 #endif /* STM32F042x6 || STM32F048xx */
355 #if defined(STM32F051x8) || defined(STM32F058xx)
356 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
357 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
358 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
359 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
361 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
362 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
363 #endif /* STM32F051x8 || STM32F058xx */
365 #if defined(STM32F071xB)
366 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
367 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
368 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
369 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
370 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
372 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
373 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
375 #endif /* STM32F071xB */
377 #if defined(STM32F072xB) || defined(STM32F078xx)
378 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
379 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
380 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
381 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
382 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
383 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
385 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
386 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
387 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
388 #endif /* STM32F072xB || STM32F078xx */
390 #if defined(STM32F091xC) || defined(STM32F098xx)
391 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
392 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
393 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
394 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
395 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
396 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
398 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
399 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
400 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
401 #endif /* STM32F091xC || STM32F098xx */
407 /** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
411 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC)
413 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
415 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
416 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
417 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
418 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
419 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
420 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
421 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
422 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
423 ((SOURCE) == RCC_MCOSOURCE_HSI14))
425 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
427 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
429 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
430 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
431 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
432 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
433 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
434 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
435 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
436 ((SOURCE) == RCC_MCOSOURCE_HSI14))
438 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
440 #if defined(STM32F042x6) || defined(STM32F048xx) || \
441 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
442 defined(STM32F091xC) || defined(STM32F098xx)
444 #define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
445 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
447 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
448 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
449 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
450 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
451 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
452 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
453 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
454 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
455 ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
456 ((SOURCE) == RCC_MCOSOURCE_HSI48))
458 #define RCC_IT_HSI48 ((uint8_t)0x40)
460 /* Flags in the CR2 register */
461 #define RCC_CR2_HSI48RDY_BitNumber 16
463 #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
465 #endif /* STM32F042x6 || STM32F048xx || */
466 /* STM32F071xB || STM32F072xB || STM32F078xx || */
467 /* STM32F091xC || STM32F098xx */
472 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
474 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
477 #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
478 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
480 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
481 ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
486 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
488 #if defined(STM32F070x6) || defined(STM32F070xB)
490 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
493 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
495 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
500 #endif /* STM32F070x6 || STM32F070xB */
502 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
503 defined(STM32F091xC) || defined(STM32F098xx)
505 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
508 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
509 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
510 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
511 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
513 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
514 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
515 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
516 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
521 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
522 /* STM32F091xC || STM32F098xx */
524 #if defined(STM32F091xC) || defined(STM32F098xx)
526 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
529 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
530 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
531 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
532 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
534 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
535 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
536 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
537 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
542 #endif /* STM32F091xC || STM32F098xx */
545 #if defined(STM32F042x6) || defined(STM32F048xx) || \
546 defined(STM32F051x8) || defined(STM32F058xx) || \
547 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
548 defined(STM32F091xC) || defined(STM32F098xx)
550 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
553 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
554 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
556 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
557 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
562 #endif /* STM32F042x6 || STM32F048xx || */
563 /* STM32F051x8 || STM32F058xx || */
564 /* STM32F071xB || STM32F072xB || STM32F078xx || */
565 /* STM32F091xC || STM32F098xx */
567 #if defined(STM32F042x6) || defined(STM32F048xx) || \
568 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
569 defined(STM32F091xC) || defined(STM32F098xx)
571 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
574 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
575 #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
577 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
578 ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
579 ((SOURCE) == RCC_PLLSOURCE_HSE))
584 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
587 #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
589 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
590 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
591 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
592 ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
594 #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
596 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
597 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
598 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
599 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
604 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
607 #define RCC_HSI48_OFF ((uint8_t)0x00)
608 #define RCC_HSI48_ON ((uint8_t)0x01)
610 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
615 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
619 #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
620 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
622 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
625 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
626 ((SOURCE) == RCC_PLLSOURCE_HSE))
631 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
634 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
635 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
636 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
638 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
639 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
640 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
645 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
648 #define RCC_HSI48_OFF ((uint8_t)0x00)
650 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
655 #endif /* STM32F042x6 || STM32F048xx || */
656 /* STM32F071xB || STM32F072xB || STM32F078xx || */
657 /* STM32F091xC || STM32F098xx */
660 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
664 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
666 #define RCC_MCO_NODIV ((uint32_t)0x00000000)
668 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
670 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
672 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
673 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \
674 defined(STM32F072xB) || defined(STM32F078xx) || \
675 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
677 #define RCC_MCO_DIV1 ((uint32_t)0x00000000)
678 #define RCC_MCO_DIV2 ((uint32_t)0x10000000)
679 #define RCC_MCO_DIV4 ((uint32_t)0x20000000)
680 #define RCC_MCO_DIV8 ((uint32_t)0x30000000)
681 #define RCC_MCO_DIV16 ((uint32_t)0x40000000)
682 #define RCC_MCO_DIV32 ((uint32_t)0x50000000)
683 #define RCC_MCO_DIV64 ((uint32_t)0x60000000)
684 #define RCC_MCO_DIV128 ((uint32_t)0x70000000)
686 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
687 ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
688 ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
689 ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
691 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
692 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
693 /* STM32F091xC || STM32F098xx || STM32F030xC */
699 #if defined(STM32F042x6) || defined(STM32F048xx) || \
700 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
701 defined(STM32F091xC) || defined(STM32F098xx)
703 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
706 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
707 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
708 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
710 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
711 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
712 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
717 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
720 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
721 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
722 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
723 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
724 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
725 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
726 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
727 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
729 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
730 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
731 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
732 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
737 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
740 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
741 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
743 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
744 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
749 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
752 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
753 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
755 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
760 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
763 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
765 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
770 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
773 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
774 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
775 corresponds to a higher output frequency */
777 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
782 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
785 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
786 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
788 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
789 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
794 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
797 #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
798 #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
799 #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
800 #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
801 #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
802 #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
803 #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
809 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
812 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
813 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
814 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
815 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
816 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
817 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
818 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
824 #endif /* STM32F042x6 || STM32F048xx || */
825 /* STM32F071xB || STM32F072xB || STM32F078xx || */
826 /* STM32F091xC || STM32F098xx */
832 /* Exported macros ------------------------------------------------------------*/
833 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
837 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
838 * @brief Enables or disables the AHB1 peripheral clock.
839 * @note After reset, the peripheral clock (used for registers read/write access)
840 * is disabled and the application software has to enable this clock before
844 #if defined(STM32F030x6) || defined(STM32F030x8) || \
845 defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \
846 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
847 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
849 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
851 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
853 #endif /* STM32F030x6 || STM32F030x8 || */
854 /* STM32F051x8 || STM32F058xx || STM32F070xB || */
855 /* STM32F071xB || STM32F072xB || STM32F078xx || */
856 /* STM32F091xC || STM32F098xx || STM32F030xC */
858 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
859 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
861 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
863 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
865 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
866 /* STM32F091xC || STM32F098xx || STM32F030xC */
868 #if defined(STM32F042x6) || defined(STM32F048xx) || \
869 defined(STM32F051x8) || defined(STM32F058xx) || \
870 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
871 defined(STM32F091xC) || defined(STM32F098xx)
873 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
875 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
877 #endif /* STM32F042x6 || STM32F048xx || */
878 /* STM32F051x8 || STM32F058xx || */
879 /* STM32F071xB || STM32F072xB || STM32F078xx || */
880 /* STM32F091xC || STM32F098xx */
882 #if defined(STM32F091xC) || defined(STM32F098xx)
884 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
886 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
888 #endif /* STM32F091xC || STM32F098xx */
890 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
891 * @note After reset, the peripheral clock (used for registers read/write access)
892 * is disabled and the application software has to enable this clock before
895 #if defined(STM32F030x8) || \
896 defined(STM32F042x6) || defined(STM32F048xx) || \
897 defined(STM32F051x8) || defined(STM32F058xx) || \
898 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
899 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
901 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
902 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
904 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
905 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
907 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
908 /* STM32F051x8 || STM32F058xx || */
909 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
910 /* STM32F091xC || STM32F098xx || STM32F030xC */
912 #if defined(STM32F031x6) || defined(STM32F038xx) || \
913 defined(STM32F042x6) || defined(STM32F048xx) || \
914 defined(STM32F051x8) || defined(STM32F058xx) || \
915 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
916 defined(STM32F091xC) || defined(STM32F098xx)
918 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
920 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
922 #endif /* STM32F031x6 || STM32F038xx || */
923 /* STM32F042x6 || STM32F048xx || */
924 /* STM32F051x8 || STM32F058xx || */
925 /* STM32F071xB || STM32F072xB || STM32F078xx || */
926 /* STM32F091xC || STM32F098xx */
928 #if defined(STM32F030x8) || \
929 defined(STM32F051x8) || defined(STM32F058xx) || \
930 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
931 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
933 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
934 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
936 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
937 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
939 #endif /* STM32F030x8 || */
940 /* STM32F051x8 || STM32F058xx || */
941 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
942 /* STM32F091xC || STM32F098xx || STM32F030xC */
944 #if defined(STM32F051x8) || defined(STM32F058xx) || \
945 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
946 defined(STM32F091xC) || defined(STM32F098xx)
948 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
950 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
952 #endif /* STM32F051x8 || STM32F058xx || */
953 /* STM32F071xB || STM32F072xB || STM32F078xx || */
954 /* STM32F091xC || STM32F098xx */
956 #if defined(STM32F042x6) || defined(STM32F048xx) || \
957 defined(STM32F051x8) || defined(STM32F058xx) || \
958 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
959 defined(STM32F091xC) || defined(STM32F098xx)
961 #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
963 #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
965 #endif /* STM32F042x6 || STM32F048xx || */
966 /* STM32F051x8 || STM32F058xx || */
967 /* STM32F071xB || STM32F072xB || STM32F078xx || */
968 /* STM32F091xC || STM32F098xx */
970 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
971 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
973 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
974 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
975 #define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
977 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
978 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
979 #define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
981 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
982 /* STM32F091xC || STM32F098xx || STM32F030xC */
984 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
985 defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
987 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
989 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
991 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
992 /* STM32F072xB || STM32F078xx || STM32F070xB */
994 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
995 defined(STM32F091xC) || defined(STM32F098xx)
997 #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
998 #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
1000 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
1001 /* STM32F091xC || STM32F098xx */
1003 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1004 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1005 defined(STM32F091xC) || defined(STM32F098xx)
1007 #define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
1009 #define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
1011 #endif /* STM32F042x6 || STM32F048xx || */
1012 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1013 /* STM32F091xC || STM32F098xx */
1015 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1017 #define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
1019 #define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
1021 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
1023 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
1024 * @note After reset, the peripheral clock (used for registers read/write access)
1025 * is disabled and the application software has to enable this clock before
1028 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
1029 defined(STM32F051x8) || defined(STM32F058xx) || \
1030 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
1031 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1033 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
1035 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
1037 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
1038 /* STM32F051x8 || STM32F058xx || */
1039 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1040 /* STM32F091xC || STM32F098xx || STM32F030xC */
1042 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1044 #define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
1046 #define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
1048 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
1050 #if defined(STM32F091xC) || defined(STM32F098xx)
1052 #define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
1053 #define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
1055 #define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
1056 #define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
1058 #endif /* STM32F091xC || STM32F098xx */
1065 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
1066 * @brief Forces or releases peripheral reset.
1070 /** @brief Force or release AHB peripheral reset.
1072 #if defined(STM32F030x6) || defined(STM32F030x8) || \
1073 defined(STM32F051x8) || defined(STM32F058xx) || \
1074 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
1075 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1077 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
1079 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
1081 #endif /* STM32F030x6 || STM32F030x8 || */
1082 /* STM32F051x8 || STM32F058xx || */
1083 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1084 /* STM32F091xC || STM32F098xx || STM32F030xC */
1086 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
1087 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1089 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
1091 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
1093 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1094 /* STM32F091xC || STM32F098xx || STM32F030xC */
1096 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1097 defined(STM32F051x8) || defined(STM32F058xx) || \
1098 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1099 defined(STM32F091xC) || defined(STM32F098xx)
1101 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
1103 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
1105 #endif /* STM32F042x6 || STM32F048xx || */
1106 /* STM32F051x8 || STM32F058xx || */
1107 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1108 /* STM32F091xC || STM32F098xx */
1110 /** @brief Force or release APB1 peripheral reset.
1112 #if defined(STM32F030x8) || \
1113 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
1114 defined(STM32F051x8) || defined(STM32F058xx) || \
1115 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
1116 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1118 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
1119 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
1121 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
1122 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
1124 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
1125 /* STM32F051x8 || STM32F058xx || */
1126 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1127 /* STM32F091xC || STM32F098xx || STM32F030xC */
1129 #if defined(STM32F031x6) || defined(STM32F038xx) || \
1130 defined(STM32F042x6) || defined(STM32F048xx) || \
1131 defined(STM32F051x8) || defined(STM32F058xx) || \
1132 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1133 defined(STM32F091xC) || defined(STM32F098xx)
1135 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1137 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1139 #endif /* STM32F031x6 || STM32F038xx || */
1140 /* STM32F042x6 || STM32F048xx || */
1141 /* STM32F051x8 || STM32F058xx || */
1142 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1143 /* STM32F091xC || STM32F098xx */
1145 #if defined(STM32F030x8) || \
1146 defined(STM32F051x8) || defined(STM32F058xx) || \
1147 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\
1148 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1150 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1151 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
1153 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1154 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
1156 #endif /* STM32F030x8 || */
1157 /* STM32F051x8 || STM32F058xx || */
1158 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1159 /* STM32F091xC || STM32F098xx || STM32F030xC */
1161 #if defined(STM32F051x8) || defined(STM32F058xx) || \
1162 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1163 defined(STM32F091xC) || defined(STM32F098xx)
1165 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1167 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1169 #endif /* STM32F051x8 || STM32F058xx || */
1170 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1171 /* STM32F091xC || STM32F098xx */
1173 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1174 defined(STM32F051x8) || defined(STM32F058xx) || \
1175 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1176 defined(STM32F091xC) || defined(STM32F098xx)
1178 #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
1180 #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
1182 #endif /* STM32F042x6 || STM32F048xx || */
1183 /* STM32F051x8 || STM32F058xx || */
1184 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1185 /* STM32F091xC || STM32F098xx */
1187 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
1188 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1190 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1191 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1192 #define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
1194 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1195 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1196 #define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
1198 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1199 /* STM32F091xC || STM32F098xx || STM32F030xC */
1201 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
1202 defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
1204 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
1206 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
1208 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
1209 /* STM32F072xB || STM32F078xx || STM32F070xB */
1211 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
1212 defined(STM32F091xC) || defined(STM32F098xx)
1214 #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
1216 #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
1218 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
1219 /* STM32F091xC || STM32F098xx */
1221 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1222 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1223 defined(STM32F091xC) || defined(STM32F098xx)
1225 #define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
1227 #define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
1229 #endif /* STM32F042x6 || STM32F048xx || */
1230 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1231 /* STM32F091xC || STM32F098xx */
1233 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1235 #define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
1237 #define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
1239 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
1242 /** @brief Force or release APB2 peripheral reset.
1244 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
1245 defined(STM32F051x8) || defined(STM32F058xx) || \
1246 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
1247 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1249 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
1251 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
1253 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
1254 /* STM32F051x8 || STM32F058xx || */
1255 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1256 /* STM32F091xC || STM32F098xx || STM32F030xC */
1258 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1260 #define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
1262 #define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
1264 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
1266 #if defined(STM32F091xC) || defined(STM32F098xx)
1268 #define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
1269 #define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
1271 #define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
1272 #define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
1274 #endif /* STM32F091xC || STM32F098xx */
1280 /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
1281 * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
1282 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
1283 * @note HSI48 can not be stopped if it is used as system clock source. In this case,
1284 * you have to select another source of the system clock then stop the HSI14.
1285 * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
1286 * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
1287 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
1288 * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
1292 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1293 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1294 defined(STM32F091xC) || defined(STM32F098xx)
1296 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
1297 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
1299 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
1300 * @retval The clock source can be one of the following values:
1301 * @arg RCC_HSI48_ON: HSI48 enabled
1302 * @arg RCC_HSI48_OFF: HSI48 disabled
1304 #define __HAL_RCC_GET_HSI48_STATE() \
1305 (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
1309 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
1310 * @retval The clock source can be one of the following values:
1311 * @arg RCC_HSI_OFF: HSI48 disabled
1313 #define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
1315 #endif /* STM32F042x6 || STM32F048xx || */
1316 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1317 /* STM32F091xC || STM32F098xx */
1323 /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
1326 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1327 defined(STM32F072xB) || defined(STM32F078xx) || \
1328 defined(STM32F070x6) || defined(STM32F070xB)
1330 /** @brief Macro to configure the USB clock (USBCLK).
1331 * @param __USBCLKSource__: specifies the USB clock source.
1332 * This parameter can be one of the following values:
1333 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
1334 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
1336 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
1337 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
1339 /** @brief Macro to get the USB clock source.
1340 * @retval The clock source can be one of the following values:
1341 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
1342 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
1344 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
1346 #endif /* STM32F042x6 || STM32F048xx || */
1347 /* STM32F072xB || STM32F078xx || */
1348 /* STM32F070x6 || STM32F070xB */
1350 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1351 defined(STM32F051x8) || defined(STM32F058xx) || \
1352 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1353 defined(STM32F091xC) || defined(STM32F098xx)
1355 /** @brief Macro to configure the CEC clock.
1356 * @param __CECCLKSource__: specifies the CEC clock source.
1357 * This parameter can be one of the following values:
1358 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
1359 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
1361 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
1362 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
1364 /** @brief Macro to get the HDMI CEC clock source.
1365 * @retval The clock source can be one of the following values:
1366 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
1367 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
1369 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
1371 #endif /* STM32F042x6 || STM32F048xx || */
1372 /* STM32F051x8 || STM32F058xx || */
1373 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1374 /* STM32F091xC || defined(STM32F098xx) */
1376 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
1377 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
1378 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
1379 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
1381 /** @brief Macro to configure the MCO clock.
1382 * @param __MCOCLKSource__: specifies the MCO clock source.
1383 * This parameter can be one of the following values:
1384 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
1385 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
1386 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
1387 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
1388 * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
1389 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
1390 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
1391 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
1392 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
1393 * @param __MCODiv__: specifies the MCO clock prescaler.
1394 * This parameter can be one of the following values:
1395 * @arg RCC_MCO_DIV1: MCO clock source is divided by 1
1396 * @arg RCC_MCO_DIV2: MCO clock source is divided by 2
1397 * @arg RCC_MCO_DIV4: MCO clock source is divided by 4
1398 * @arg RCC_MCO_DIV8: MCO clock source is divided by 8
1399 * @arg RCC_MCO_DIV16: MCO clock source is divided by 16
1400 * @arg RCC_MCO_DIV32: MCO clock source is divided by 32
1401 * @arg RCC_MCO_DIV64: MCO clock source is divided by 64
1402 * @arg RCC_MCO_DIV128: MCO clock source is divided by 128
1404 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
1405 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
1408 /** @brief Macro to configure the MCO clock.
1409 * @param __MCOCLKSource__: specifies the MCO clock source.
1410 * This parameter can be one of the following values:
1411 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
1412 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
1413 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
1414 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
1415 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
1416 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
1417 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
1418 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
1419 * @param __MCODiv__: specifies the MCO clock prescaler.
1420 * This parameter can be one of the following values:
1421 * @arg RCC_MCO_NODIV: No division applied on MCO clock source
1423 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
1424 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
1426 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || */
1427 /* STM32F042x6 || STM32F048xx || */
1428 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
1429 /* STM32F091xC || STM32F098xx || STM32F030xC */
1431 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1432 defined(STM32F091xC) || defined(STM32F098xx)
1433 /** @brief Macro to configure the USART2 clock (USART2CLK).
1434 * @param __USART2CLKSource__: specifies the USART2 clock source.
1435 * This parameter can be one of the following values:
1436 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
1437 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
1438 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
1439 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
1441 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
1442 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
1444 /** @brief Macro to get the USART2 clock source.
1445 * @retval The clock source can be one of the following values:
1446 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
1447 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
1448 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
1449 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
1451 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
1452 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/
1454 #if defined(STM32F091xC) || defined(STM32F098xx)
1455 /** @brief Macro to configure the USART3 clock (USART3CLK).
1456 * @param __USART3CLKSource__: specifies the USART3 clock source.
1457 * This parameter can be one of the following values:
1458 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
1459 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
1460 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
1461 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
1463 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
1464 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
1466 /** @brief Macro to get the USART3 clock source.
1467 * @retval The clock source can be one of the following values:
1468 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
1469 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
1470 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
1471 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
1473 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
1475 #endif /* STM32F091xC || STM32F098xx */
1480 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1481 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1482 defined(STM32F091xC) || defined(STM32F098xx)
1484 /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
1487 /* Interrupt & Flag management */
1490 * @brief Enables the specified CRS interrupts.
1491 * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
1492 * This parameter can be any combination of the following values:
1493 * @arg RCC_CRS_IT_SYNCOK
1494 * @arg RCC_CRS_IT_SYNCWARN
1495 * @arg RCC_CRS_IT_ERR
1496 * @arg RCC_CRS_IT_ESYNC
1499 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
1502 * @brief Disables the specified CRS interrupts.
1503 * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
1504 * This parameter can be any combination of the following values:
1505 * @arg RCC_CRS_IT_SYNCOK
1506 * @arg RCC_CRS_IT_SYNCWARN
1507 * @arg RCC_CRS_IT_ERR
1508 * @arg RCC_CRS_IT_ESYNC
1511 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
1513 /** @brief Check the CRS's interrupt has occurred or not.
1514 * @param __INTERRUPT__: specifies the CRS interrupt source to check.
1515 * This parameter can be one of the following values:
1516 * @arg RCC_CRS_IT_SYNCOK
1517 * @arg RCC_CRS_IT_SYNCWARN
1518 * @arg RCC_CRS_IT_ERR
1519 * @arg RCC_CRS_IT_ESYNC
1520 * @retval The new state of __INTERRUPT__ (SET or RESET).
1522 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
1524 /** @brief Clear the CRS's interrupt pending bits
1525 * bits to clear the selected interrupt pending bits.
1526 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1527 * This parameter can be any combination of the following values:
1528 * @arg RCC_CRS_IT_SYNCOK
1529 * @arg RCC_CRS_IT_SYNCWARN
1530 * @arg RCC_CRS_IT_ERR
1531 * @arg RCC_CRS_IT_ESYNC
1532 * @arg RCC_CRS_IT_TRIMOVF
1533 * @arg RCC_CRS_IT_SYNCERR
1534 * @arg RCC_CRS_IT_SYNCMISS
1536 /* CRS IT Error Mask */
1537 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
1539 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
1540 (CRS->ICR |= (__INTERRUPT__)))
1543 * @brief Checks whether the specified CRS flag is set or not.
1544 * @param _FLAG_: specifies the flag to check.
1545 * This parameter can be one of the following values:
1546 * @arg RCC_CRS_FLAG_SYNCOK
1547 * @arg RCC_CRS_FLAG_SYNCWARN
1548 * @arg RCC_CRS_FLAG_ERR
1549 * @arg RCC_CRS_FLAG_ESYNC
1550 * @arg RCC_CRS_FLAG_TRIMOVF
1551 * @arg RCC_CRS_FLAG_SYNCERR
1552 * @arg RCC_CRS_FLAG_SYNCMISS
1553 * @retval The new state of _FLAG_ (TRUE or FALSE).
1555 #define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
1558 * @brief Clears the CRS specified FLAG.
1559 * @param _FLAG_: specifies the flag to clear.
1560 * This parameter can be one of the following values:
1561 * @arg RCC_CRS_FLAG_SYNCOK
1562 * @arg RCC_CRS_FLAG_SYNCWARN
1563 * @arg RCC_CRS_FLAG_ERR
1564 * @arg RCC_CRS_FLAG_ESYNC
1565 * @arg RCC_CRS_FLAG_TRIMOVF
1566 * @arg RCC_CRS_FLAG_SYNCERR
1567 * @arg RCC_CRS_FLAG_SYNCMISS
1571 /* CRS Flag Error Mask */
1572 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
1574 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
1575 (CRS->ICR |= (__FLAG__)))
1581 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
1585 * @brief Enables the oscillator clock for frequency error counter.
1586 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
1589 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
1592 * @brief Disables the oscillator clock for frequency error counter.
1595 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
1598 * @brief Enables the automatic hardware adjustement of TRIM bits.
1599 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
1602 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
1605 * @brief Enables or disables the automatic hardware adjustement of TRIM bits.
1608 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
1611 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
1612 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
1613 * of the synchronization source after prescaling. It is then decreased by one in order to
1614 * reach the expected synchronization on the zero value. The formula is the following:
1615 * RELOAD = (fTARGET / fSYNC) -1
1616 * @param _FTARGET_ Target frequency (value in Hz)
1617 * @param _FSYNC_ Synchronization signal frequency (value in Hz)
1620 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
1626 #endif /* STM32F042x6 || STM32F048xx || */
1627 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1628 /* STM32F091xC || STM32F098xx */
1634 /* Exported functions --------------------------------------------------------*/
1635 /** @addtogroup RCCEx_Exported_Functions
1639 /** @addtogroup RCCEx_Exported_Functions_Group1
1643 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1644 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1646 #if defined(STM32F042x6) || defined(STM32F048xx) || \
1647 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
1648 defined(STM32F091xC) || defined(STM32F098xx)
1649 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
1650 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
1651 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
1652 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
1653 #endif /* STM32F042x6 || STM32F048xx || */
1654 /* STM32F071xB || STM32F072xB || STM32F078xx || */
1655 /* STM32F091xC || STM32F098xx */
1678 #endif /* __STM32F0xx_HAL_RCC_EX_H */
1680 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/