2 ******************************************************************************
3 * @file stm32f0xx_hal_spi.c
4 * @author MCD Application Team
6 * @date 11-December-2014
7 * @brief SPI HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the SPI peripheral:
10 * + Initialization/de-initialization functions
11 * + I/O operation functions
12 * + Peripheral Control functions
13 * + Peripheral State functions
16 ===============================================================================
17 ##### How to use this driver #####
18 ===============================================================================
20 The SPI HAL driver can be used as follows:
22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
23 SPI_HandleTypeDef hspi;
25 (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
26 (##) Enable the SPIx interface clock
27 (##) SPI pins configuration
28 (+++) Enable the clock for the SPI GPIOs
29 (+++) Configure these SPI pins as alternate function push-pull
30 (##) NVIC configuration if you need to use interrupt process
31 (+++) Configure the SPIx interrupt priority
32 (+++) Enable the NVIC SPI IRQ handle
33 (##) DMA Configuration if you need to use DMA process
34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
35 (+++) Enable the DMAx interface clock using
36 (+++) Configure the DMA handle parameters
37 (+++) Configure the DMA Tx or Rx channel
38 (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
45 (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
46 by calling the customed HAL_SPI_MspInit(&hspi) API.
49 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
50 the following table resume the max SPI frequency reached with data size 8bits/16bits:
51 +-----------------------------------------------------------------------------------------+
52 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
53 | Process | Tranfert mode |--------------------|--------------------|--------------------|
54 | | | Master | Slave | Master | Slave | Master | Slave |
55 |=========================================================================================|
56 | T | Polling | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA |
57 | X |----------------|----------|---------|----------|---------|----------|---------|
58 | / | Interrupt | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA |
59 | R |----------------|----------|---------|----------|---------|----------|---------|
60 | X | DMA | Fcpu/32 | Fcpu/16 | NA | NA | NA | NA |
61 |=========|================|==========|=========|==========|=========|==========|=========|
62 | | Polling | Fcpu/32 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 |
63 | |----------------|----------|---------|----------|---------|----------|---------|
64 | R | Interrupt | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 |
65 | X |----------------|----------|---------|----------|---------|----------|---------|
66 | | DMA | Fcpu/4 | Fcpu/8 | Fcpu/4 | Fcpu/4 | Fcpu/8 | Fcpu/16 |
67 |=========|================|==========|=========|==========|=========|==========|=========|
68 | | Polling | Fcpu/16 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 |
69 | |----------------|----------|---------|----------|---------|----------|---------|
70 | T | Interrupt | Fcpu/32 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 |
71 | X |----------------|----------|---------|----------|---------|----------|---------|
72 | | DMA | Fcpu/2 | Fcpu/16 | NA | NA | Fcpu/8 | Fcpu/16 |
73 +-----------------------------------------------------------------------------------------+
74 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
75 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
77 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
78 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
79 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
82 ******************************************************************************
85 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
87 * Redistribution and use in source and binary forms, with or without modification,
88 * are permitted provided that the following conditions are met:
89 * 1. Redistributions of source code must retain the above copyright notice,
90 * this list of conditions and the following disclaimer.
91 * 2. Redistributions in binary form must reproduce the above copyright notice,
92 * this list of conditions and the following disclaimer in the documentation
93 * and/or other materials provided with the distribution.
94 * 3. Neither the name of STMicroelectronics nor the names of its contributors
95 * may be used to endorse or promote products derived from this software
96 * without specific prior written permission.
98 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
99 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
101 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
104 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
105 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
106 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
107 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
109 ******************************************************************************
112 /* Includes ------------------------------------------------------------------*/
113 #include "stm32f0xx_hal.h"
115 /** @addtogroup STM32F0xx_HAL_Driver
119 /** @defgroup SPI SPI HAL module driver
120 * @brief SPI HAL module driver
123 #ifdef HAL_SPI_MODULE_ENABLED
125 /* Private typedef -----------------------------------------------------------*/
126 /* Private define ------------------------------------------------------------*/
128 /** @defgroup SPI_Private_Constants SPI Private Constants
131 #define SPI_DEFAULT_TIMEOUT 50
132 #define SPI_FIFO_SIZE 4
137 /* Private macro -------------------------------------------------------------*/
138 /* Private variables ---------------------------------------------------------*/
139 /* Private function prototypes -----------------------------------------------*/
140 /** @defgroup SPI_Private_Functions SPI Private Functions
144 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
145 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
146 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
147 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
148 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
149 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
150 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
151 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
152 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
153 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
154 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
155 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
156 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
157 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
158 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
159 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
160 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
161 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
162 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
163 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
164 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
165 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
166 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
167 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
168 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
173 /* Exported functions ---------------------------------------------------------*/
175 /** @defgroup SPI_Exported_Functions SPI Exported Functions
179 /** @defgroup SPI_Exported_Functions_Group1 Initialization/de-initialization functions
180 * @brief Initialization and Configuration functions
183 ===============================================================================
184 ##### Initialization and Configuration functions #####
185 ===============================================================================
186 [..] This subsection provides a set of functions allowing to initialize and
187 de-initialiaze the SPIx peripheral:
189 (+) User must Implement HAL_SPI_MspInit() function in which he configures
190 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
192 (+) Call the function HAL_SPI_Init() to configure the selected device with
193 the selected configuration:
197 (++) Clock Polarity and Phase
199 (++) BaudRate Prescaler
203 (++) CRC Polynomial if CRC enabled
204 (++) CRC Length, used only with Data8 and Data16
205 (++) FIFO reception threshold
207 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
208 of the selected SPIx periperal.
215 * @brief Initializes the SPI according to the specified parameters
216 * in the SPI_InitTypeDef and create the associated handle.
217 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
218 * the configuration information for SPI module.
221 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
225 /* Check the SPI handle allocation */
231 /* Check the parameters */
232 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
233 assert_param(IS_SPI_MODE(hspi->Init.Mode));
234 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
235 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
236 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
237 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
238 assert_param(IS_SPI_NSS(hspi->Init.NSS));
239 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
240 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
241 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
242 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
243 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
244 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
245 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
247 hspi->State = HAL_SPI_STATE_BUSY;
249 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
250 HAL_SPI_MspInit(hspi);
252 /* Disable the selected SPI peripheral */
253 __HAL_SPI_DISABLE(hspi);
255 /* Align by default the rs fifo threshold on the data size */
256 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
258 frxth = SPI_RXFIFO_THRESHOLD_HF;
262 frxth = SPI_RXFIFO_THRESHOLD_QF;
265 /* CRC calculation is valid only for 16Bit and 8 Bit */
266 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
268 /* CRC must be disabled */
269 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
272 /* Align the CRC Length on the data size */
273 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
275 /* CRC Lengtht aligned on the data size : value set by default */
276 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
278 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
282 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
286 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
287 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
288 Communication speed, First bit, CRC calculation state, CRC Length */
289 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
290 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
291 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
293 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
295 hspi->Instance->CR1|= SPI_CR1_CRCL;
298 /* Configure : NSS management */
299 /* Configure : Rx Fifo Threshold */
300 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
301 hspi->Init.DataSize ) | frxth;
303 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
304 /* Configure : CRC Polynomial */
305 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
307 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
308 hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD);
310 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
311 hspi->State= HAL_SPI_STATE_READY;
317 * @brief DeInitializes the SPI peripheral
318 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
319 * the configuration information for SPI module.
322 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
324 /* Check the SPI handle allocation */
330 /* Check the parameters */
331 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
332 hspi->State = HAL_SPI_STATE_BUSY;
334 /* check flag before the SPI disable */
335 SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
336 SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
337 SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
339 /* Disable the SPI Peripheral Clock */
340 __HAL_SPI_DISABLE(hspi);
342 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
343 HAL_SPI_MspDeInit(hspi);
345 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
346 hspi->State = HAL_SPI_STATE_RESET;
354 * @brief SPI MSP Init
355 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
356 * the configuration information for SPI module.
359 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
361 /* NOTE : This function Should not be modified, when the callback is needed,
362 the HAL_SPI_MspInit could be implenetd in the user file
367 * @brief SPI MSP DeInit
368 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
369 * the configuration information for SPI module.
372 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
374 /* NOTE : This function Should not be modified, when the callback is needed,
375 the HAL_SPI_MspDeInit could be implenetd in the user file
383 /** @defgroup SPI_Exported_Functions_Group2 I/O operation functions
384 * @brief Data transfers functions
387 ===============================================================================
388 ##### IO operation functions #####
389 ===============================================================================
390 This subsection provides a set of functions allowing to manage the SPI
393 [..] The SPI supports master and slave mode :
395 (#) There are two modes of transfer:
396 (++) Blocking mode: The communication is performed in polling mode.
397 The HAL status of all data processing is returned by the same function
398 after finishing transfer.
399 (++) Non Blocking mode: The communication is performed using Interrupts
400 or DMA, These APIs return the HAL status.
401 The end of the data processing will be indicated through the
402 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
404 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
405 will be executed respectivelly at the end of the transmit or Receive process
406 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
408 (#) Blocking mode APIs are :
409 (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
410 (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
411 (++) HAL_SPI_TransmitReceive() in full duplex mode
413 (#) Non Blocking mode APIs with Interrupt are :
414 (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
415 (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
416 (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
417 (++) HAL_SPI_IRQHandler()
419 (#) Non Blocking mode functions with DMA are :
420 (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
421 (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
422 (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
424 (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
425 (++) HAL_SPI_TxCpltCallback()
426 (++) HAL_SPI_RxCpltCallback()
427 (++) HAL_SPI_ErrorCallback()
428 (++) HAL_SPI_TxRxCpltCallback()
435 * @brief Transmit an amount of data in blocking mode
436 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
437 * the configuration information for SPI module.
438 * @param pData : pointer to data buffer
439 * @param Size : amount of data to be sent
440 * @param Timeout : Timeout duration
443 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
445 uint32_t tickstart = HAL_GetTick();
446 HAL_StatusTypeDef errorcode = HAL_OK;
448 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
453 if(hspi->State != HAL_SPI_STATE_READY)
455 errorcode = HAL_BUSY;
459 if((pData == NULL ) || (Size == 0))
461 errorcode = HAL_ERROR;
465 /* Set the transaction information */
466 hspi->State = HAL_SPI_STATE_BUSY_TX;
467 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
468 hspi->pTxBuffPtr = pData;
469 hspi->TxXferSize = Size;
470 hspi->TxXferCount = Size;
471 hspi->pRxBuffPtr = (uint8_t*)NULL;
472 hspi->RxXferSize = 0;
473 hspi->RxXferCount = 0;
475 /* Configure communication direction : 1Line */
476 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
478 __HAL_SPI_1LINE_TX(hspi);
481 /* Reset CRC Calculation */
482 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
484 __HAL_SPI_RESET_CRC(hspi);
487 /* Check if the SPI is already enabled */
488 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
490 /* Enable SPI peripheral */
491 __HAL_SPI_ENABLE(hspi);
494 /* Transmit data in 16 Bit mode */
495 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
497 /* Transmit data in 16 Bit mode */
498 while (hspi->TxXferCount > 0)
500 /* Wait until TXE flag is set to send data */
501 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
503 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
504 hspi->pTxBuffPtr += sizeof(uint16_t);
509 /* Timeout management */
510 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
512 errorcode = HAL_TIMEOUT;
518 /* Transmit data in 8 Bit mode */
521 while (hspi->TxXferCount > 0)
523 /* Wait until TXE flag is set to send data */
524 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
526 if(hspi->TxXferCount > 1)
528 /* write on the data register in packaing mode */
529 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
530 hspi->pTxBuffPtr += sizeof(uint16_t);
531 hspi->TxXferCount -= 2;
535 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
541 /* Timeout management */
542 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
544 errorcode = HAL_TIMEOUT;
551 /* Enable CRC Transmission */
552 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
554 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
557 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
558 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
560 __HAL_SPI_CLEAR_OVRFLAG(hspi);
563 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
565 errorcode = HAL_ERROR;
569 hspi->State = HAL_SPI_STATE_READY;
570 /* Process Unlocked */
576 * @brief Receive an amount of data in blocking mode
577 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
578 * the configuration information for SPI module.
579 * @param pData : pointer to data buffer
580 * @param Size : amount of data to be sent
581 * @param Timeout : Timeout duration
584 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
586 __IO uint16_t tmpreg;
587 uint32_t tickstart = HAL_GetTick();
588 HAL_StatusTypeDef errorcode = HAL_OK;
590 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
592 /* the receive process is not supported in 2Lines direction master mode */
593 /* in this case we call the transmitReceive process */
595 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
601 if(hspi->State != HAL_SPI_STATE_READY)
603 errorcode = HAL_BUSY;
607 if((pData == NULL ) || (Size == 0))
609 errorcode = HAL_ERROR;
613 hspi->State = HAL_SPI_STATE_BUSY_RX;
614 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
615 hspi->pRxBuffPtr = pData;
616 hspi->RxXferSize = Size;
617 hspi->RxXferCount = Size;
618 hspi->pTxBuffPtr = (uint8_t*)NULL;
619 hspi->TxXferSize = 0;
620 hspi->TxXferCount = 0;
622 /* Reset CRC Calculation */
623 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
625 __HAL_SPI_RESET_CRC(hspi);
626 /* this is done to handle the CRCNEXT before the latest data */
630 /* Set the Rx Fido thresold */
631 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
633 /* set fiforxthresold according the reception data lenght: 16bit */
634 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
638 /* set fiforxthresold according the reception data lenght: 8bit */
639 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
642 /* Configure communication direction 1Line and enabled SPI if needed */
643 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
645 __HAL_SPI_1LINE_RX(hspi);
648 /* Check if the SPI is already enabled */
649 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
651 /* Enable SPI peripheral */
652 __HAL_SPI_ENABLE(hspi);
655 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
658 while(hspi->RxXferCount > 0)
660 /* Check the RXNE flag */
661 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
663 /* read the received data */
664 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
669 /* Timeout manamgement */
670 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
672 errorcode = HAL_TIMEOUT;
681 while(hspi->RxXferCount > 0)
683 /* Check the RXNE flag */
684 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
686 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
687 hspi->pRxBuffPtr += sizeof(uint16_t);
692 /* Timeout mamangement */
693 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
695 errorcode = HAL_TIMEOUT;
702 /* Handle the CRC Transmission */
703 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
705 /* freeze the CRC before the latest data */
706 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
708 /* Read the latest data */
709 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
711 errorcode = HAL_TIMEOUT;
715 /* Receive last data in 16 Bit mode */
716 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
718 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
720 /* Receive last data in 8 Bit mode */
723 *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
726 /* Wait until TXE flag */
727 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
730 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
733 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
735 tmpreg = hspi->Instance->DR;
740 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
742 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
744 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
746 /* Erreur on the CRC reception */
747 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
749 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
755 /* Check the end of the transaction */
756 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
758 errorcode = HAL_TIMEOUT;
762 /* Check if CRC error occurred */
763 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
765 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
766 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
769 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
771 errorcode = HAL_ERROR;
775 hspi->State = HAL_SPI_STATE_READY;
781 * @brief Transmit and Receive an amount of data in blocking mode
782 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
783 * the configuration information for SPI module.
784 * @param pTxData : pointer to transmission data buffer
785 * @param pRxData : pointer to reception data buffer to be
786 * @param Size : amount of data to be sent
787 * @param Timeout : Timeout duration
790 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
792 __IO uint16_t tmpreg;
793 uint32_t tickstart = HAL_GetTick();
794 HAL_StatusTypeDef errorcode = HAL_OK;
796 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
797 assert_param(pTxData != NULL);
802 if(hspi->State != HAL_SPI_STATE_READY)
804 errorcode = HAL_BUSY;
808 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
810 errorcode = HAL_ERROR;
814 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
815 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
816 hspi->pRxBuffPtr = pRxData;
817 hspi->RxXferCount = Size;
818 hspi->RxXferSize = Size;
819 hspi->pTxBuffPtr = pTxData;
820 hspi->TxXferCount = Size;
821 hspi->TxXferSize = Size;
823 /* Reset CRC Calculation */
824 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
826 __HAL_SPI_RESET_CRC(hspi);
829 /* Set the Rx Fido threshold */
830 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
832 /* set fiforxthreshold according the reception data lenght: 16bit */
833 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
837 /* set fiforxthreshold according the reception data lenght: 8bit */
838 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
841 /* Check if the SPI is already enabled */
842 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
844 /* Enable SPI peripheral */
845 __HAL_SPI_ENABLE(hspi);
848 /* Transmit and Receive data in 16 Bit mode */
849 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
851 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
854 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
856 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
857 hspi->pTxBuffPtr += sizeof(uint16_t);
860 /* Enable CRC Transmission */
861 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
863 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
867 /* Check RXNE flag */
868 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
870 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
871 hspi->pRxBuffPtr += sizeof(uint16_t);
874 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
876 errorcode = HAL_TIMEOUT;
881 /* Transmit and Receive data in 8 Bit mode */
884 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
887 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
889 if(hspi->TxXferCount > 1)
891 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
892 hspi->pTxBuffPtr += sizeof(uint16_t);
893 hspi->TxXferCount -= 2;
897 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
901 /* Enable CRC Transmission */
902 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
904 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
908 /* Wait until RXNE flag is reset */
909 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
911 if(hspi->RxXferCount > 1)
913 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
914 hspi->pRxBuffPtr += sizeof(uint16_t);
915 hspi->RxXferCount -= 2;
916 if(hspi->RxXferCount <= 1)
918 /* set fiforxthresold before to switch on 8 bit data size */
919 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
924 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
928 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
930 errorcode = HAL_TIMEOUT;
936 /* Read CRC from DR to close CRC calculation process */
937 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
939 /* Wait until TXE flag */
940 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
942 /* Erreur on the CRC reception */
943 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
946 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
948 tmpreg = hspi->Instance->DR;
953 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
955 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
957 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
959 /* Erreur on the CRC reception */
960 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
962 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
968 /* Check if CRC error occurred */
969 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
971 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
973 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
975 errorcode = HAL_ERROR;
978 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
980 errorcode = HAL_ERROR;
984 hspi->State = HAL_SPI_STATE_READY;
990 * @brief Transmit an amount of data in no-blocking mode with Interrupt
991 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
992 * the configuration information for SPI module.
993 * @param pData : pointer to data buffer
994 * @param Size : amount of data to be sent
997 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
999 HAL_StatusTypeDef errorcode = HAL_OK;
1000 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1002 /* Process Locked */
1005 if((pData == NULL) || (Size == 0))
1007 errorcode = HAL_ERROR;
1011 if(hspi->State != HAL_SPI_STATE_READY)
1013 errorcode = HAL_BUSY;
1017 /* prepore the transfer */
1018 hspi->State = HAL_SPI_STATE_BUSY_TX;
1019 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1020 hspi->pTxBuffPtr = pData;
1021 hspi->TxXferSize = Size;
1022 hspi->TxXferCount = Size;
1023 hspi->pRxBuffPtr = (uint8_t*)NULL;
1024 hspi->RxXferSize = 0;
1025 hspi->RxXferCount = 0;
1026 hspi->RxISR = (void (*)(SPI_HandleTypeDef *))NULL;
1028 /* Set the function for IT treatement */
1029 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1031 hspi->TxISR = SPI_TxISR_16BIT;
1035 hspi->TxISR = SPI_TxISR_8BIT;
1038 /* Configure communication direction : 1Line */
1039 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1041 __HAL_SPI_1LINE_TX(hspi);
1044 /* Reset CRC Calculation */
1045 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1047 __HAL_SPI_RESET_CRC(hspi);
1050 /* Enable TXE and ERR interrupt */
1051 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
1054 /* Check if the SPI is already enabled */
1055 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1057 /* Enable SPI peripheral */
1058 __HAL_SPI_ENABLE(hspi);
1067 * @brief Receive an amount of data in no-blocking mode with Interrupt
1068 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1069 * the configuration information for SPI module.
1070 * @param pData : pointer to data buffer
1071 * @param Size : amount of data to be sent
1072 * @retval HAL status
1074 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1076 HAL_StatusTypeDef errorcode = HAL_OK;
1078 /* Process Locked */
1081 if(hspi->State != HAL_SPI_STATE_READY)
1083 errorcode = HAL_BUSY;
1086 if((pData == NULL) || (Size == 0))
1088 errorcode = HAL_ERROR;
1092 /* Configure communication */
1093 hspi->State = HAL_SPI_STATE_BUSY_RX;
1094 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1095 hspi->pRxBuffPtr = pData;
1096 hspi->RxXferSize = Size;
1097 hspi->RxXferCount = Size;
1098 hspi->pTxBuffPtr = (uint8_t*)NULL;
1099 hspi->TxXferSize = 0;
1100 hspi->TxXferCount = 0;
1102 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1104 /* Process Unlocked */
1106 /* the receive process is not supported in 2Lines direction master mode */
1107 /* in this we call the transmitReceive process */
1108 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
1111 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1114 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1124 hspi->TxISR = (void (*)(SPI_HandleTypeDef *))NULL;
1125 /* check the data size to adapt Rx threshold and the set the function for IT treatement */
1126 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1128 /* set fiforxthresold according the reception data lenght: 16 bit */
1129 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1130 hspi->RxISR = SPI_RxISR_16BIT;
1134 /* set fiforxthresold according the reception data lenght: 8 bit */
1135 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1136 hspi->RxISR = SPI_RxISR_8BIT;
1139 /* Configure communication direction : 1Line */
1140 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1142 __HAL_SPI_1LINE_RX(hspi);
1145 /* Reset CRC Calculation */
1146 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1148 __HAL_SPI_RESET_CRC(hspi);
1151 /* Enable TXE and ERR interrupt */
1152 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1154 /* Check if the SPI is already enabled */
1155 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1157 /* Enable SPI peripheral */
1158 __HAL_SPI_ENABLE(hspi);
1162 /* Process Unlocked */
1168 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
1169 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1170 * the configuration information for SPI module.
1171 * @param pTxData : pointer to transmission data buffer
1172 * @param pRxData : pointer to reception data buffer to be
1173 * @param Size : amount of data to be sent
1174 * @retval HAL status
1176 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1178 HAL_StatusTypeDef errorcode = HAL_OK;
1179 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1181 /* Process locked */
1184 if(!((hspi->State == HAL_SPI_STATE_READY) || \
1185 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
1187 errorcode = HAL_BUSY;
1191 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
1193 errorcode = HAL_ERROR;
1198 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1201 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1207 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
1209 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1212 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1213 hspi->pTxBuffPtr = pTxData;
1214 hspi->TxXferSize = Size;
1215 hspi->TxXferCount = Size;
1216 hspi->pRxBuffPtr = pRxData;
1217 hspi->RxXferSize = Size;
1218 hspi->RxXferCount = Size;
1220 /* Set the function for IT treatement */
1221 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
1223 hspi->RxISR = SPI_2linesRxISR_16BIT;
1224 hspi->TxISR = SPI_2linesTxISR_16BIT;
1228 hspi->RxISR = SPI_2linesRxISR_8BIT;
1229 hspi->TxISR = SPI_2linesTxISR_8BIT;
1232 /* Reset CRC Calculation */
1233 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1235 __HAL_SPI_RESET_CRC(hspi);
1238 /* check if packing mode is enabled and if there is more than 2 data to receive */
1239 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
1241 /* set fiforxthresold according the reception data lenght: 16 bit */
1242 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1246 /* set fiforxthresold according the reception data lenght: 8 bit */
1247 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1250 /* Enable TXE, RXNE and ERR interrupt */
1251 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1253 /* Check if the SPI is already enabled */
1254 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1256 /* Enable SPI peripheral */
1257 __HAL_SPI_ENABLE(hspi);
1261 /* Process Unlocked */
1267 * @brief Transmit an amount of data in no-blocking mode with DMA
1268 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1269 * the configuration information for SPI module.
1270 * @param pData : pointer to data buffer
1271 * @param Size : amount of data to be sent
1272 * @retval HAL status
1274 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1276 HAL_StatusTypeDef errorcode = HAL_OK;
1277 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1279 /* Process Locked */
1282 if(hspi->State != HAL_SPI_STATE_READY)
1284 errorcode = HAL_BUSY;
1288 if((pData == NULL) || (Size == 0))
1290 errorcode = HAL_ERROR;
1294 hspi->State = HAL_SPI_STATE_BUSY_TX;
1295 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1296 hspi->pTxBuffPtr = pData;
1297 hspi->TxXferSize = Size;
1298 hspi->TxXferCount = Size;
1299 hspi->pRxBuffPtr = (uint8_t*)NULL;
1300 hspi->RxXferSize = 0;
1301 hspi->RxXferCount = 0;
1303 /* Configure communication direction : 1Line */
1304 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1306 __HAL_SPI_1LINE_TX(hspi);
1309 /* Reset CRC Calculation */
1310 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1312 __HAL_SPI_RESET_CRC(hspi);
1315 /* Set the SPI TxDMA Half transfer complete callback */
1316 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1318 /* Set the SPI TxDMA transfert complete callback */
1319 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1321 /* Set the DMA error callback */
1322 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1324 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1325 /* packing mode is enabled only if the DMA setting is HALWORD */
1326 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1328 /* Check the even/odd of the data size + crc if enabled */
1329 if((hspi->TxXferCount & 0x1) == 0)
1331 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1332 hspi->TxXferCount = (hspi->TxXferCount >> 1);
1336 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1337 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
1341 /* Enable the Tx DMA channel */
1342 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1344 /* Check if the SPI is already enabled */
1345 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1347 /* Enable SPI peripheral */
1348 __HAL_SPI_ENABLE(hspi);
1351 /* Enable Tx DMA Request */
1352 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1355 /* Process Unlocked */
1361 * @brief Receive an amount of data in no-blocking mode with DMA
1362 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1363 * the configuration information for SPI module.
1364 * @param pData : pointer to data buffer
1365 * @param Size : amount of data to be sent
1366 * @retval HAL status
1368 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1370 HAL_StatusTypeDef errorcode = HAL_OK;
1372 /* Process Locked */
1375 if(hspi->State != HAL_SPI_STATE_READY)
1377 errorcode = HAL_BUSY;
1381 if((pData == NULL) || (Size == 0))
1383 errorcode = HAL_ERROR;
1387 hspi->State = HAL_SPI_STATE_BUSY_RX;
1388 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1389 hspi->pRxBuffPtr = pData;
1390 hspi->RxXferSize = Size;
1391 hspi->RxXferCount = Size;
1392 hspi->pTxBuffPtr = (uint8_t*)NULL;
1393 hspi->TxXferSize = 0;
1394 hspi->TxXferCount = 0;
1396 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1398 /* Process Unlocked */
1400 /* the receive process is not supported in 2Lines direction master mode */
1401 /* in this case we call the transmitReceive process */
1402 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
1405 /* Configure communication direction : 1Line */
1406 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1408 __HAL_SPI_1LINE_RX(hspi);
1411 /* Reset CRC Calculation */
1412 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1414 __HAL_SPI_RESET_CRC(hspi);
1417 /* packing mode management is enabled by the DMA settings */
1418 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1420 /* Restriction the DMA data received is not allowed in this mode */
1421 errorcode = HAL_ERROR;
1425 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1426 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1428 /* set fiforxthresold according the reception data lenght: 16bit */
1429 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1433 /* set fiforxthresold according the reception data lenght: 8bit */
1434 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1437 /* Set the SPI RxDMA Half transfer complete callback */
1438 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1440 /* Set the SPI Rx DMA transfert complete callback */
1441 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1443 /* Set the DMA error callback */
1444 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1446 /* Enable Rx DMA Request */
1447 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1449 /* Enable the Rx DMA channel */
1450 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
1452 /* Check if the SPI is already enabled */
1453 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1455 /* Enable SPI peripheral */
1456 __HAL_SPI_ENABLE(hspi);
1460 /* Process Unlocked */
1466 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
1467 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1468 * the configuration information for SPI module.
1469 * @param pTxData : pointer to transmission data buffer
1470 * @param pRxData : pointer to reception data buffer
1471 * @param Size : amount of data to be sent
1472 * @retval HAL status
1474 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1476 HAL_StatusTypeDef errorcode = HAL_OK;
1477 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1479 /* Process locked */
1482 if(!((hspi->State == HAL_SPI_STATE_READY) ||
1483 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
1485 errorcode = HAL_BUSY;
1489 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
1491 errorcode = HAL_ERROR;
1495 /* check if the transmit Receive function is not called by a receive master */
1496 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
1498 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1501 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1502 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1503 hspi->TxXferSize = Size;
1504 hspi->TxXferCount = Size;
1505 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1506 hspi->RxXferSize = Size;
1507 hspi->RxXferCount = Size;
1509 /* Reset CRC Calculation + increase the rxsize */
1510 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1512 __HAL_SPI_RESET_CRC(hspi);
1515 /* Reset the threshold bit */
1516 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
1518 /* the packing mode management is enabled by the DMA settings according the spi data size */
1519 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1521 /* set fiforxthreshold according the reception data lenght: 16bit */
1522 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1526 /* set fiforxthresold according the reception data lenght: 8bit */
1527 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1529 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
1531 if((hspi->TxXferSize & 0x1) == 0x0)
1533 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1534 hspi->TxXferCount = hspi->TxXferCount >> 1;
1538 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1539 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
1543 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
1545 /* set fiforxthresold according the reception data lenght: 16bit */
1546 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1548 if((hspi->RxXferCount & 0x1) == 0x0 )
1550 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1551 hspi->RxXferCount = hspi->RxXferCount >> 1;
1555 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1556 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
1561 /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
1562 reception request (RXNE) */
1563 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
1565 /* Set the SPI Rx DMA Half transfer complete callback */
1566 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1567 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1571 /* Set the SPI Rx DMA Half transfer complete callback */
1572 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1573 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
1576 /* Set the DMA error callback */
1577 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1579 /* Enable Rx DMA Request */
1580 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1582 /* Enable the Rx DMA channel */
1583 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
1585 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
1586 is performed in DMA reception complete callback */
1587 hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1589 /* Set the DMA error callback */
1590 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1592 /* Enable the Tx DMA channel */
1593 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1595 /* Check if the SPI is already enabled */
1596 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1598 /* Enable SPI peripheral */
1599 __HAL_SPI_ENABLE(hspi);
1602 /* Enable Tx DMA Request */
1603 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1606 /* Process Unlocked */
1612 * @brief Pauses the DMA Transfer.
1613 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1614 * the configuration information for the specified SPI module.
1615 * @retval HAL status
1617 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
1619 /* Process Locked */
1622 /* Disable the SPI DMA Tx & Rx requests */
1623 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1625 /* Process Unlocked */
1632 * @brief Resumes the DMA Transfer.
1633 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1634 * the configuration information for the specified SPI module.
1635 * @retval HAL status
1637 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
1639 /* Process Locked */
1642 /* Enable the SPI DMA Tx & Rx requests */
1643 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1645 /* Process Unlocked */
1652 * @brief Stops the DMA Transfer.
1653 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1654 * the configuration information for the specified SPI module.
1655 * @retval HAL status
1657 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
1659 /* The Lock is not implemented on this API to allow the user application
1660 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
1661 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
1662 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
1665 /* Abort the SPI DMA tx channel */
1666 if(hspi->hdmatx != NULL)
1668 HAL_DMA_Abort(hspi->hdmatx);
1670 /* Abort the SPI DMA rx channel */
1671 if(hspi->hdmarx != NULL)
1673 HAL_DMA_Abort(hspi->hdmarx);
1676 /* Disable the SPI DMA Tx & Rx requests */
1677 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1678 hspi->State = HAL_SPI_STATE_READY;
1683 * @brief This function handles SPI interrupt request.
1684 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1685 * the configuration information for the specified SPI module.
1688 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
1690 uint32_t itsource = hspi->Instance->CR2;
1691 uint32_t itflag = hspi->Instance->SR;
1693 /* SPI in mode Receiver ----------------------------------------------------*/
1694 if(((itflag & SPI_FLAG_OVR) == RESET) &&
1695 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
1701 /* SPI in mode Tramitter ---------------------------------------------------*/
1702 if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
1708 /* SPI in Erreur Treatment ---------------------------------------------------*/
1709 if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
1711 /* SPI Overrun error interrupt occured -------------------------------------*/
1712 if((itflag & SPI_FLAG_OVR) != RESET)
1714 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
1716 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
1717 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1725 /* SPI Mode Fault error interrupt occured -------------------------------------*/
1726 if((itflag & SPI_FLAG_MODF) != RESET)
1728 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
1729 __HAL_SPI_CLEAR_MODFFLAG(hspi);
1732 /* SPI Frame error interrupt occured ----------------------------------------*/
1733 if((itflag & SPI_FLAG_FRE) != RESET)
1735 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
1736 __HAL_SPI_CLEAR_FREFLAG(hspi);
1739 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
1740 hspi->State = HAL_SPI_STATE_READY;
1741 HAL_SPI_ErrorCallback(hspi);
1747 * @brief Flush the RX fifo.
1748 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1749 * the configuration information for the specified SPI module.
1750 * @retval HAL status
1752 HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi)
1754 __IO uint32_t tmpreg;
1756 while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
1759 tmpreg = hspi->Instance->DR;
1761 if(count == SPI_FIFO_SIZE)
1770 * @brief Tx Transfer completed callbacks
1771 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1772 * the configuration information for SPI module.
1775 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
1777 /* NOTE : This function Should not be modified, when the callback is needed,
1778 the HAL_SPI_TxCpltCallback could be implenetd in the user file
1783 * @brief Rx Transfer completed callbacks
1784 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1785 * the configuration information for SPI module.
1788 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
1790 /* NOTE : This function Should not be modified, when the callback is needed,
1791 the HAL_SPI_RxCpltCallback could be implenetd in the user file
1796 * @brief Tx and Rx Transfer completed callbacks
1797 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1798 * the configuration information for SPI module.
1801 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
1803 /* NOTE : This function Should not be modified, when the callback is needed,
1804 the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
1809 * @brief Tx Half Transfer completed callbacks
1810 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1811 * the configuration information for SPI module.
1814 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1816 /* NOTE : This function Should not be modified, when the callback is needed,
1817 the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
1822 * @brief Rx Half Transfer completed callbacks
1823 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1824 * the configuration information for SPI module.
1827 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1829 /* NOTE : This function Should not be modified, when the callback is needed,
1830 the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
1835 * @brief Tx and Rx Transfer completed callbacks
1836 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1837 * the configuration information for SPI module.
1840 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1842 /* NOTE : This function Should not be modified, when the callback is needed,
1843 the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
1848 * @brief SPI error callbacks
1849 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1850 * the configuration information for SPI module.
1853 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
1855 /* NOTE : This function Should not be modified, when the callback is needed,
1856 the HAL_SPI_ErrorCallback could be implenetd in the user file
1864 /** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions
1865 * @brief SPI control functions
1868 ===============================================================================
1869 ##### Peripheral Control functions #####
1870 ===============================================================================
1872 This subsection provides a set of functions allowing to control the SPI.
1873 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
1874 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
1880 * @brief Return the SPI state
1881 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1882 * the configuration information for SPI module.
1885 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
1891 * @brief Return the SPI error code
1892 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1893 * the configuration information for SPI module.
1894 * @retval SPI Error Code
1896 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
1898 return hspi->ErrorCode;
1910 /** @addtogroup SPI_Private_Functions SPI Private Functions
1911 * @brief Data transfers Private functions
1916 * @brief DMA SPI transmit process complete callback
1917 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
1918 * the configuration information for the specified DMA module.
1921 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
1923 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1925 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
1927 /* Disable Tx DMA Request */
1928 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1930 /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
1931 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
1933 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1936 hspi->TxXferCount = 0;
1937 hspi->State = HAL_SPI_STATE_READY;
1939 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1941 HAL_SPI_ErrorCallback(hspi);
1945 HAL_SPI_TxCpltCallback(hspi);
1949 * @brief DMA SPI receive process complete callback
1950 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
1951 * the configuration information for the specified DMA module.
1954 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
1956 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1958 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
1960 __IO uint16_t tmpreg;
1963 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
1965 /* Wait until TXE flag */
1966 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
1968 /* Erreur on the CRC reception */
1969 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
1971 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1973 tmpreg = hspi->Instance->DR;
1978 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
1980 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1982 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
1984 /* Erreur on the CRC reception */
1985 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
1987 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
1993 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
1994 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
1996 /* Check the end of the transaction */
1997 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
1999 hspi->RxXferCount = 0;
2000 hspi->State = HAL_SPI_STATE_READY;
2002 /* Check if CRC error occurred */
2003 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2005 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2006 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2009 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2011 HAL_SPI_ErrorCallback(hspi);
2015 HAL_SPI_RxCpltCallback(hspi);
2019 * @brief DMA SPI transmit receive process complete callback
2020 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2021 * the configuration information for the specified DMA module.
2024 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2026 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2028 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2030 __IO int16_t tmpreg;
2032 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2034 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
2036 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
2038 /* Erreur on the CRC reception */
2039 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2041 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
2046 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
2048 /* Erreur on the CRC reception */
2049 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2051 tmpreg = hspi->Instance->DR;
2056 /* Disable Rx/Tx DMA Request */
2057 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2060 hspi->TxXferCount = 0;
2061 hspi->RxXferCount = 0;
2062 hspi->State = HAL_SPI_STATE_READY;
2064 /* Check if CRC error occurred */
2065 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2067 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
2068 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2071 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2073 HAL_SPI_ErrorCallback(hspi);
2077 HAL_SPI_TxRxCpltCallback(hspi);
2081 * @brief DMA SPI half transmit process complete callback
2082 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2083 * the configuration information for the specified DMA module.
2086 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2088 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2090 HAL_SPI_TxHalfCpltCallback(hspi);
2094 * @brief DMA SPI half receive process complete callback
2095 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2096 * the configuration information for the specified DMA module.
2099 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2101 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2103 HAL_SPI_RxHalfCpltCallback(hspi);
2107 * @brief DMA SPI Half transmit receive process complete callback
2108 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2109 * the configuration information for the specified DMA module.
2112 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2114 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2116 HAL_SPI_TxRxHalfCpltCallback(hspi);
2120 * @brief DMA SPI communication error callback
2121 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
2122 * the configuration information for the specified DMA module.
2125 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
2127 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2129 /* Stop the disable DMA transfer on SPI side */
2130 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2132 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
2133 hspi->State = HAL_SPI_STATE_READY;
2134 HAL_SPI_ErrorCallback(hspi);
2138 * @brief Rx Handler for Transmit and Receive in Interrupt mode
2139 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2140 * the configuration information for SPI module.
2143 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2145 /* Receive data in packing mode */
2146 if(hspi->RxXferCount > 1)
2148 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
2149 hspi->pRxBuffPtr += sizeof(uint16_t);
2150 hspi->RxXferCount -= 2;
2151 if(hspi->RxXferCount == 1)
2153 /* set fiforxthresold according the reception data lenght: 8bit */
2154 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2157 /* Receive data in 8 Bit mode */
2160 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
2161 hspi->RxXferCount--;
2164 /* check end of the reception */
2165 if(hspi->RxXferCount == 0)
2167 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2169 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
2173 /* Disable RXNE interrupt */
2174 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2176 if(hspi->TxXferCount == 0)
2178 SPI_CloseRxTx_ISR(hspi);
2184 * @brief Rx Handler for Transmit and Receive in Interrupt mode
2185 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2186 * the configuration information for SPI module.
2189 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
2191 __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
2195 /* check end of the reception */
2196 if(hspi->CRCSize == 0)
2198 /* Disable RXNE interrupt */
2199 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2201 if(hspi->TxXferCount == 0)
2203 SPI_CloseRxTx_ISR(hspi);
2209 * @brief Tx Handler for Transmit and Receive in Interrupt mode
2210 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2211 * the configuration information for SPI module.
2214 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2216 /* Transmit data in packing Bit mode */
2217 if(hspi->TxXferCount >= 2)
2219 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2220 hspi->pTxBuffPtr += sizeof(uint16_t);
2221 hspi->TxXferCount -= 2;
2223 /* Transmit data in 8 Bit mode */
2226 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
2227 hspi->TxXferCount--;
2230 /* check the end of the transmission */
2231 if(hspi->TxXferCount == 0)
2233 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2235 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2237 /* Disable TXE interrupt */
2238 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2240 if(hspi->RxXferCount == 0)
2242 SPI_CloseRxTx_ISR(hspi);
2248 * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
2249 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2250 * the configuration information for SPI module.
2253 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2255 /* Receive data in 16 Bit mode */
2256 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
2257 hspi->pRxBuffPtr += sizeof(uint16_t);
2258 hspi->RxXferCount--;
2260 if(hspi->RxXferCount == 0)
2262 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2264 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
2268 /* Disable RXNE interrupt */
2269 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2271 if(hspi->TxXferCount == 0)
2273 SPI_CloseRxTx_ISR(hspi);
2279 * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
2280 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2281 * the configuration information for SPI module.
2284 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
2286 /* Receive data in 16 Bit mode */
2287 __IO uint16_t tmpreg = hspi->Instance->DR;
2290 /* Disable RXNE interrupt */
2291 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
2293 SPI_CloseRxTx_ISR(hspi);
2297 * @brief Tx Handler for Transmit and Receive in Interrupt mode
2298 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2299 * the configuration information for SPI module.
2302 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2304 /* Transmit data in 16 Bit mode */
2305 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2306 hspi->pTxBuffPtr += sizeof(uint16_t);
2307 hspi->TxXferCount--;
2309 /* Enable CRC Transmission */
2310 if(hspi->TxXferCount == 0)
2312 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2314 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2316 /* Disable TXE interrupt */
2317 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
2319 if(hspi->RxXferCount == 0)
2321 SPI_CloseRxTx_ISR(hspi);
2327 * @brief Manage the CRC receive in Interrupt context
2328 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2329 * the configuration information for SPI module.
2332 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
2334 __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR);
2338 if(hspi->CRCSize == 0)
2340 SPI_CloseRx_ISR(hspi);
2345 * @brief Manage the recieve in Interrupt context
2346 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2347 * the configuration information for SPI module.
2350 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2352 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
2353 hspi->RxXferCount--;
2355 /* Enable CRC Transmission */
2356 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
2358 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2361 if(hspi->RxXferCount == 0)
2363 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2365 hspi->RxISR = SPI_RxISR_8BITCRC;
2368 SPI_CloseRx_ISR(hspi);
2373 * @brief Manage the CRC 16bit recieve in Interrupt context
2374 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2375 * the configuration information for SPI module.
2378 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
2380 __IO uint16_t tmpreg;
2382 tmpreg = hspi->Instance->DR;
2385 /* Disable RXNE and ERR interrupt */
2386 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
2388 SPI_CloseRx_ISR(hspi);
2392 * @brief Manage the 16Bit recieve in Interrupt context
2393 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2394 * the configuration information for SPI module.
2397 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2399 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
2400 hspi->pRxBuffPtr += sizeof(uint16_t);
2401 hspi->RxXferCount--;
2403 /* Enable CRC Transmission */
2404 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
2406 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2409 if(hspi->RxXferCount == 0)
2411 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2413 hspi->RxISR = SPI_RxISR_16BITCRC;
2416 SPI_CloseRx_ISR(hspi);
2421 * @brief Handle the data 8Bit transmit in Interrupt mode
2422 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2423 * the configuration information for SPI module.
2426 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
2428 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
2429 hspi->TxXferCount--;
2431 if(hspi->TxXferCount == 0)
2433 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2435 /* Enable CRC Transmission */
2436 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2438 SPI_CloseTx_ISR(hspi);
2443 * @brief Handle the data 16Bit transmit in Interrupt mode
2444 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2445 * the configuration information for SPI module.
2448 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
2450 /* Transmit data in 16 Bit mode */
2451 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
2452 hspi->pTxBuffPtr += sizeof(uint16_t);
2453 hspi->TxXferCount--;
2455 if(hspi->TxXferCount == 0)
2457 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2459 /* Enable CRC Transmission */
2460 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
2462 SPI_CloseTx_ISR(hspi);
2467 * @brief This function handles SPI Communication Timeout.
2468 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2469 * the configuration information for SPI module.
2470 * @param Flag : SPI flag to check
2471 * @param State : flag state to check
2472 * @param Timeout : Timeout duration
2473 * @retval HAL status
2475 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
2477 uint32_t tickstart = HAL_GetTick();
2479 while((hspi->Instance->SR & Flag) != State)
2481 if(Timeout != HAL_MAX_DELAY)
2483 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
2485 /* Disable the SPI and reset the CRC: the CRC value should be cleared
2486 on both master and slave sides in order to resynchronize the master
2487 and slave for their respective CRC calculation */
2489 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
2490 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
2492 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2494 /* Disable SPI peripheral */
2495 __HAL_SPI_DISABLE(hspi);
2498 /* Reset CRC Calculation */
2499 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2501 __HAL_SPI_RESET_CRC(hspi);
2504 hspi->State= HAL_SPI_STATE_READY;
2506 /* Process Unlocked */
2518 * @brief This function handles SPI Communication Timeout.
2519 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2520 * the configuration information for SPI module.
2521 * @param Fifo : Fifo to check
2522 * @param State : Fifo state to check
2523 * @param Timeout : Timeout duration
2524 * @retval HAL status
2526 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
2528 __IO uint8_t tmpreg;
2529 uint32_t tickstart = HAL_GetTick();
2531 while((hspi->Instance->SR & Fifo) != State)
2533 if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
2535 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
2539 if(Timeout != HAL_MAX_DELAY)
2541 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
2543 /* Disable the SPI and reset the CRC: the CRC value should be cleared
2544 on both master and slave sides in order to resynchronize the master
2545 and slave for their respective CRC calculation */
2547 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
2548 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
2550 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2552 /* Disable SPI peripheral */
2553 __HAL_SPI_DISABLE(hspi);
2556 /* Reset CRC Calculation */
2557 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
2559 __HAL_SPI_RESET_CRC(hspi);
2562 hspi->State = HAL_SPI_STATE_READY;
2564 /* Process Unlocked */
2576 * @brief This function handles the check of the RX transaction complete.
2577 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2578 * the configuration information for SPI module.
2579 * @param Timeout : Timeout duration
2582 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
2584 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2586 /* Disable SPI peripheral */
2587 __HAL_SPI_DISABLE(hspi);
2589 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
2591 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
2594 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
2596 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
2604 * @brief This function handles the close of the RXTX transaction.
2605 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2606 * the configuration information for SPI module.
2609 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
2611 /* Disable ERR interrupt */
2612 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2614 /* Check if CRC error occurred */
2615 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2617 hspi->State = HAL_SPI_STATE_READY;
2618 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2619 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2620 HAL_SPI_ErrorCallback(hspi);
2624 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
2626 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
2628 hspi->State = HAL_SPI_STATE_READY;
2629 HAL_SPI_RxCpltCallback(hspi);
2633 hspi->State = HAL_SPI_STATE_READY;
2634 HAL_SPI_TxRxCpltCallback(hspi);
2639 hspi->State = HAL_SPI_STATE_READY;
2640 HAL_SPI_ErrorCallback(hspi);
2646 * @brief This function handles the close of the RX transaction.
2647 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2648 * the configuration information for SPI module.
2651 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
2653 /* Disable RXNE and ERR interrupt */
2654 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
2656 /* Check the end of the transaction */
2657 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
2659 hspi->State = HAL_SPI_STATE_READY;
2661 /* Check if CRC error occurred */
2662 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2664 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
2665 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2666 HAL_SPI_ErrorCallback(hspi);
2670 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
2672 HAL_SPI_RxCpltCallback(hspi);
2676 HAL_SPI_ErrorCallback(hspi);
2682 * @brief This function handles the close of the TX transaction.
2683 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2684 * the configuration information for SPI module.
2687 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
2689 /* Disable TXE and ERR interrupt */
2690 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
2692 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
2693 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
2695 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2698 hspi->State = HAL_SPI_STATE_READY;
2699 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2701 HAL_SPI_ErrorCallback(hspi);
2705 HAL_SPI_TxCpltCallback(hspi);
2713 #endif /* HAL_SPI_MODULE_ENABLED */
2722 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/