2 ******************************************************************************
3 * @file stm32f0xx_hal_spi.h
4 * @author MCD Application Team
6 * @date 11-December-2014
7 * @brief Header file of SPI HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
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18 * this list of conditions and the following disclaimer in the documentation
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F0xx_HAL_SPI_H
40 #define __STM32F0xx_HAL_SPI_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f0xx_hal_def.h"
49 /** @addtogroup STM32F0xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup SPI_Exported_Types SPI Exported Types
63 * @brief SPI Configuration Structure definition
67 uint32_t Mode; /*!< Specifies the SPI operating mode.
68 This parameter can be a value of @ref SPI_mode */
70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
71 This parameter can be a value of @ref SPI_Direction */
73 uint32_t DataSize; /*!< Specifies the SPI data size.
74 This parameter can be a value of @ref SPI_data_size */
76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
77 This parameter can be a value of @ref SPI_Clock_Polarity */
79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
80 This parameter can be a value of @ref SPI_Clock_Phase */
82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
83 hardware (NSS pin) or by software using the SSI bit.
84 This parameter can be a value of @ref SPI_Slave_Select_management */
86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
87 used to configure the transmit and receive SCK clock.
88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
89 @note The communication clock is derived from the master
90 clock. The slave clock does not need to be set. */
92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
96 This parameter can be a value of @ref SPI_TI_mode */
98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
99 This parameter can be a value of @ref SPI_CRC_Calculation */
101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
104 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
105 CRC Length is only used with Data8 and Data16, not other data size
106 This parameter must 0 or 1 or 2*/
108 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
109 This parameter can be a value of @ref SPI_NSSP_Mode
110 This mode is activated by the NSSP bit in the SPIx_CR2 register and
111 it takes effect only if the SPI interface is configured as Motorola SPI
112 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
113 CPOL setting is ignored).. */
117 * @brief HAL State structures definition
121 HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
122 HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
123 HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
124 HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
125 HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
126 HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
127 HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
128 }HAL_SPI_StateTypeDef;
131 * @brief SPI handle Structure definition
133 typedef struct __SPI_HandleTypeDef
135 SPI_TypeDef *Instance; /*!< SPI registers base address */
137 SPI_InitTypeDef Init; /*!< SPI communication parameters */
139 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
141 uint16_t TxXferSize; /*!< SPI Tx Transfer size */
143 uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
145 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
147 uint16_t RxXferSize; /*!< SPI Rx Transfer size */
149 uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
151 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
153 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
155 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
157 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
159 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
161 HAL_LockTypeDef Lock; /*!< Locking object */
163 HAL_SPI_StateTypeDef State; /*!< SPI communication state */
165 __IO uint32_t ErrorCode; /*!< SPI Error code
166 This parameter can be a value of @ref SPI_Error */
174 /* Exported constants --------------------------------------------------------*/
176 /** @defgroup SPI_Exported_Constants SPI Exported Constants
180 /** @defgroup SPI_Error SPI Error
183 #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
184 #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
185 #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
186 #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
187 #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
188 #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
189 #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
190 #define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040) /*!< Unknow Error error */
195 /** @defgroup SPI_mode SPI mode
198 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
199 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
200 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
201 ((MODE) == SPI_MODE_MASTER))
206 /** @defgroup SPI_Direction SPI Direction
209 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
210 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
211 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
213 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
214 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
215 ((MODE) == SPI_DIRECTION_1LINE))
217 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
219 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
220 ((MODE) == SPI_DIRECTION_1LINE))
225 /** @defgroup SPI_data_size SPI Data size
228 #define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */
229 #define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */
230 #define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */
231 #define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */
232 #define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */
233 #define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */
234 #define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */
235 #define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */
236 #define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */
237 #define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */
238 #define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */
239 #define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */
240 #define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */
241 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
242 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
243 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
244 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
245 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
246 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
247 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
248 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
249 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
250 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
251 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
252 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
253 ((DATASIZE) == SPI_DATASIZE_4BIT))
259 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
262 #define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */
263 #define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */
264 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
265 ((CPOL) == SPI_POLARITY_HIGH))
270 /** @defgroup SPI_Clock_Phase SPI Clock Phase
273 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SPI Phase 1EDGE */
274 #define SPI_PHASE_2EDGE SPI_CR1_CPHA /*!< SPI Phase 2EDGE */
275 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
276 ((CPHA) == SPI_PHASE_2EDGE))
281 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
284 #define SPI_NSS_SOFT SPI_CR1_SSM
285 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
286 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
287 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
288 ((NSS) == SPI_NSS_HARD_INPUT) || \
289 ((NSS) == SPI_NSS_HARD_OUTPUT))
294 /** @defgroup SPI_NSSP_Mode SPI NSS pulse management
297 #define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
298 #define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000)
300 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \
301 ((NSSP) == SPI_NSS_PULSE_DISABLED))
306 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
309 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
310 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
311 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
312 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
313 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
314 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
315 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
316 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
317 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
318 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
319 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
320 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
321 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
322 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
323 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
324 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
329 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
332 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
333 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
334 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
335 ((BIT) == SPI_FIRSTBIT_LSB))
340 /** @defgroup SPI_TI_mode SPI TI mode
343 #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
344 #define SPI_TIMODE_ENABLED SPI_CR2_FRF
345 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
346 ((MODE) == SPI_TIMODE_ENABLED))
351 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
354 #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
355 #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
356 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
357 ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
362 /** @defgroup SPI_CRC_length SPI CRC length
364 * This parameter can be one of the following values:
365 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
366 * SPI_CRC_LENGTH_8BIT : CRC 8bit
367 * SPI_CRC_LENGTH_16BIT : CRC 16bit
369 #define SPI_CRC_LENGTH_DATASIZE 0
370 #define SPI_CRC_LENGTH_8BIT 1
371 #define SPI_CRC_LENGTH_16BIT 2
372 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
373 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
374 ((LENGTH) == SPI_CRC_LENGTH_16BIT))
379 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold
381 * This parameter can be one of the following values:
382 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
383 * RXNE event is generated if the FIFO
384 * level is greater or equal to 1/2(16-bits).
385 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
386 * level is greater or equal to 1/4(8 bits). */
387 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
388 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
389 #define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
395 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
396 * @brief SPI Interrupt definition
397 * Elements values convention: 0xXXXXXXXX
398 * - XXXXXXXX : Interrupt control mask
401 #define SPI_IT_TXE SPI_CR2_TXEIE
402 #define SPI_IT_RXNE SPI_CR2_RXNEIE
403 #define SPI_IT_ERR SPI_CR2_ERRIE
409 /** @defgroup SPI_Flag_definition SPI Flag definition
410 * @brief Flag definition
411 * Elements values convention: 0xXXXXYYYY
412 * - XXXX : Flag register Index
416 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
417 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
418 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
419 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
420 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
421 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
422 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
423 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
424 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
429 /** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level
432 #define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
433 #define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
434 #define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
435 #define SPI_FTLVL_FULL ((uint32_t)0x1800)
441 /** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level
444 #define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
445 #define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
446 #define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
447 #define SPI_FRLVL_FULL ((uint32_t)0x0600)
457 /* Exported macros ------------------------------------------------------------*/
458 /** @defgroup SPI_Exported_Macros SPI Exported Macros
462 /** @brief Reset SPI handle state
463 * @param __HANDLE__: SPI handle.
466 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
468 /** @brief Enables or disables the specified SPI interrupts.
469 * @param __HANDLE__ : specifies the SPI Handle.
470 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
471 * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.
472 * This parameter can be one of the following values:
473 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
474 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
475 * @arg SPI_IT_ERR: Error interrupt enable
478 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
479 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
481 /** @brief Checks if the specified SPI interrupt source is enabled or disabled.
482 * @param __HANDLE__ : specifies the SPI Handle.
483 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
484 * @param __INTERRUPT__ : specifies the SPI interrupt source to check.
485 * This parameter can be one of the following values:
486 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
487 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
488 * @arg SPI_IT_ERR: Error interrupt enable
489 * @retval The new state of __IT__ (TRUE or FALSE).
491 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
493 /** @brief Checks whether the specified SPI flag is set or not.
494 * @param __HANDLE__ : specifies the SPI Handle.
495 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
496 * @param __FLAG__ : specifies the flag to check.
497 * This parameter can be one of the following values:
498 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
499 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
500 * @arg SPI_FLAG_CRCERR: CRC error flag
501 * @arg SPI_FLAG_MODF: Mode fault flag
502 * @arg SPI_FLAG_OVR: Overrun flag
503 * @arg SPI_FLAG_BSY: Busy flag
504 * @arg SPI_FLAG_FRE: Frame format error flag
505 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
506 * @arg SPI_FLAG_FRLVL: SPI fifo reception level
507 * @retval The new state of __FLAG__ (TRUE or FALSE).
509 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
511 /** @brief Clears the SPI CRCERR pending flag.
512 * @param __HANDLE__ : specifies the SPI Handle.
513 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
516 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
518 /** @brief Clears the SPI MODF pending flag.
519 * @param __HANDLE__ : specifies the SPI Handle.
520 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
524 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{\
525 __IO uint32_t tmpreg;\
526 tmpreg = (__HANDLE__)->Instance->SR;\
528 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);\
531 /** @brief Clears the SPI OVR pending flag.
532 * @param __HANDLE__ : specifies the SPI Handle.
533 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
537 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ \
538 __IO uint32_t tmpreg; \
539 tmpreg = (__HANDLE__)->Instance->DR; \
540 tmpreg = (__HANDLE__)->Instance->SR; \
544 /** @brief Clears the SPI FRE pending flag.
545 * @param __HANDLE__ : specifies the SPI Handle.
546 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
550 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{\
551 __IO uint32_t tmpreg;\
552 tmpreg = ((__HANDLE__)->Instance->SR);\
555 /** @brief Enables the SPI.
556 * @param __HANDLE__ : specifies the SPI Handle.
557 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
560 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
562 /** @brief Disables the SPI.
563 * @param __HANDLE__ : specifies the SPI Handle.
564 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
567 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
569 /** @brief Sets the SPI transmit-only mode.
570 * @param __HANDLE__ : specifies the SPI Handle.
571 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
574 #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
576 /** @brief Sets the SPI receive-only mode.
577 * @param __HANDLE__ : specifies the SPI Handle.
578 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
581 #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
583 /** @brief Resets the CRC calculation of the SPI.
584 * @param __HANDLE__ : specifies the SPI Handle.
585 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
588 #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
589 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
592 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
597 /* Exported functions --------------------------------------------------------*/
598 /** @addtogroup SPI_Exported_Functions
602 /** @addtogroup SPI_Exported_Functions_Group1
606 /* Initialization and de-initialization functions ****************************/
607 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
608 HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi);
609 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
610 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
611 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
616 /** @addtogroup SPI_Exported_Functions_Group2
620 /* IO operation functions *****************************************************/
621 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
622 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
623 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
624 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
625 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
626 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
627 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
628 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
629 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
630 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
631 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
632 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
633 HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi);
635 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
636 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
637 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
638 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
639 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
640 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
641 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
642 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
647 /** @addtogroup SPI_Exported_Functions_Group3
651 /* Peripheral State and Error functions ***************************************/
652 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
653 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
674 #endif /* __STM32F0xx_HAL_SPI_H */
676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/