2 ******************************************************************************
3 * @file stm32f0xx_hal_tim.c
4 * @author MCD Application Team
6 * @date 11-December-2014
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Time Base Initialization
12 * + Time Base Start Interruption
13 * + Time Base Start DMA
14 * + Time Output Compare/PWM Initialization
15 * + Time Output Compare/PWM Channel Configuration
16 * + Time Output Compare/PWM Start
17 * + Time Output Compare/PWM Start Interruption
18 * + Time Output Compare/PWM Start DMA
19 * + Time Input Capture Initialization
20 * + Time Input Capture Channel Configuration
21 * + Time Input Capture Start
22 * + Time Input Capture Start Interruption
23 * + Time Input Capture Start DMA
24 * + Time One Pulse Initialization
25 * + Time One Pulse Channel Configuration
26 * + Time One Pulse Start
27 * + Time Encoder Interface Initialization
28 * + Time Encoder Interface Start
29 * + Time Encoder Interface Start Interruption
30 * + Time Encoder Interface Start DMA
31 * + Commutation Event configuration with Interruption and DMA
32 * + Time OCRef clear configuration
33 * + Time External Clock configuration
35 ==============================================================================
36 ##### TIMER Generic features #####
37 ==============================================================================
38 [..] The Timer features include:
39 (#) 16-bit up, down, up/down auto-reload counter.
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
41 counter clock frequency either by any factor between 1 and 65536.
42 (#) Up to 4 independent channels for:
45 (++) PWM generation (Edge and Center-aligned Mode)
46 (++) One-pulse mode output
48 ##### How to use this driver #####
49 ==============================================================================
51 (#) Initialize the TIM low level resources by implementing the following functions
52 depending from feature used :
53 (++) Time Base : HAL_TIM_Base_MspInit()
54 (++) Input Capture : HAL_TIM_IC_MspInit()
55 (++) Output Compare : HAL_TIM_OC_MspInit()
56 (++) PWM generation : HAL_TIM_PWM_MspInit()
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60 (#) Initialize the TIM low level resources :
61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
62 (##) TIM pins configuration
63 (+++) Enable the clock for the TIM GPIOs using the following function:
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67 (#) The external Clock can be configured, if needed (the default clock is the
68 internal clock from the APBx), using the following function:
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
72 (#) Configure the TIM in the desired functioning mode using one of the
73 Initialization function of this driver:
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
76 Output Compare signal.
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93 (#) The DMA Burst is managed with the two following functions:
94 HAL_TIM_DMABurst_WriteStart()
95 HAL_TIM_DMABurst_ReadStart()
98 ******************************************************************************
101 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
125 ******************************************************************************
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f0xx_hal.h"
131 /** @addtogroup STM32F0xx_HAL_Driver
135 /** @defgroup TIM TIM HAL module driver
136 * @brief TIM HAL module driver
140 #ifdef HAL_TIM_MODULE_ENABLED
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /* Private macro -------------------------------------------------------------*/
145 /* Private variables ---------------------------------------------------------*/
146 /* Private function prototypes -----------------------------------------------*/
148 /** @defgroup TIM_Private_Functions TIM_Private_Functions
151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
152 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
153 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
156 uint32_t TIM_ICFilter);
157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
159 uint32_t TIM_ICFilter);
160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
161 uint32_t TIM_ICFilter);
162 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
163 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
164 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
165 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
166 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
167 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
168 TIM_SlaveConfigTypeDef * sSlaveConfig);
174 /* Exported functions ---------------------------------------------------------*/
176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
181 * @brief Time Base functions
184 ==============================================================================
185 ##### Time Base functions #####
186 ==============================================================================
188 This section provides functions allowing to:
189 (+) Initialize and configure the TIM base.
190 (+) De-initialize the TIM base.
191 (+) Start the Time Base.
192 (+) Stop the Time Base.
193 (+) Start the Time Base and enable interrupt.
194 (+) Stop the Time Base and disable interrupt.
195 (+) Start the Time Base and enable DMA transfer.
196 (+) Stop the Time Base and disable DMA transfer.
202 * @brief Initializes the TIM Time base Unit according to the specified
203 * parameters in the TIM_HandleTypeDef and create the associated handle.
204 * @param htim : TIM Base handle
207 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
209 /* Check the TIM handle allocation */
215 /* Check the parameters */
216 assert_param(IS_TIM_INSTANCE(htim->Instance));
217 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
218 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
220 if(htim->State == HAL_TIM_STATE_RESET)
222 /* Init the low level hardware : GPIO, CLOCK, NVIC */
223 HAL_TIM_Base_MspInit(htim);
226 /* Set the TIM state */
227 htim->State= HAL_TIM_STATE_BUSY;
229 /* Set the Time Base configuration */
230 TIM_Base_SetConfig(htim->Instance, &htim->Init);
232 /* Initialize the TIM state*/
233 htim->State= HAL_TIM_STATE_READY;
239 * @brief DeInitializes the TIM Base peripheral
240 * @param htim : TIM Base handle
243 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
245 /* Check the parameters */
246 assert_param(IS_TIM_INSTANCE(htim->Instance));
248 htim->State = HAL_TIM_STATE_BUSY;
250 /* Disable the TIM Peripheral Clock */
251 __HAL_TIM_DISABLE(htim);
253 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
254 HAL_TIM_Base_MspDeInit(htim);
256 /* Change TIM state */
257 htim->State = HAL_TIM_STATE_RESET;
266 * @brief Initializes the TIM Base MSP.
267 * @param htim : TIM handle
270 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
272 /* NOTE : This function Should not be modified, when the callback is needed,
273 the HAL_TIM_Base_MspInit could be implemented in the user file
278 * @brief DeInitializes TIM Base MSP.
279 * @param htim : TIM handle
282 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
284 /* NOTE : This function Should not be modified, when the callback is needed,
285 the HAL_TIM_Base_MspDeInit could be implemented in the user file
291 * @brief Starts the TIM Base generation.
292 * @param htim : TIM handle
295 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
297 /* Check the parameters */
298 assert_param(IS_TIM_INSTANCE(htim->Instance));
300 /* Set the TIM state */
301 htim->State= HAL_TIM_STATE_BUSY;
303 /* Enable the Peripheral */
304 __HAL_TIM_ENABLE(htim);
306 /* Change the TIM state*/
307 htim->State= HAL_TIM_STATE_READY;
309 /* Return function status */
314 * @brief Stops the TIM Base generation.
315 * @param htim : TIM handle
318 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
320 /* Check the parameters */
321 assert_param(IS_TIM_INSTANCE(htim->Instance));
323 /* Set the TIM state */
324 htim->State= HAL_TIM_STATE_BUSY;
326 /* Disable the Peripheral */
327 __HAL_TIM_DISABLE(htim);
329 /* Change the TIM state*/
330 htim->State= HAL_TIM_STATE_READY;
332 /* Return function status */
337 * @brief Starts the TIM Base generation in interrupt mode.
338 * @param htim : TIM handle
341 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
343 /* Check the parameters */
344 assert_param(IS_TIM_INSTANCE(htim->Instance));
346 /* Enable the TIM Update interrupt */
347 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
349 /* Enable the Peripheral */
350 __HAL_TIM_ENABLE(htim);
352 /* Return function status */
357 * @brief Stops the TIM Base generation in interrupt mode.
358 * @param htim : TIM handle
361 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
363 /* Check the parameters */
364 assert_param(IS_TIM_INSTANCE(htim->Instance));
365 /* Disable the TIM Update interrupt */
366 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
368 /* Disable the Peripheral */
369 __HAL_TIM_DISABLE(htim);
371 /* Return function status */
376 * @brief Starts the TIM Base generation in DMA mode.
377 * @param htim : TIM handle
378 * @param pData : The source Buffer address.
379 * @param Length : The length of data to be transferred from memory to peripheral.
382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
384 /* Check the parameters */
385 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
387 if((htim->State == HAL_TIM_STATE_BUSY))
391 else if((htim->State == HAL_TIM_STATE_READY))
393 if((pData == 0 ) && (Length > 0))
399 htim->State = HAL_TIM_STATE_BUSY;
402 /* Set the DMA Period elapsed callback */
403 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
405 /* Set the DMA error callback */
406 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
408 /* Enable the DMA channel */
409 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
411 /* Enable the TIM Update DMA request */
412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
414 /* Enable the Peripheral */
415 __HAL_TIM_ENABLE(htim);
417 /* Return function status */
422 * @brief Stops the TIM Base generation in DMA mode.
423 * @param htim : TIM handle
426 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
428 /* Check the parameters */
429 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
431 /* Disable the TIM Update DMA request */
432 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
434 /* Disable the Peripheral */
435 __HAL_TIM_DISABLE(htim);
437 /* Change the htim state */
438 htim->State = HAL_TIM_STATE_READY;
440 /* Return function status */
448 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
449 * @brief Time Output Compare functions
452 ==============================================================================
453 ##### Time Output Compare functions #####
454 ==============================================================================
456 This section provides functions allowing to:
457 (+) Initialize and configure the TIM Output Compare.
458 (+) De-initialize the TIM Output Compare.
459 (+) Start the Time Output Compare.
460 (+) Stop the Time Output Compare.
461 (+) Start the Time Output Compare and enable interrupt.
462 (+) Stop the Time Output Compare and disable interrupt.
463 (+) Start the Time Output Compare and enable DMA transfer.
464 (+) Stop the Time Output Compare and disable DMA transfer.
470 * @brief Initializes the TIM Output Compare according to the specified
471 * parameters in the TIM_HandleTypeDef and create the associated handle.
472 * @param htim : TIM Output Compare handle
475 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
477 /* Check the TIM handle allocation */
483 /* Check the parameters */
484 assert_param(IS_TIM_INSTANCE(htim->Instance));
485 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
486 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
488 if(htim->State == HAL_TIM_STATE_RESET)
490 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
491 HAL_TIM_OC_MspInit(htim);
494 /* Set the TIM state */
495 htim->State= HAL_TIM_STATE_BUSY;
497 /* Init the base time for the Output Compare */
498 TIM_Base_SetConfig(htim->Instance, &htim->Init);
500 /* Initialize the TIM state*/
501 htim->State= HAL_TIM_STATE_READY;
507 * @brief DeInitializes the TIM peripheral
508 * @param htim : TIM Output Compare handle
511 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
513 /* Check the parameters */
514 assert_param(IS_TIM_INSTANCE(htim->Instance));
516 htim->State = HAL_TIM_STATE_BUSY;
518 /* Disable the TIM Peripheral Clock */
519 __HAL_TIM_DISABLE(htim);
521 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
522 HAL_TIM_OC_MspDeInit(htim);
524 /* Change TIM state */
525 htim->State = HAL_TIM_STATE_RESET;
534 * @brief Initializes the TIM Output Compare MSP.
535 * @param htim : TIM handle
538 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
540 /* NOTE : This function Should not be modified, when the callback is needed,
541 the HAL_TIM_OC_MspInit could be implemented in the user file
546 * @brief DeInitializes TIM Output Compare MSP.
547 * @param htim : TIM handle
550 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
552 /* NOTE : This function Should not be modified, when the callback is needed,
553 the HAL_TIM_OC_MspDeInit could be implemented in the user file
558 * @brief Starts the TIM Output Compare signal generation.
559 * @param htim : TIM Output Compare handle
560 * @param Channel : TIM Channel to be enabled
561 * This parameter can be one of the following values:
562 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
563 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
564 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
565 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
568 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
570 /* Check the parameters */
571 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
573 /* Enable the Output compare channel */
574 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
576 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
578 /* Enable the main output */
579 __HAL_TIM_MOE_ENABLE(htim);
582 /* Enable the Peripheral */
583 __HAL_TIM_ENABLE(htim);
585 /* Return function status */
590 * @brief Stops the TIM Output Compare signal generation.
591 * @param htim : TIM handle
592 * @param Channel : TIM Channel to be disabled
593 * This parameter can be one of the following values:
594 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
595 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
596 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
597 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
600 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
602 /* Check the parameters */
603 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
605 /* Disable the Output compare channel */
606 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
608 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
610 /* Disable the Main Ouput */
611 __HAL_TIM_MOE_DISABLE(htim);
614 /* Disable the Peripheral */
615 __HAL_TIM_DISABLE(htim);
617 /* Return function status */
622 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
623 * @param htim : TIM OC handle
624 * @param Channel : TIM Channel to be enabled
625 * This parameter can be one of the following values:
626 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
627 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
628 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
629 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
632 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
634 /* Check the parameters */
635 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
641 /* Enable the TIM Capture/Compare 1 interrupt */
642 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
648 /* Enable the TIM Capture/Compare 2 interrupt */
649 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
655 /* Enable the TIM Capture/Compare 3 interrupt */
656 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
662 /* Enable the TIM Capture/Compare 4 interrupt */
663 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
671 /* Enable the Output compare channel */
672 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
674 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
676 /* Enable the main output */
677 __HAL_TIM_MOE_ENABLE(htim);
680 /* Enable the Peripheral */
681 __HAL_TIM_ENABLE(htim);
683 /* Return function status */
688 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
689 * @param htim : TIM Output Compare handle
690 * @param Channel : TIM Channel to be disabled
691 * This parameter can be one of the following values:
692 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
693 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
694 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
695 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
698 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
700 /* Check the parameters */
701 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
707 /* Disable the TIM Capture/Compare 1 interrupt */
708 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
714 /* Disable the TIM Capture/Compare 2 interrupt */
715 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
721 /* Disable the TIM Capture/Compare 3 interrupt */
722 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
728 /* Disable the TIM Capture/Compare 4 interrupt */
729 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
737 /* Disable the Output compare channel */
738 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
740 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
742 /* Disable the Main Ouput */
743 __HAL_TIM_MOE_DISABLE(htim);
746 /* Disable the Peripheral */
747 __HAL_TIM_DISABLE(htim);
749 /* Return function status */
754 * @brief Starts the TIM Output Compare signal generation in DMA mode.
755 * @param htim : TIM Output Compare handle
756 * @param Channel : TIM Channel to be enabled
757 * This parameter can be one of the following values:
758 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
759 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
760 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
761 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
762 * @param pData : The source Buffer address.
763 * @param Length : The length of data to be transferred from memory to TIM peripheral
766 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
768 /* Check the parameters */
769 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
771 if((htim->State == HAL_TIM_STATE_BUSY))
775 else if((htim->State == HAL_TIM_STATE_READY))
777 if(((uint32_t)pData == 0 ) && (Length > 0))
783 htim->State = HAL_TIM_STATE_BUSY;
790 /* Set the DMA Period elapsed callback */
791 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
793 /* Set the DMA error callback */
794 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
796 /* Enable the DMA channel */
797 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
799 /* Enable the TIM Capture/Compare 1 DMA request */
800 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
806 /* Set the DMA Period elapsed callback */
807 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
809 /* Set the DMA error callback */
810 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
812 /* Enable the DMA channel */
813 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
815 /* Enable the TIM Capture/Compare 2 DMA request */
816 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
822 /* Set the DMA Period elapsed callback */
823 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
825 /* Set the DMA error callback */
826 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
828 /* Enable the DMA channel */
829 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
831 /* Enable the TIM Capture/Compare 3 DMA request */
832 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
838 /* Set the DMA Period elapsed callback */
839 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
841 /* Set the DMA error callback */
842 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
844 /* Enable the DMA channel */
845 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
847 /* Enable the TIM Capture/Compare 4 DMA request */
848 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
856 /* Enable the Output compare channel */
857 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
859 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
861 /* Enable the main output */
862 __HAL_TIM_MOE_ENABLE(htim);
865 /* Enable the Peripheral */
866 __HAL_TIM_ENABLE(htim);
868 /* Return function status */
873 * @brief Stops the TIM Output Compare signal generation in DMA mode.
874 * @param htim : TIM Output Compare handle
875 * @param Channel : TIM Channel to be disabled
876 * This parameter can be one of the following values:
877 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
878 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
879 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
880 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
883 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
885 /* Check the parameters */
886 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
892 /* Disable the TIM Capture/Compare 1 DMA request */
893 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
899 /* Disable the TIM Capture/Compare 2 DMA request */
900 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
906 /* Disable the TIM Capture/Compare 3 DMA request */
907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
913 /* Disable the TIM Capture/Compare 4 interrupt */
914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
922 /* Disable the Output compare channel */
923 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
925 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
927 /* Disable the Main Ouput */
928 __HAL_TIM_MOE_DISABLE(htim);
931 /* Disable the Peripheral */
932 __HAL_TIM_DISABLE(htim);
934 /* Change the htim state */
935 htim->State = HAL_TIM_STATE_READY;
937 /* Return function status */
945 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
946 * @brief Time PWM functions
949 ==============================================================================
950 ##### Time PWM functions #####
951 ==============================================================================
953 This section provides functions allowing to:
954 (+) Initialize and configure the TIM OPWM.
955 (+) De-initialize the TIM PWM.
956 (+) Start the Time PWM.
957 (+) Stop the Time PWM.
958 (+) Start the Time PWM and enable interrupt.
959 (+) Stop the Time PWM and disable interrupt.
960 (+) Start the Time PWM and enable DMA transfer.
961 (+) Stop the Time PWM and disable DMA transfer.
967 * @brief Initializes the TIM PWM Time Base according to the specified
968 * parameters in the TIM_HandleTypeDef and create the associated handle.
969 * @param htim : TIM handle
972 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
974 /* Check the TIM handle allocation */
980 /* Check the parameters */
981 assert_param(IS_TIM_INSTANCE(htim->Instance));
982 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
983 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
985 if(htim->State == HAL_TIM_STATE_RESET)
987 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
988 HAL_TIM_PWM_MspInit(htim);
991 /* Set the TIM state */
992 htim->State= HAL_TIM_STATE_BUSY;
994 /* Init the base time for the PWM */
995 TIM_Base_SetConfig(htim->Instance, &htim->Init);
997 /* Initialize the TIM state*/
998 htim->State= HAL_TIM_STATE_READY;
1004 * @brief DeInitializes the TIM peripheral
1005 * @param htim : TIM handle
1006 * @retval HAL status
1008 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1010 /* Check the parameters */
1011 assert_param(IS_TIM_INSTANCE(htim->Instance));
1013 htim->State = HAL_TIM_STATE_BUSY;
1015 /* Disable the TIM Peripheral Clock */
1016 __HAL_TIM_DISABLE(htim);
1018 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1019 HAL_TIM_PWM_MspDeInit(htim);
1021 /* Change TIM state */
1022 htim->State = HAL_TIM_STATE_RESET;
1031 * @brief Initializes the TIM PWM MSP.
1032 * @param htim : TIM handle
1035 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1037 /* NOTE : This function Should not be modified, when the callback is needed,
1038 the HAL_TIM_PWM_MspInit could be implemented in the user file
1043 * @brief DeInitializes TIM PWM MSP.
1044 * @param htim : TIM handle
1047 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1049 /* NOTE : This function Should not be modified, when the callback is needed,
1050 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1055 * @brief Starts the PWM signal generation.
1056 * @param htim : TIM handle
1057 * @param Channel : TIM Channels to be enabled
1058 * This parameter can be one of the following values:
1059 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1060 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1061 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1062 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1063 * @retval HAL status
1065 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1067 /* Check the parameters */
1068 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1070 /* Enable the Capture compare channel */
1071 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1073 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1075 /* Enable the main output */
1076 __HAL_TIM_MOE_ENABLE(htim);
1079 /* Enable the Peripheral */
1080 __HAL_TIM_ENABLE(htim);
1082 /* Return function status */
1087 * @brief Stops the PWM signal generation.
1088 * @param htim : TIM handle
1089 * @param Channel : TIM Channels to be disabled
1090 * This parameter can be one of the following values:
1091 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1092 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1093 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1094 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1095 * @retval HAL status
1097 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1099 /* Check the parameters */
1100 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1102 /* Disable the Capture compare channel */
1103 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1105 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1107 /* Disable the Main Ouput */
1108 __HAL_TIM_MOE_DISABLE(htim);
1111 /* Disable the Peripheral */
1112 __HAL_TIM_DISABLE(htim);
1114 /* Change the htim state */
1115 htim->State = HAL_TIM_STATE_READY;
1117 /* Return function status */
1122 * @brief Starts the PWM signal generation in interrupt mode.
1123 * @param htim : TIM handle
1124 * @param Channel : TIM Channel to be disabled
1125 * This parameter can be one of the following values:
1126 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1127 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1128 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1129 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1130 * @retval HAL status
1132 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1134 /* Check the parameters */
1135 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1141 /* Enable the TIM Capture/Compare 1 interrupt */
1142 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1148 /* Enable the TIM Capture/Compare 2 interrupt */
1149 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1155 /* Enable the TIM Capture/Compare 3 interrupt */
1156 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1162 /* Enable the TIM Capture/Compare 4 interrupt */
1163 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1171 /* Enable the Capture compare channel */
1172 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1174 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1176 /* Enable the main output */
1177 __HAL_TIM_MOE_ENABLE(htim);
1180 /* Enable the Peripheral */
1181 __HAL_TIM_ENABLE(htim);
1183 /* Return function status */
1188 * @brief Stops the PWM signal generation in interrupt mode.
1189 * @param htim : TIM handle
1190 * @param Channel : TIM Channels to be disabled
1191 * This parameter can be one of the following values:
1192 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1193 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1194 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1195 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1196 * @retval HAL status
1198 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1200 /* Check the parameters */
1201 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1207 /* Disable the TIM Capture/Compare 1 interrupt */
1208 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1214 /* Disable the TIM Capture/Compare 2 interrupt */
1215 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1221 /* Disable the TIM Capture/Compare 3 interrupt */
1222 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1228 /* Disable the TIM Capture/Compare 4 interrupt */
1229 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1237 /* Disable the Capture compare channel */
1238 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1240 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1242 /* Disable the Main Ouput */
1243 __HAL_TIM_MOE_DISABLE(htim);
1246 /* Disable the Peripheral */
1247 __HAL_TIM_DISABLE(htim);
1249 /* Return function status */
1254 * @brief Starts the TIM PWM signal generation in DMA mode.
1255 * @param htim : TIM handle
1256 * @param Channel : TIM Channels to be enabled
1257 * This parameter can be one of the following values:
1258 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1259 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1260 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1261 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1262 * @param pData : The source Buffer address.
1263 * @param Length : The length of data to be transferred from memory to TIM peripheral
1264 * @retval HAL status
1266 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1268 /* Check the parameters */
1269 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1271 if((htim->State == HAL_TIM_STATE_BUSY))
1275 else if((htim->State == HAL_TIM_STATE_READY))
1277 if(((uint32_t)pData == 0 ) && (Length > 0))
1283 htim->State = HAL_TIM_STATE_BUSY;
1290 /* Set the DMA Period elapsed callback */
1291 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1293 /* Set the DMA error callback */
1294 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1296 /* Enable the DMA channel */
1297 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1299 /* Enable the TIM Capture/Compare 1 DMA request */
1300 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1306 /* Set the DMA Period elapsed callback */
1307 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1309 /* Set the DMA error callback */
1310 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1312 /* Enable the DMA channel */
1313 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1315 /* Enable the TIM Capture/Compare 2 DMA request */
1316 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1322 /* Set the DMA Period elapsed callback */
1323 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1325 /* Set the DMA error callback */
1326 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1328 /* Enable the DMA channel */
1329 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1331 /* Enable the TIM Output Capture/Compare 3 request */
1332 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1338 /* Set the DMA Period elapsed callback */
1339 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1341 /* Set the DMA error callback */
1342 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1344 /* Enable the DMA channel */
1345 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1347 /* Enable the TIM Capture/Compare 4 DMA request */
1348 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1356 /* Enable the Capture compare channel */
1357 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1359 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1361 /* Enable the main output */
1362 __HAL_TIM_MOE_ENABLE(htim);
1365 /* Enable the Peripheral */
1366 __HAL_TIM_ENABLE(htim);
1368 /* Return function status */
1373 * @brief Stops the TIM PWM signal generation in DMA mode.
1374 * @param htim : TIM handle
1375 * @param Channel : TIM Channels to be disabled
1376 * This parameter can be one of the following values:
1377 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1378 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1379 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1380 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1381 * @retval HAL status
1383 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1385 /* Check the parameters */
1386 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1392 /* Disable the TIM Capture/Compare 1 DMA request */
1393 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1399 /* Disable the TIM Capture/Compare 2 DMA request */
1400 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1406 /* Disable the TIM Capture/Compare 3 DMA request */
1407 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1413 /* Disable the TIM Capture/Compare 4 interrupt */
1414 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1422 /* Disable the Capture compare channel */
1423 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1425 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1427 /* Disable the Main Ouput */
1428 __HAL_TIM_MOE_DISABLE(htim);
1431 /* Disable the Peripheral */
1432 __HAL_TIM_DISABLE(htim);
1434 /* Change the htim state */
1435 htim->State = HAL_TIM_STATE_READY;
1437 /* Return function status */
1445 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1446 * @brief Time Input Capture functions
1449 ==============================================================================
1450 ##### Time Input Capture functions #####
1451 ==============================================================================
1453 This section provides functions allowing to:
1454 (+) Initialize and configure the TIM Input Capture.
1455 (+) De-initialize the TIM Input Capture.
1456 (+) Start the Time Input Capture.
1457 (+) Stop the Time Input Capture.
1458 (+) Start the Time Input Capture and enable interrupt.
1459 (+) Stop the Time Input Capture and disable interrupt.
1460 (+) Start the Time Input Capture and enable DMA transfer.
1461 (+) Stop the Time Input Capture and disable DMA transfer.
1467 * @brief Initializes the TIM Input Capture Time base according to the specified
1468 * parameters in the TIM_HandleTypeDef and create the associated handle.
1469 * @param htim : TIM Input Capture handle
1470 * @retval HAL status
1472 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1474 /* Check the TIM handle allocation */
1480 /* Check the parameters */
1481 assert_param(IS_TIM_INSTANCE(htim->Instance));
1482 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1483 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1485 if(htim->State == HAL_TIM_STATE_RESET)
1487 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1488 HAL_TIM_IC_MspInit(htim);
1491 /* Set the TIM state */
1492 htim->State= HAL_TIM_STATE_BUSY;
1494 /* Init the base time for the input capture */
1495 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1497 /* Initialize the TIM state*/
1498 htim->State= HAL_TIM_STATE_READY;
1504 * @brief DeInitializes the TIM peripheral
1505 * @param htim : TIM Input Capture handle
1506 * @retval HAL status
1508 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1510 /* Check the parameters */
1511 assert_param(IS_TIM_INSTANCE(htim->Instance));
1513 htim->State = HAL_TIM_STATE_BUSY;
1515 /* Disable the TIM Peripheral Clock */
1516 __HAL_TIM_DISABLE(htim);
1518 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1519 HAL_TIM_IC_MspDeInit(htim);
1521 /* Change TIM state */
1522 htim->State = HAL_TIM_STATE_RESET;
1531 * @brief Initializes the TIM Input Capture MSP.
1532 * @param htim : TIM handle
1535 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1537 /* NOTE : This function Should not be modified, when the callback is needed,
1538 the HAL_TIM_IC_MspInit could be implemented in the user file
1543 * @brief DeInitializes TIM Input Capture MSP.
1544 * @param htim : TIM handle
1547 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1549 /* NOTE : This function Should not be modified, when the callback is needed,
1550 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1555 * @brief Starts the TIM Input Capture measurement.
1556 * @param htim : TIM Input Capture handle
1557 * @param Channel : TIM Channels to be enabled
1558 * This parameter can be one of the following values:
1559 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1560 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1561 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1562 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1563 * @retval HAL status
1565 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1567 /* Check the parameters */
1568 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1570 /* Enable the Input Capture channel */
1571 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1573 /* Enable the Peripheral */
1574 __HAL_TIM_ENABLE(htim);
1576 /* Return function status */
1581 * @brief Stops the TIM Input Capture measurement.
1582 * @param htim : TIM handle
1583 * @param Channel : TIM Channels to be disabled
1584 * This parameter can be one of the following values:
1585 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1586 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1587 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1588 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1589 * @retval HAL status
1591 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1593 /* Check the parameters */
1594 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1596 /* Disable the Input Capture channel */
1597 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1599 /* Disable the Peripheral */
1600 __HAL_TIM_DISABLE(htim);
1602 /* Return function status */
1607 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1608 * @param htim : TIM Input Capture handle
1609 * @param Channel : TIM Channels to be enabled
1610 * This parameter can be one of the following values:
1611 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1612 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1613 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1614 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1615 * @retval HAL status
1617 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1619 /* Check the parameters */
1620 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1626 /* Enable the TIM Capture/Compare 1 interrupt */
1627 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1633 /* Enable the TIM Capture/Compare 2 interrupt */
1634 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1640 /* Enable the TIM Capture/Compare 3 interrupt */
1641 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1647 /* Enable the TIM Capture/Compare 4 interrupt */
1648 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1655 /* Enable the Input Capture channel */
1656 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1658 /* Enable the Peripheral */
1659 __HAL_TIM_ENABLE(htim);
1661 /* Return function status */
1666 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1667 * @param htim : TIM handle
1668 * @param Channel : TIM Channels to be disabled
1669 * This parameter can be one of the following values:
1670 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1671 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1672 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1673 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1674 * @retval HAL status
1676 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1678 /* Check the parameters */
1679 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1685 /* Disable the TIM Capture/Compare 1 interrupt */
1686 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1692 /* Disable the TIM Capture/Compare 2 interrupt */
1693 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1699 /* Disable the TIM Capture/Compare 3 interrupt */
1700 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1706 /* Disable the TIM Capture/Compare 4 interrupt */
1707 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1715 /* Disable the Input Capture channel */
1716 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1718 /* Disable the Peripheral */
1719 __HAL_TIM_DISABLE(htim);
1721 /* Return function status */
1726 * @brief Starts the TIM Input Capture measurement in DMA mode.
1727 * @param htim : TIM Input Capture handle
1728 * @param Channel : TIM Channels to be enabled
1729 * This parameter can be one of the following values:
1730 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1731 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1732 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1733 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1734 * @param pData : The destination Buffer address.
1735 * @param Length : The length of data to be transferred from TIM peripheral to memory.
1736 * @retval HAL status
1738 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1740 /* Check the parameters */
1741 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1742 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1744 if((htim->State == HAL_TIM_STATE_BUSY))
1748 else if((htim->State == HAL_TIM_STATE_READY))
1750 if((pData == 0 ) && (Length > 0))
1756 htim->State = HAL_TIM_STATE_BUSY;
1764 /* Set the DMA Period elapsed callback */
1765 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1767 /* Set the DMA error callback */
1768 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1770 /* Enable the DMA channel */
1771 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1773 /* Enable the TIM Capture/Compare 1 DMA request */
1774 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1780 /* Set the DMA Period elapsed callback */
1781 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1783 /* Set the DMA error callback */
1784 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1786 /* Enable the DMA channel */
1787 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1789 /* Enable the TIM Capture/Compare 2 DMA request */
1790 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1796 /* Set the DMA Period elapsed callback */
1797 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1799 /* Set the DMA error callback */
1800 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1802 /* Enable the DMA channel */
1803 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1805 /* Enable the TIM Capture/Compare 3 DMA request */
1806 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1812 /* Set the DMA Period elapsed callback */
1813 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1815 /* Set the DMA error callback */
1816 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1818 /* Enable the DMA channel */
1819 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1821 /* Enable the TIM Capture/Compare 4 DMA request */
1822 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1830 /* Enable the Input Capture channel */
1831 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1833 /* Enable the Peripheral */
1834 __HAL_TIM_ENABLE(htim);
1836 /* Return function status */
1841 * @brief Stops the TIM Input Capture measurement in DMA mode.
1842 * @param htim : TIM Input Capture handle
1843 * @param Channel : TIM Channels to be disabled
1844 * This parameter can be one of the following values:
1845 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1846 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1847 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1848 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1849 * @retval HAL status
1851 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1853 /* Check the parameters */
1854 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1855 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1861 /* Disable the TIM Capture/Compare 1 DMA request */
1862 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1868 /* Disable the TIM Capture/Compare 2 DMA request */
1869 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1875 /* Disable the TIM Capture/Compare 3 DMA request */
1876 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1882 /* Disable the TIM Capture/Compare 4 DMA request */
1883 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1891 /* Disable the Input Capture channel */
1892 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1894 /* Disable the Peripheral */
1895 __HAL_TIM_DISABLE(htim);
1897 /* Change the htim state */
1898 htim->State = HAL_TIM_STATE_READY;
1900 /* Return function status */
1907 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1908 * @brief Time One Pulse functions
1911 ==============================================================================
1912 ##### Time One Pulse functions #####
1913 ==============================================================================
1915 This section provides functions allowing to:
1916 (+) Initialize and configure the TIM One Pulse.
1917 (+) De-initialize the TIM One Pulse.
1918 (+) Start the Time One Pulse.
1919 (+) Stop the Time One Pulse.
1920 (+) Start the Time One Pulse and enable interrupt.
1921 (+) Stop the Time One Pulse and disable interrupt.
1922 (+) Start the Time One Pulse and enable DMA transfer.
1923 (+) Stop the Time One Pulse and disable DMA transfer.
1929 * @brief Initializes the TIM One Pulse Time Base according to the specified
1930 * parameters in the TIM_HandleTypeDef and create the associated handle.
1931 * @param htim : TIM OnePulse handle
1932 * @param OnePulseMode : Select the One pulse mode.
1933 * This parameter can be one of the following values:
1934 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1935 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
1936 * @retval HAL status
1938 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1940 /* Check the TIM handle allocation */
1946 /* Check the parameters */
1947 assert_param(IS_TIM_INSTANCE(htim->Instance));
1948 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1949 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1950 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1952 if(htim->State == HAL_TIM_STATE_RESET)
1954 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1955 HAL_TIM_OnePulse_MspInit(htim);
1958 /* Set the TIM state */
1959 htim->State= HAL_TIM_STATE_BUSY;
1961 /* Configure the Time base in the One Pulse Mode */
1962 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1964 /* Reset the OPM Bit */
1965 htim->Instance->CR1 &= ~TIM_CR1_OPM;
1967 /* Configure the OPM Mode */
1968 htim->Instance->CR1 |= OnePulseMode;
1970 /* Initialize the TIM state*/
1971 htim->State= HAL_TIM_STATE_READY;
1977 * @brief DeInitializes the TIM One Pulse
1978 * @param htim : TIM One Pulse handle
1979 * @retval HAL status
1981 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
1983 /* Check the parameters */
1984 assert_param(IS_TIM_INSTANCE(htim->Instance));
1986 htim->State = HAL_TIM_STATE_BUSY;
1988 /* Disable the TIM Peripheral Clock */
1989 __HAL_TIM_DISABLE(htim);
1991 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
1992 HAL_TIM_OnePulse_MspDeInit(htim);
1994 /* Change TIM state */
1995 htim->State = HAL_TIM_STATE_RESET;
2004 * @brief Initializes the TIM One Pulse MSP.
2005 * @param htim : TIM handle
2008 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2010 /* NOTE : This function Should not be modified, when the callback is needed,
2011 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2016 * @brief DeInitializes TIM One Pulse MSP.
2017 * @param htim : TIM handle
2020 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2022 /* NOTE : This function Should not be modified, when the callback is needed,
2023 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2028 * @brief Starts the TIM One Pulse signal generation.
2029 * @param htim : TIM One Pulse handle
2030 * @param OutputChannel : TIM Channels to be enabled
2031 * This parameter can be one of the following values:
2032 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2033 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2034 * @retval HAL status
2036 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2038 /* Enable the Capture compare and the Input Capture channels
2039 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2040 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2041 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2042 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2044 No need to enable the counter, it's enabled automatically by hardware
2045 (the counter starts in response to a stimulus and generate a pulse */
2047 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2048 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2050 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2052 /* Enable the main output */
2053 __HAL_TIM_MOE_ENABLE(htim);
2056 /* Return function status */
2061 * @brief Stops the TIM One Pulse signal generation.
2062 * @param htim : TIM One Pulse handle
2063 * @param OutputChannel : TIM Channels to be disable
2064 * This parameter can be one of the following values:
2065 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2066 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2067 * @retval HAL status
2069 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2071 /* Disable the Capture compare and the Input Capture channels
2072 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2073 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2074 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2075 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2077 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2078 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2080 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2082 /* Disable the Main Ouput */
2083 __HAL_TIM_MOE_DISABLE(htim);
2086 /* Disable the Peripheral */
2087 __HAL_TIM_DISABLE(htim);
2089 /* Return function status */
2094 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2095 * @param htim : TIM One Pulse handle
2096 * @param OutputChannel : TIM Channels to be enabled
2097 * This parameter can be one of the following values:
2098 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2099 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2100 * @retval HAL status
2102 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2104 /* Enable the Capture compare and the Input Capture channels
2105 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2106 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2107 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2108 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2110 No need to enable the counter, it's enabled automatically by hardware
2111 (the counter starts in response to a stimulus and generate a pulse */
2113 /* Enable the TIM Capture/Compare 1 interrupt */
2114 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2116 /* Enable the TIM Capture/Compare 2 interrupt */
2117 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2119 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2120 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2122 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2124 /* Enable the main output */
2125 __HAL_TIM_MOE_ENABLE(htim);
2128 /* Return function status */
2133 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2134 * @param htim : TIM One Pulse handle
2135 * @param OutputChannel : TIM Channels to be enabled
2136 * This parameter can be one of the following values:
2137 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2138 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2139 * @retval HAL status
2141 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2143 /* Disable the TIM Capture/Compare 1 interrupt */
2144 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2146 /* Disable the TIM Capture/Compare 2 interrupt */
2147 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2149 /* Disable the Capture compare and the Input Capture channels
2150 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2151 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2152 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2153 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2154 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2155 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2157 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2159 /* Disable the Main Ouput */
2160 __HAL_TIM_MOE_DISABLE(htim);
2163 /* Disable the Peripheral */
2164 __HAL_TIM_DISABLE(htim);
2166 /* Return function status */
2174 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2175 * @brief Time Encoder functions
2178 ==============================================================================
2179 ##### Time Encoder functions #####
2180 ==============================================================================
2182 This section provides functions allowing to:
2183 (+) Initialize and configure the TIM Encoder.
2184 (+) De-initialize the TIM Encoder.
2185 (+) Start the Time Encoder.
2186 (+) Stop the Time Encoder.
2187 (+) Start the Time Encoder and enable interrupt.
2188 (+) Stop the Time Encoder and disable interrupt.
2189 (+) Start the Time Encoder and enable DMA transfer.
2190 (+) Stop the Time Encoder and disable DMA transfer.
2196 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2197 * @param htim : TIM Encoder Interface handle
2198 * @param sConfig : TIM Encoder Interface configuration structure
2199 * @retval HAL status
2201 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2203 uint32_t tmpsmcr = 0;
2204 uint32_t tmpccmr1 = 0;
2205 uint32_t tmpccer = 0;
2207 /* Check the TIM handle allocation */
2213 /* Check the parameters */
2214 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2215 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2216 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2217 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2218 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2219 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2220 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2221 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2222 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2223 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2225 if(htim->State == HAL_TIM_STATE_RESET)
2227 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2228 HAL_TIM_Encoder_MspInit(htim);
2231 /* Set the TIM state */
2232 htim->State= HAL_TIM_STATE_BUSY;
2234 /* Reset the SMS bits */
2235 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2237 /* Configure the Time base in the Encoder Mode */
2238 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2240 /* Get the TIMx SMCR register value */
2241 tmpsmcr = htim->Instance->SMCR;
2243 /* Get the TIMx CCMR1 register value */
2244 tmpccmr1 = htim->Instance->CCMR1;
2246 /* Get the TIMx CCER register value */
2247 tmpccer = htim->Instance->CCER;
2249 /* Set the encoder Mode */
2250 tmpsmcr |= sConfig->EncoderMode;
2252 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2253 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2254 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
2256 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2257 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2258 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2259 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
2260 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
2262 /* Set the TI1 and the TI2 Polarities */
2263 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2264 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2265 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
2267 /* Write to TIMx SMCR */
2268 htim->Instance->SMCR = tmpsmcr;
2270 /* Write to TIMx CCMR1 */
2271 htim->Instance->CCMR1 = tmpccmr1;
2273 /* Write to TIMx CCER */
2274 htim->Instance->CCER = tmpccer;
2276 /* Initialize the TIM state*/
2277 htim->State= HAL_TIM_STATE_READY;
2284 * @brief DeInitializes the TIM Encoder interface
2285 * @param htim : TIM Encoder handle
2286 * @retval HAL status
2288 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2290 /* Check the parameters */
2291 assert_param(IS_TIM_INSTANCE(htim->Instance));
2293 htim->State = HAL_TIM_STATE_BUSY;
2295 /* Disable the TIM Peripheral Clock */
2296 __HAL_TIM_DISABLE(htim);
2298 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2299 HAL_TIM_Encoder_MspDeInit(htim);
2301 /* Change TIM state */
2302 htim->State = HAL_TIM_STATE_RESET;
2311 * @brief Initializes the TIM Encoder Interface MSP.
2312 * @param htim : TIM handle
2315 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2317 /* NOTE : This function Should not be modified, when the callback is needed,
2318 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2323 * @brief DeInitializes TIM Encoder Interface MSP.
2324 * @param htim : TIM handle
2327 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2329 /* NOTE : This function Should not be modified, when the callback is needed,
2330 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2335 * @brief Starts the TIM Encoder Interface.
2336 * @param htim : TIM Encoder Interface handle
2337 * @param Channel : TIM Channels to be enabled
2338 * This parameter can be one of the following values:
2339 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2340 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2341 * @retval HAL status
2343 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2345 /* Check the parameters */
2346 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2348 /* Enable the encoder interface channels */
2353 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2358 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2363 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2364 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2368 /* Enable the Peripheral */
2369 __HAL_TIM_ENABLE(htim);
2371 /* Return function status */
2376 * @brief Stops the TIM Encoder Interface.
2377 * @param htim : TIM Encoder Interface handle
2378 * @param Channel : TIM Channels to be disabled
2379 * This parameter can be one of the following values:
2380 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2381 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2382 * @retval HAL status
2384 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2386 /* Check the parameters */
2387 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2389 /* Disable the Input Capture channels 1 and 2
2390 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2395 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2400 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2405 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2406 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2411 /* Disable the Peripheral */
2412 __HAL_TIM_DISABLE(htim);
2414 /* Return function status */
2419 * @brief Starts the TIM Encoder Interface in interrupt mode.
2420 * @param htim : TIM Encoder Interface handle
2421 * @param Channel : TIM Channels to be enabled
2422 * This parameter can be one of the following values:
2423 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2424 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2425 * @retval HAL status
2427 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2429 /* Check the parameters */
2430 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2432 /* Enable the encoder interface channels */
2433 /* Enable the capture compare Interrupts 1 and/or 2 */
2438 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2439 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2451 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2452 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2453 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2458 /* Enable the Peripheral */
2459 __HAL_TIM_ENABLE(htim);
2461 /* Return function status */
2466 * @brief Stops the TIM Encoder Interface in interrupt mode.
2467 * @param htim : TIM Encoder Interface handle
2468 * @param Channel : TIM Channels to be disabled
2469 * This parameter can be one of the following values:
2470 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2471 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2472 * @retval HAL status
2474 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2476 /* Check the parameters */
2477 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2479 /* Disable the Input Capture channels 1 and 2
2480 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2481 if(Channel == TIM_CHANNEL_1)
2483 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2485 /* Disable the capture compare Interrupts 1 */
2486 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2488 else if(Channel == TIM_CHANNEL_2)
2490 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2492 /* Disable the capture compare Interrupts 2 */
2493 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2497 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2498 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2500 /* Disable the capture compare Interrupts 1 and 2 */
2501 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2502 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2505 /* Disable the Peripheral */
2506 __HAL_TIM_DISABLE(htim);
2508 /* Change the htim state */
2509 htim->State = HAL_TIM_STATE_READY;
2511 /* Return function status */
2516 * @brief Starts the TIM Encoder Interface in DMA mode.
2517 * @param htim : TIM Encoder Interface handle
2518 * @param Channel : TIM Channels to be enabled
2519 * This parameter can be one of the following values:
2520 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2521 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2522 * @param pData1 : The destination Buffer address for IC1.
2523 * @param pData2 : The destination Buffer address for IC2.
2524 * @param Length : The length of data to be transferred from TIM peripheral to memory.
2525 * @retval HAL status
2527 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2529 /* Check the parameters */
2530 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2532 if((htim->State == HAL_TIM_STATE_BUSY))
2536 else if((htim->State == HAL_TIM_STATE_READY))
2538 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
2544 htim->State = HAL_TIM_STATE_BUSY;
2552 /* Set the DMA Period elapsed callback */
2553 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2555 /* Set the DMA error callback */
2556 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
2558 /* Enable the DMA channel */
2559 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2561 /* Enable the TIM Input Capture DMA request */
2562 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2564 /* Enable the Peripheral */
2565 __HAL_TIM_ENABLE(htim);
2567 /* Enable the Capture compare channel */
2568 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2574 /* Set the DMA Period elapsed callback */
2575 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2577 /* Set the DMA error callback */
2578 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
2579 /* Enable the DMA channel */
2580 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2582 /* Enable the TIM Input Capture DMA request */
2583 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2585 /* Enable the Peripheral */
2586 __HAL_TIM_ENABLE(htim);
2588 /* Enable the Capture compare channel */
2589 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2593 case TIM_CHANNEL_ALL:
2595 /* Set the DMA Period elapsed callback */
2596 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2598 /* Set the DMA error callback */
2599 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
2601 /* Enable the DMA channel */
2602 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2604 /* Set the DMA Period elapsed callback */
2605 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2607 /* Set the DMA error callback */
2608 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
2610 /* Enable the DMA channel */
2611 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2613 /* Enable the Peripheral */
2614 __HAL_TIM_ENABLE(htim);
2616 /* Enable the Capture compare channel */
2617 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2618 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2620 /* Enable the TIM Input Capture DMA request */
2621 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2622 /* Enable the TIM Input Capture DMA request */
2623 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2630 /* Return function status */
2635 * @brief Stops the TIM Encoder Interface in DMA mode.
2636 * @param htim : TIM Encoder Interface handle
2637 * @param Channel : TIM Channels to be enabled
2638 * This parameter can be one of the following values:
2639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2641 * @retval HAL status
2643 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2645 /* Check the parameters */
2646 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2648 /* Disable the Input Capture channels 1 and 2
2649 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2650 if(Channel == TIM_CHANNEL_1)
2652 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2654 /* Disable the capture compare DMA Request 1 */
2655 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2657 else if(Channel == TIM_CHANNEL_2)
2659 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2661 /* Disable the capture compare DMA Request 2 */
2662 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2666 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2667 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2669 /* Disable the capture compare DMA Request 1 and 2 */
2670 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2671 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2674 /* Disable the Peripheral */
2675 __HAL_TIM_DISABLE(htim);
2677 /* Change the htim state */
2678 htim->State = HAL_TIM_STATE_READY;
2680 /* Return function status */
2687 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2688 * @brief IRQ handler management
2691 ==============================================================================
2692 ##### IRQ handler management #####
2693 ==============================================================================
2695 This section provides Timer IRQ handler function.
2701 * @brief This function handles TIM interrupts requests.
2702 * @param htim : TIM handle
2705 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2707 /* Capture compare 1 event */
2708 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2710 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
2713 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2714 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2716 /* Input capture event */
2717 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
2719 HAL_TIM_IC_CaptureCallback(htim);
2721 /* Output compare event */
2724 HAL_TIM_OC_DelayElapsedCallback(htim);
2725 HAL_TIM_PWM_PulseFinishedCallback(htim);
2727 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2731 /* Capture compare 2 event */
2732 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2734 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
2736 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2737 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2738 /* Input capture event */
2739 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
2741 HAL_TIM_IC_CaptureCallback(htim);
2743 /* Output compare event */
2746 HAL_TIM_OC_DelayElapsedCallback(htim);
2747 HAL_TIM_PWM_PulseFinishedCallback(htim);
2749 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2752 /* Capture compare 3 event */
2753 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2755 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
2757 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2758 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2759 /* Input capture event */
2760 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
2762 HAL_TIM_IC_CaptureCallback(htim);
2764 /* Output compare event */
2767 HAL_TIM_OC_DelayElapsedCallback(htim);
2768 HAL_TIM_PWM_PulseFinishedCallback(htim);
2770 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2773 /* Capture compare 4 event */
2774 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2776 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
2778 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2779 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2780 /* Input capture event */
2781 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
2783 HAL_TIM_IC_CaptureCallback(htim);
2785 /* Output compare event */
2788 HAL_TIM_OC_DelayElapsedCallback(htim);
2789 HAL_TIM_PWM_PulseFinishedCallback(htim);
2791 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2794 /* TIM Update event */
2795 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2797 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
2799 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2800 HAL_TIM_PeriodElapsedCallback(htim);
2803 /* TIM Break input event */
2804 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
2806 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
2808 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
2809 HAL_TIMEx_BreakCallback(htim);
2812 /* TIM Trigger detection event */
2813 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2815 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
2817 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2818 HAL_TIM_TriggerCallback(htim);
2821 /* TIM commutation event */
2822 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
2824 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
2826 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
2827 HAL_TIMEx_CommutationCallback(htim);
2836 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2837 * @brief Peripheral Control functions
2840 ==============================================================================
2841 ##### Peripheral Control functions #####
2842 ==============================================================================
2844 This section provides functions allowing to:
2845 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2846 (+) Configure External Clock source.
2847 (+) Configure Complementary channels, break features and dead time.
2848 (+) Configure Master and the Slave synchronization.
2849 (+) Configure the DMA Burst Mode.
2856 * @brief Initializes the TIM Output Compare Channels according to the specified
2857 * parameters in the TIM_OC_InitTypeDef.
2858 * @param htim : TIM Output Compare handle
2859 * @param sConfig : TIM Output Compare configuration structure
2860 * @param Channel : TIM Channels to be enabled
2861 * This parameter can be one of the following values:
2862 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2863 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2864 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2865 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2866 * @retval HAL status
2868 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2870 /* Check the parameters */
2871 assert_param(IS_TIM_CHANNELS(Channel));
2872 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2873 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2874 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
2875 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
2876 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
2878 /* Check input state */
2881 htim->State = HAL_TIM_STATE_BUSY;
2887 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2888 /* Configure the TIM Channel 1 in Output Compare */
2889 TIM_OC1_SetConfig(htim->Instance, sConfig);
2895 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2896 /* Configure the TIM Channel 2 in Output Compare */
2897 TIM_OC2_SetConfig(htim->Instance, sConfig);
2903 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2904 /* Configure the TIM Channel 3 in Output Compare */
2905 TIM_OC3_SetConfig(htim->Instance, sConfig);
2911 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2912 /* Configure the TIM Channel 4 in Output Compare */
2913 TIM_OC4_SetConfig(htim->Instance, sConfig);
2920 htim->State = HAL_TIM_STATE_READY;
2928 * @brief Initializes the TIM Input Capture Channels according to the specified
2929 * parameters in the TIM_IC_InitTypeDef.
2930 * @param htim : TIM IC handle
2931 * @param sConfig : TIM Input Capture configuration structure
2932 * @param Channel : TIM Channels to be enabled
2933 * This parameter can be one of the following values:
2934 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2935 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2936 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2937 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2938 * @retval HAL status
2940 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
2942 /* Check the parameters */
2943 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2944 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
2945 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
2946 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
2947 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
2951 htim->State = HAL_TIM_STATE_BUSY;
2953 if (Channel == TIM_CHANNEL_1)
2955 /* TI1 Configuration */
2956 TIM_TI1_SetConfig(htim->Instance,
2957 sConfig->ICPolarity,
2958 sConfig->ICSelection,
2961 /* Reset the IC1PSC Bits */
2962 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
2964 /* Set the IC1PSC value */
2965 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
2967 else if (Channel == TIM_CHANNEL_2)
2969 /* TI2 Configuration */
2970 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2972 TIM_TI2_SetConfig(htim->Instance,
2973 sConfig->ICPolarity,
2974 sConfig->ICSelection,
2977 /* Reset the IC2PSC Bits */
2978 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
2980 /* Set the IC2PSC value */
2981 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
2983 else if (Channel == TIM_CHANNEL_3)
2985 /* TI3 Configuration */
2986 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2988 TIM_TI3_SetConfig(htim->Instance,
2989 sConfig->ICPolarity,
2990 sConfig->ICSelection,
2993 /* Reset the IC3PSC Bits */
2994 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
2996 /* Set the IC3PSC value */
2997 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3001 /* TI4 Configuration */
3002 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3004 TIM_TI4_SetConfig(htim->Instance,
3005 sConfig->ICPolarity,
3006 sConfig->ICSelection,
3009 /* Reset the IC4PSC Bits */
3010 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3012 /* Set the IC4PSC value */
3013 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
3016 htim->State = HAL_TIM_STATE_READY;
3024 * @brief Initializes the TIM PWM channels according to the specified
3025 * parameters in the TIM_OC_InitTypeDef.
3026 * @param htim : TIM handle
3027 * @param sConfig : TIM PWM configuration structure
3028 * @param Channel : TIM Channels to be enabled
3029 * This parameter can be one of the following values:
3030 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3031 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3032 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3033 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3034 * @retval HAL status
3036 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
3040 /* Check the parameters */
3041 assert_param(IS_TIM_CHANNELS(Channel));
3042 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3043 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3044 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
3045 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3046 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
3047 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
3049 htim->State = HAL_TIM_STATE_BUSY;
3055 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3056 /* Configure the Channel 1 in PWM mode */
3057 TIM_OC1_SetConfig(htim->Instance, sConfig);
3059 /* Set the Preload enable bit for channel1 */
3060 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3062 /* Configure the Output Fast mode */
3063 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3064 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3070 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3071 /* Configure the Channel 2 in PWM mode */
3072 TIM_OC2_SetConfig(htim->Instance, sConfig);
3074 /* Set the Preload enable bit for channel2 */
3075 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3077 /* Configure the Output Fast mode */
3078 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3079 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
3085 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3086 /* Configure the Channel 3 in PWM mode */
3087 TIM_OC3_SetConfig(htim->Instance, sConfig);
3089 /* Set the Preload enable bit for channel3 */
3090 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3092 /* Configure the Output Fast mode */
3093 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3094 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3100 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3101 /* Configure the Channel 4 in PWM mode */
3102 TIM_OC4_SetConfig(htim->Instance, sConfig);
3104 /* Set the Preload enable bit for channel4 */
3105 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3107 /* Configure the Output Fast mode */
3108 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3109 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
3117 htim->State = HAL_TIM_STATE_READY;
3125 * @brief Initializes the TIM One Pulse Channels according to the specified
3126 * parameters in the TIM_OnePulse_InitTypeDef.
3127 * @param htim : TIM One Pulse handle
3128 * @param sConfig : TIM One Pulse configuration structure
3129 * @param OutputChannel : TIM Channels to be enabled
3130 * This parameter can be one of the following values:
3131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3133 * @param InputChannel : TIM Channels to be enabled
3134 * This parameter can be one of the following values:
3135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3137 * @retval HAL status
3139 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3141 TIM_OC_InitTypeDef temp1;
3143 /* Check the parameters */
3144 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3145 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3147 if(OutputChannel != InputChannel)
3151 htim->State = HAL_TIM_STATE_BUSY;
3153 /* Extract the Ouput compare configuration from sConfig structure */
3154 temp1.OCMode = sConfig->OCMode;
3155 temp1.Pulse = sConfig->Pulse;
3156 temp1.OCPolarity = sConfig->OCPolarity;
3157 temp1.OCNPolarity = sConfig->OCNPolarity;
3158 temp1.OCIdleState = sConfig->OCIdleState;
3159 temp1.OCNIdleState = sConfig->OCNIdleState;
3161 switch (OutputChannel)
3165 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3167 TIM_OC1_SetConfig(htim->Instance, &temp1);
3172 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3174 TIM_OC2_SetConfig(htim->Instance, &temp1);
3180 switch (InputChannel)
3184 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3186 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3187 sConfig->ICSelection, sConfig->ICFilter);
3189 /* Reset the IC1PSC Bits */
3190 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3192 /* Select the Trigger source */
3193 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3194 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3196 /* Select the Slave Mode */
3197 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3198 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3203 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3205 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3206 sConfig->ICSelection, sConfig->ICFilter);
3208 /* Reset the IC2PSC Bits */
3209 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3211 /* Select the Trigger source */
3212 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3213 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3215 /* Select the Slave Mode */
3216 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3217 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3225 htim->State = HAL_TIM_STATE_READY;
3238 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3239 * @param htim : TIM handle
3240 * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
3241 * This parameter can be one of the following values:
3242 * @arg TIM_DMABase_CR1
3243 * @arg TIM_DMABase_CR2
3244 * @arg TIM_DMABase_SMCR
3245 * @arg TIM_DMABase_DIER
3246 * @arg TIM_DMABase_SR
3247 * @arg TIM_DMABase_EGR
3248 * @arg TIM_DMABase_CCMR1
3249 * @arg TIM_DMABase_CCMR2
3250 * @arg TIM_DMABase_CCER
3251 * @arg TIM_DMABase_CNT
3252 * @arg TIM_DMABase_PSC
3253 * @arg TIM_DMABase_ARR
3254 * @arg TIM_DMABase_RCR
3255 * @arg TIM_DMABase_CCR1
3256 * @arg TIM_DMABase_CCR2
3257 * @arg TIM_DMABase_CCR3
3258 * @arg TIM_DMABase_CCR4
3259 * @arg TIM_DMABase_BDTR
3260 * @arg TIM_DMABase_DCR
3261 * @param BurstRequestSrc : TIM DMA Request sources
3262 * This parameter can be one of the following values:
3263 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3264 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3265 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3266 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3267 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3268 * @arg TIM_DMA_COM: TIM Commutation DMA source
3269 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3270 * @param BurstBuffer : The Buffer address.
3271 * @param BurstLength : DMA Burst length. This parameter can be one value
3272 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3273 * @retval HAL status
3275 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3276 uint32_t* BurstBuffer, uint32_t BurstLength)
3278 /* Check the parameters */
3279 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3280 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3281 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3282 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3284 if((htim->State == HAL_TIM_STATE_BUSY))
3288 else if((htim->State == HAL_TIM_STATE_READY))
3290 if((BurstBuffer == 0 ) && (BurstLength > 0))
3296 htim->State = HAL_TIM_STATE_BUSY;
3299 switch(BurstRequestSrc)
3301 case TIM_DMA_UPDATE:
3303 /* Set the DMA Period elapsed callback */
3304 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3306 /* Set the DMA error callback */
3307 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
3309 /* Enable the DMA channel */
3310 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3315 /* Set the DMA Period elapsed callback */
3316 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3318 /* Set the DMA error callback */
3319 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
3321 /* Enable the DMA channel */
3322 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3327 /* Set the DMA Period elapsed callback */
3328 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3330 /* Set the DMA error callback */
3331 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
3333 /* Enable the DMA channel */
3334 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3339 /* Set the DMA Period elapsed callback */
3340 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3342 /* Set the DMA error callback */
3343 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
3345 /* Enable the DMA channel */
3346 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3351 /* Set the DMA Period elapsed callback */
3352 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3354 /* Set the DMA error callback */
3355 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
3357 /* Enable the DMA channel */
3358 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3363 /* Set the DMA Period elapsed callback */
3364 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
3366 /* Set the DMA error callback */
3367 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
3369 /* Enable the DMA channel */
3370 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3373 case TIM_DMA_TRIGGER:
3375 /* Set the DMA Period elapsed callback */
3376 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3378 /* Set the DMA error callback */
3379 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
3381 /* Enable the DMA channel */
3382 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3388 /* configure the DMA Burst Mode */
3389 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3391 /* Enable the TIM DMA Request */
3392 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3394 htim->State = HAL_TIM_STATE_READY;
3396 /* Return function status */
3401 * @brief Stops the TIM DMA Burst mode
3402 * @param htim : TIM handle
3403 * @param BurstRequestSrc : TIM DMA Request sources to disable
3404 * @retval HAL status
3406 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3408 /* Check the parameters */
3409 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3411 /* Abort the DMA transfer (at least disable the DMA channel) */
3412 switch(BurstRequestSrc)
3414 case TIM_DMA_UPDATE:
3416 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3421 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3426 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3431 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3436 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3441 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3444 case TIM_DMA_TRIGGER:
3446 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3453 /* Disable the TIM Update DMA request */
3454 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3456 /* Return function status */
3461 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3462 * @param htim : TIM handle
3463 * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
3464 * This parameter can be one of the following values:
3465 * @arg TIM_DMABase_CR1
3466 * @arg TIM_DMABase_CR2
3467 * @arg TIM_DMABase_SMCR
3468 * @arg TIM_DMABase_DIER
3469 * @arg TIM_DMABase_SR
3470 * @arg TIM_DMABase_EGR
3471 * @arg TIM_DMABase_CCMR1
3472 * @arg TIM_DMABase_CCMR2
3473 * @arg TIM_DMABase_CCER
3474 * @arg TIM_DMABase_CNT
3475 * @arg TIM_DMABase_PSC
3476 * @arg TIM_DMABase_ARR
3477 * @arg TIM_DMABase_RCR
3478 * @arg TIM_DMABase_CCR1
3479 * @arg TIM_DMABase_CCR2
3480 * @arg TIM_DMABase_CCR3
3481 * @arg TIM_DMABase_CCR4
3482 * @arg TIM_DMABase_BDTR
3483 * @arg TIM_DMABase_DCR
3484 * @param BurstRequestSrc : TIM DMA Request sources
3485 * This parameter can be one of the following values:
3486 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3487 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3488 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3489 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3490 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3491 * @arg TIM_DMA_COM: TIM Commutation DMA source
3492 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3493 * @param BurstBuffer : The Buffer address.
3494 * @param BurstLength : DMA Burst length. This parameter can be one value
3495 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3496 * @retval HAL status
3498 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3499 uint32_t *BurstBuffer, uint32_t BurstLength)
3501 /* Check the parameters */
3502 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3503 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3504 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3505 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3507 if((htim->State == HAL_TIM_STATE_BUSY))
3511 else if((htim->State == HAL_TIM_STATE_READY))
3513 if((BurstBuffer == 0 ) && (BurstLength > 0))
3519 htim->State = HAL_TIM_STATE_BUSY;
3522 switch(BurstRequestSrc)
3524 case TIM_DMA_UPDATE:
3526 /* Set the DMA Period elapsed callback */
3527 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3529 /* Set the DMA error callback */
3530 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
3532 /* Enable the DMA channel */
3533 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3538 /* Set the DMA Period elapsed callback */
3539 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3541 /* Set the DMA error callback */
3542 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
3544 /* Enable the DMA channel */
3545 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3550 /* Set the DMA Period elapsed callback */
3551 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3553 /* Set the DMA error callback */
3554 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
3556 /* Enable the DMA channel */
3557 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3562 /* Set the DMA Period elapsed callback */
3563 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3565 /* Set the DMA error callback */
3566 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
3568 /* Enable the DMA channel */
3569 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3574 /* Set the DMA Period elapsed callback */
3575 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3577 /* Set the DMA error callback */
3578 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
3580 /* Enable the DMA channel */
3581 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3586 /* Set the DMA Period elapsed callback */
3587 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
3589 /* Set the DMA error callback */
3590 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
3592 /* Enable the DMA channel */
3593 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3596 case TIM_DMA_TRIGGER:
3598 /* Set the DMA Period elapsed callback */
3599 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3601 /* Set the DMA error callback */
3602 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
3604 /* Enable the DMA channel */
3605 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3612 /* configure the DMA Burst Mode */
3613 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3615 /* Enable the TIM DMA Request */
3616 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3618 htim->State = HAL_TIM_STATE_READY;
3620 /* Return function status */
3625 * @brief Stop the DMA burst reading
3626 * @param htim : TIM handle
3627 * @param BurstRequestSrc : TIM DMA Request sources to disable.
3628 * @retval HAL status
3630 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3632 /* Check the parameters */
3633 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3635 /* Abort the DMA transfer (at least disable the DMA channel) */
3636 switch(BurstRequestSrc)
3638 case TIM_DMA_UPDATE:
3640 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3645 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3650 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3655 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3660 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3665 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3668 case TIM_DMA_TRIGGER:
3670 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3677 /* Disable the TIM Update DMA request */
3678 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3680 /* Return function status */
3685 * @brief Generate a software event
3686 * @param htim : TIM handle
3687 * @param EventSource : specifies the event source.
3688 * This parameter can be one of the following values:
3689 * @arg TIM_EventSource_Update: Timer update Event source
3690 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
3691 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
3692 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
3693 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
3694 * @arg TIM_EventSource_COM: Timer COM event source
3695 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
3696 * @arg TIM_EventSource_Break: Timer Break event source
3697 * @note TIM6 and TIM7 can only generate an update event.
3698 * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1, TIM15, TIM16 and TIM17.
3699 * @retval HAL status
3702 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3704 /* Check the parameters */
3705 assert_param(IS_TIM_INSTANCE(htim->Instance));
3706 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3708 /* Process Locked */
3711 /* Change the TIM state */
3712 htim->State = HAL_TIM_STATE_BUSY;
3714 /* Set the event sources */
3715 htim->Instance->EGR = EventSource;
3717 /* Change the TIM state */
3718 htim->State = HAL_TIM_STATE_READY;
3722 /* Return function status */
3727 * @brief Configures the OCRef clear feature
3728 * @param htim : TIM handle
3729 * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
3730 * contains the OCREF clear feature and parameters for the TIM peripheral.
3731 * @param Channel : specifies the TIM Channel
3732 * This parameter can be one of the following values:
3733 * @arg TIM_Channel_1: TIM Channel 1
3734 * @arg TIM_Channel_2: TIM Channel 2
3735 * @arg TIM_Channel_3: TIM Channel 3
3736 * @arg TIM_Channel_4: TIM Channel 4
3737 * @retval HAL status
3739 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3741 uint32_t tmpsmcr = 0;
3743 /* Check the parameters */
3744 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
3745 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3746 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3747 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3748 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3750 /* Process Locked */
3753 htim->State = HAL_TIM_STATE_BUSY;
3755 switch (sClearInputConfig->ClearInputSource)
3757 case TIM_CLEARINPUTSOURCE_NONE:
3759 /* Clear the OCREF clear selection bit */
3760 tmpsmcr &= ~TIM_SMCR_OCCS;
3762 /* Clear the ETR Bits */
3763 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3766 htim->Instance->SMCR = tmpsmcr;
3770 case TIM_CLEARINPUTSOURCE_ETR:
3772 TIM_ETR_SetConfig(htim->Instance,
3773 sClearInputConfig->ClearInputPrescaler,
3774 sClearInputConfig->ClearInputPolarity,
3775 sClearInputConfig->ClearInputFilter);
3777 /* Set the OCREF clear selection bit */
3778 htim->Instance->SMCR |= TIM_SMCR_OCCS;
3789 if(sClearInputConfig->ClearInputState != RESET)
3791 /* Enable the Ocref clear feature for Channel 1 */
3792 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3796 /* Disable the Ocref clear feature for Channel 1 */
3797 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3803 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3804 if(sClearInputConfig->ClearInputState != RESET)
3806 /* Enable the Ocref clear feature for Channel 2 */
3807 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3811 /* Disable the Ocref clear feature for Channel 2 */
3812 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3818 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3819 if(sClearInputConfig->ClearInputState != RESET)
3821 /* Enable the Ocref clear feature for Channel 3 */
3822 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3826 /* Disable the Ocref clear feature for Channel 3 */
3827 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3833 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3834 if(sClearInputConfig->ClearInputState != RESET)
3836 /* Enable the Ocref clear feature for Channel 4 */
3837 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3841 /* Disable the Ocref clear feature for Channel 4 */
3842 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3850 htim->State = HAL_TIM_STATE_READY;
3858 * @brief Configures the clock source to be used
3859 * @param htim : TIM handle
3860 * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
3861 * contains the clock source information for the TIM peripheral.
3862 * @retval HAL status
3864 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3866 uint32_t tmpsmcr = 0;
3868 /* Process Locked */
3871 htim->State = HAL_TIM_STATE_BUSY;
3873 /* Check the parameters */
3874 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3875 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3876 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3877 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3879 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3880 tmpsmcr = htim->Instance->SMCR;
3881 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3882 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3883 htim->Instance->SMCR = tmpsmcr;
3885 switch (sClockSourceConfig->ClockSource)
3887 case TIM_CLOCKSOURCE_INTERNAL:
3889 assert_param(IS_TIM_INSTANCE(htim->Instance));
3890 /* Disable slave mode to clock the prescaler directly with the internal clock */
3891 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3895 case TIM_CLOCKSOURCE_ETRMODE1:
3897 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
3898 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
3900 /* Configure the ETR Clock source */
3901 TIM_ETR_SetConfig(htim->Instance,
3902 sClockSourceConfig->ClockPrescaler,
3903 sClockSourceConfig->ClockPolarity,
3904 sClockSourceConfig->ClockFilter);
3905 /* Get the TIMx SMCR register value */
3906 tmpsmcr = htim->Instance->SMCR;
3907 /* Reset the SMS and TS Bits */
3908 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3909 /* Select the External clock mode1 and the ETRF trigger */
3910 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3911 /* Write to TIMx SMCR */
3912 htim->Instance->SMCR = tmpsmcr;
3916 case TIM_CLOCKSOURCE_ETRMODE2:
3918 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
3919 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
3921 /* Configure the ETR Clock source */
3922 TIM_ETR_SetConfig(htim->Instance,
3923 sClockSourceConfig->ClockPrescaler,
3924 sClockSourceConfig->ClockPolarity,
3925 sClockSourceConfig->ClockFilter);
3926 /* Enable the External clock mode2 */
3927 htim->Instance->SMCR |= TIM_SMCR_ECE;
3931 case TIM_CLOCKSOURCE_TI1:
3933 /* Check whether or not the timer instance supports external clock mode 1 */
3934 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3936 TIM_TI1_ConfigInputStage(htim->Instance,
3937 sClockSourceConfig->ClockPolarity,
3938 sClockSourceConfig->ClockFilter);
3939 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
3942 case TIM_CLOCKSOURCE_TI2:
3944 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
3945 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3947 TIM_TI2_ConfigInputStage(htim->Instance,
3948 sClockSourceConfig->ClockPolarity,
3949 sClockSourceConfig->ClockFilter);
3950 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
3953 case TIM_CLOCKSOURCE_TI1ED:
3955 /* Check whether or not the timer instance supports external clock mode 1 */
3956 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3958 TIM_TI1_ConfigInputStage(htim->Instance,
3959 sClockSourceConfig->ClockPolarity,
3960 sClockSourceConfig->ClockFilter);
3961 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
3964 case TIM_CLOCKSOURCE_ITR0:
3966 /* Check whether or not the timer instance supports external clock mode 1 */
3967 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3969 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
3972 case TIM_CLOCKSOURCE_ITR1:
3974 /* Check whether or not the timer instance supports external clock mode 1 */
3975 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3977 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
3980 case TIM_CLOCKSOURCE_ITR2:
3982 /* Check whether or not the timer instance supports external clock mode 1 */
3983 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3985 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
3988 case TIM_CLOCKSOURCE_ITR3:
3990 /* Check whether or not the timer instance supports external clock mode 1 */
3991 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3993 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
4000 htim->State = HAL_TIM_STATE_READY;
4008 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4009 * or a XOR combination between CH1_input, CH2_input & CH3_input
4010 * @param htim : TIM handle.
4011 * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
4012 * output of a XOR gate.
4013 * This parameter can be one of the following values:
4014 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4015 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4016 * pins are connected to the TI1 input (XOR combination)
4017 * @retval HAL status
4019 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4021 uint32_t tmpcr2 = 0;
4023 /* Check the parameters */
4024 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4025 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4027 /* Get the TIMx CR2 register value */
4028 tmpcr2 = htim->Instance->CR2;
4030 /* Reset the TI1 selection */
4031 tmpcr2 &= ~TIM_CR2_TI1S;
4033 /* Set the the TI1 selection */
4034 tmpcr2 |= TI1_Selection;
4036 /* Write to TIMxCR2 */
4037 htim->Instance->CR2 = tmpcr2;
4043 * @brief Configures the TIM in Slave mode
4044 * @param htim : TIM handle.
4045 * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
4046 * contains the selected trigger (internal trigger input, filtered
4047 * timer input or external trigger input) and the ) and the Slave
4048 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4049 * @retval HAL status
4051 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
4053 /* Check the parameters */
4054 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4055 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4056 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4060 htim->State = HAL_TIM_STATE_BUSY;
4062 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4064 /* Disable Trigger Interrupt */
4065 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4067 /* Disable Trigger DMA request */
4068 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4070 htim->State = HAL_TIM_STATE_READY;
4078 * @brief Configures the TIM in Slave mode in interrupt mode
4079 * @param htim: TIM handle.
4080 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4081 * contains the selected trigger (internal trigger input, filtered
4082 * timer input or external trigger input) and the ) and the Slave
4083 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4084 * @retval HAL status
4086 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
4087 TIM_SlaveConfigTypeDef * sSlaveConfig)
4089 /* Check the parameters */
4090 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4091 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4092 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4096 htim->State = HAL_TIM_STATE_BUSY;
4098 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4100 /* Enable Trigger Interrupt */
4101 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4103 /* Disable Trigger DMA request */
4104 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4106 htim->State = HAL_TIM_STATE_READY;
4114 * @brief Read the captured value from Capture Compare unit
4115 * @param htim : TIM handle.
4116 * @param Channel : TIM Channels to be enabled
4117 * This parameter can be one of the following values:
4118 * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
4119 * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
4120 * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
4121 * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
4122 * @retval Captured value
4124 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4126 uint32_t tmpreg = 0;
4134 /* Check the parameters */
4135 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4137 /* Return the capture 1 value */
4138 tmpreg = htim->Instance->CCR1;
4144 /* Check the parameters */
4145 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4147 /* Return the capture 2 value */
4148 tmpreg = htim->Instance->CCR2;
4155 /* Check the parameters */
4156 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4158 /* Return the capture 3 value */
4159 tmpreg = htim->Instance->CCR3;
4166 /* Check the parameters */
4167 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4169 /* Return the capture 4 value */
4170 tmpreg = htim->Instance->CCR4;
4187 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4188 * @brief TIM Callbacks functions
4191 ==============================================================================
4192 ##### TIM Callbacks functions #####
4193 ==============================================================================
4195 This section provides TIM callback functions:
4196 (+) Timer Period elapsed callback
4197 (+) Timer Output Compare callback
4198 (+) Timer Input capture callback
4199 (+) Timer Trigger callback
4200 (+) Timer Error callback
4207 * @brief Period elapsed callback in non blocking mode
4208 * @param htim : TIM handle
4211 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4213 /* NOTE : This function Should not be modified, when the callback is needed,
4214 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4219 * @brief Output Compare callback in non blocking mode
4220 * @param htim : TIM OC handle
4223 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4225 /* NOTE : This function Should not be modified, when the callback is needed,
4226 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4230 * @brief Input Capture callback in non blocking mode
4231 * @param htim : TIM IC handle
4234 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4236 /* NOTE : This function Should not be modified, when the callback is needed,
4237 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4242 * @brief PWM Pulse finished callback in non blocking mode
4243 * @param htim : TIM handle
4246 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4248 /* NOTE : This function Should not be modified, when the callback is needed,
4249 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4254 * @brief Hall Trigger detection callback in non blocking mode
4255 * @param htim : TIM handle
4258 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4260 /* NOTE : This function Should not be modified, when the callback is needed,
4261 the HAL_TIM_TriggerCallback could be implemented in the user file
4266 * @brief Timer error callback in non blocking mode
4267 * @param htim : TIM handle
4270 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4272 /* NOTE : This function Should not be modified, when the callback is needed,
4273 the HAL_TIM_ErrorCallback could be implemented in the user file
4281 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4282 * @brief Peripheral State functions
4285 ==============================================================================
4286 ##### Peripheral State functions #####
4287 ==============================================================================
4289 This subsection permit to get in run-time the status of the peripheral
4297 * @brief Return the TIM Base state
4298 * @param htim : TIM Base handle
4301 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4307 * @brief Return the TIM OC state
4308 * @param htim : TIM Ouput Compare handle
4311 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4317 * @brief Return the TIM PWM state
4318 * @param htim : TIM handle
4321 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4327 * @brief Return the TIM Input Capture state
4328 * @param htim : TIM IC handle
4331 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4337 * @brief Return the TIM One Pulse Mode state
4338 * @param htim : TIM OPM handle
4341 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4347 * @brief Return the TIM Encoder Mode state
4348 * @param htim : TIM Encoder handle
4351 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4364 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
4369 * @brief TIM DMA error callback
4370 * @param hdma : pointer to DMA handle.
4373 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
4375 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4377 htim->State= HAL_TIM_STATE_READY;
4379 HAL_TIM_ErrorCallback(htim);
4383 * @brief TIM DMA Delay Pulse complete callback.
4384 * @param hdma : pointer to DMA handle.
4387 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4389 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4391 htim->State= HAL_TIM_STATE_READY;
4393 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4395 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4397 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4399 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4401 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4403 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4405 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4407 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4410 HAL_TIM_PWM_PulseFinishedCallback(htim);
4412 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4415 * @brief TIM DMA Capture complete callback.
4416 * @param hdma : pointer to DMA handle.
4419 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4421 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4423 htim->State= HAL_TIM_STATE_READY;
4425 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4427 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4429 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4431 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4433 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4435 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4437 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4439 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4442 HAL_TIM_IC_CaptureCallback(htim);
4444 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4448 * @brief TIM DMA Period Elapse complete callback.
4449 * @param hdma : pointer to DMA handle.
4452 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4454 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4456 htim->State= HAL_TIM_STATE_READY;
4458 HAL_TIM_PeriodElapsedCallback(htim);
4462 * @brief TIM DMA Trigger callback.
4463 * @param hdma : pointer to DMA handle.
4466 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4468 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4470 htim->State= HAL_TIM_STATE_READY;
4472 HAL_TIM_TriggerCallback(htim);
4476 * @brief Time Base configuration
4477 * @param TIMx : TIM periheral
4478 * @param Structure : TIM Base configuration structure
4481 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4483 uint32_t tmpcr1 = 0;
4486 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4487 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
4489 /* Select the Counter Mode */
4490 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4491 tmpcr1 |= Structure->CounterMode;
4494 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
4496 /* Set the clock division */
4497 tmpcr1 &= ~TIM_CR1_CKD;
4498 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4503 /* Set the Autoreload value */
4504 TIMx->ARR = (uint32_t)Structure->Period ;
4506 /* Set the Prescaler value */
4507 TIMx->PSC = (uint32_t)Structure->Prescaler;
4509 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
4511 /* Set the Repetition Counter value */
4512 TIMx->RCR = Structure->RepetitionCounter;
4515 /* Generate an update event to reload the Prescaler
4516 and the repetition counter(only for TIM1 and TIM8) value immediatly */
4517 TIMx->EGR = TIM_EGR_UG;
4521 * @brief Time Ouput Compare 1 configuration
4522 * @param TIMx to select the TIM peripheral
4523 * @param OC_Config : The ouput configuration structure
4526 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4528 uint32_t tmpccmrx = 0;
4529 uint32_t tmpccer = 0;
4530 uint32_t tmpcr2 = 0;
4532 /* Disable the Channel 1: Reset the CC1E Bit */
4533 TIMx->CCER &= ~TIM_CCER_CC1E;
4535 /* Get the TIMx CCER register value */
4536 tmpccer = TIMx->CCER;
4537 /* Get the TIMx CR2 register value */
4540 /* Get the TIMx CCMR1 register value */
4541 tmpccmrx = TIMx->CCMR1;
4543 /* Reset the Output Compare Mode Bits */
4544 tmpccmrx &= ~TIM_CCMR1_OC1M;
4545 tmpccmrx &= ~TIM_CCMR1_CC1S;
4546 /* Select the Output Compare Mode */
4547 tmpccmrx |= OC_Config->OCMode;
4549 /* Reset the Output Polarity level */
4550 tmpccer &= ~TIM_CCER_CC1P;
4551 /* Set the Output Compare Polarity */
4552 tmpccer |= OC_Config->OCPolarity;
4554 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
4556 /* Check parameters */
4557 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4559 /* Reset the Output N Polarity level */
4560 tmpccer &= ~TIM_CCER_CC1NP;
4561 /* Set the Output N Polarity */
4562 tmpccer |= OC_Config->OCNPolarity;
4563 /* Reset the Output N State */
4564 tmpccer &= ~TIM_CCER_CC1NE;
4567 if(IS_TIM_BREAK_INSTANCE(TIMx))
4569 /* Check parameters */
4570 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4571 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4573 /* Reset the Output Compare and Output Compare N IDLE State */
4574 tmpcr2 &= ~TIM_CR2_OIS1;
4575 tmpcr2 &= ~TIM_CR2_OIS1N;
4576 /* Set the Output Idle state */
4577 tmpcr2 |= OC_Config->OCIdleState;
4578 /* Set the Output N Idle state */
4579 tmpcr2 |= OC_Config->OCNIdleState;
4581 /* Write to TIMx CR2 */
4584 /* Write to TIMx CCMR1 */
4585 TIMx->CCMR1 = tmpccmrx;
4587 /* Set the Capture Compare Register value */
4588 TIMx->CCR1 = OC_Config->Pulse;
4590 /* Write to TIMx CCER */
4591 TIMx->CCER = tmpccer;
4595 * @brief Time Ouput Compare 2 configuration
4596 * @param TIMx to select the TIM peripheral
4597 * @param OC_Config : The ouput configuration structure
4600 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4602 uint32_t tmpccmrx = 0;
4603 uint32_t tmpccer = 0;
4604 uint32_t tmpcr2 = 0;
4606 /* Disable the Channel 2: Reset the CC2E Bit */
4607 TIMx->CCER &= ~TIM_CCER_CC2E;
4609 /* Get the TIMx CCER register value */
4610 tmpccer = TIMx->CCER;
4611 /* Get the TIMx CR2 register value */
4614 /* Get the TIMx CCMR1 register value */
4615 tmpccmrx = TIMx->CCMR1;
4617 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4618 tmpccmrx &= ~TIM_CCMR1_OC2M;
4619 tmpccmrx &= ~TIM_CCMR1_CC2S;
4621 /* Select the Output Compare Mode */
4622 tmpccmrx |= (OC_Config->OCMode << 8);
4624 /* Reset the Output Polarity level */
4625 tmpccer &= ~TIM_CCER_CC2P;
4626 /* Set the Output Compare Polarity */
4627 tmpccer |= (OC_Config->OCPolarity << 4);
4629 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
4631 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4632 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4633 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4635 /* Reset the Output N Polarity level */
4636 tmpccer &= ~TIM_CCER_CC2NP;
4637 /* Set the Output N Polarity */
4638 tmpccer |= (OC_Config->OCNPolarity << 4);
4639 /* Reset the Output N State */
4640 tmpccer &= ~TIM_CCER_CC2NE;
4644 if(IS_TIM_BREAK_INSTANCE(TIMx))
4646 /* Check parameters */
4647 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4648 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4650 /* Reset the Output Compare and Output Compare N IDLE State */
4651 tmpcr2 &= ~TIM_CR2_OIS2;
4652 tmpcr2 &= ~TIM_CR2_OIS2N;
4653 /* Set the Output Idle state */
4654 tmpcr2 |= (OC_Config->OCIdleState << 2);
4655 /* Set the Output N Idle state */
4656 tmpcr2 |= (OC_Config->OCNIdleState << 2);
4659 /* Write to TIMx CR2 */
4662 /* Write to TIMx CCMR1 */
4663 TIMx->CCMR1 = tmpccmrx;
4665 /* Set the Capture Compare Register value */
4666 TIMx->CCR2 = OC_Config->Pulse;
4668 /* Write to TIMx CCER */
4669 TIMx->CCER = tmpccer;
4673 * @brief Time Ouput Compare 3 configuration
4674 * @param TIMx to select the TIM peripheral
4675 * @param OC_Config : The ouput configuration structure
4678 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4680 uint32_t tmpccmrx = 0;
4681 uint32_t tmpccer = 0;
4682 uint32_t tmpcr2 = 0;
4684 /* Disable the Channel 3: Reset the CC2E Bit */
4685 TIMx->CCER &= ~TIM_CCER_CC3E;
4687 /* Get the TIMx CCER register value */
4688 tmpccer = TIMx->CCER;
4689 /* Get the TIMx CR2 register value */
4692 /* Get the TIMx CCMR2 register value */
4693 tmpccmrx = TIMx->CCMR2;
4695 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4696 tmpccmrx &= ~TIM_CCMR2_OC3M;
4697 tmpccmrx &= ~TIM_CCMR2_CC3S;
4698 /* Select the Output Compare Mode */
4699 tmpccmrx |= OC_Config->OCMode;
4701 /* Reset the Output Polarity level */
4702 tmpccer &= ~TIM_CCER_CC3P;
4703 /* Set the Output Compare Polarity */
4704 tmpccer |= (OC_Config->OCPolarity << 8);
4706 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
4708 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4709 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4710 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4712 /* Reset the Output N Polarity level */
4713 tmpccer &= ~TIM_CCER_CC3NP;
4714 /* Set the Output N Polarity */
4715 tmpccer |= (OC_Config->OCNPolarity << 8);
4716 /* Reset the Output N State */
4717 tmpccer &= ~TIM_CCER_CC3NE;
4720 if(IS_TIM_BREAK_INSTANCE(TIMx))
4722 /* Check parameters */
4723 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4724 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4726 /* Reset the Output Compare and Output Compare N IDLE State */
4727 tmpcr2 &= ~TIM_CR2_OIS3;
4728 tmpcr2 &= ~TIM_CR2_OIS3N;
4729 /* Set the Output Idle state */
4730 tmpcr2 |= (OC_Config->OCIdleState << 4);
4731 /* Set the Output N Idle state */
4732 tmpcr2 |= (OC_Config->OCNIdleState << 4);
4735 /* Write to TIMx CR2 */
4738 /* Write to TIMx CCMR2 */
4739 TIMx->CCMR2 = tmpccmrx;
4741 /* Set the Capture Compare Register value */
4742 TIMx->CCR3 = OC_Config->Pulse;
4744 /* Write to TIMx CCER */
4745 TIMx->CCER = tmpccer;
4749 * @brief Time Ouput Compare 4 configuration
4750 * @param TIMx to select the TIM peripheral
4751 * @param OC_Config : The ouput configuration structure
4754 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4756 uint32_t tmpccmrx = 0;
4757 uint32_t tmpccer = 0;
4758 uint32_t tmpcr2 = 0;
4760 /* Disable the Channel 4: Reset the CC4E Bit */
4761 TIMx->CCER &= ~TIM_CCER_CC4E;
4763 /* Get the TIMx CCER register value */
4764 tmpccer = TIMx->CCER;
4765 /* Get the TIMx CR2 register value */
4768 /* Get the TIMx CCMR2 register value */
4769 tmpccmrx = TIMx->CCMR2;
4771 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4772 tmpccmrx &= ~TIM_CCMR2_OC4M;
4773 tmpccmrx &= ~TIM_CCMR2_CC4S;
4775 /* Select the Output Compare Mode */
4776 tmpccmrx |= (OC_Config->OCMode << 8);
4778 /* Reset the Output Polarity level */
4779 tmpccer &= ~TIM_CCER_CC4P;
4780 /* Set the Output Compare Polarity */
4781 tmpccer |= (OC_Config->OCPolarity << 12);
4783 if(IS_TIM_BREAK_INSTANCE(TIMx))
4785 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4787 /* Reset the Output Compare IDLE State */
4788 tmpcr2 &= ~TIM_CR2_OIS4;
4789 /* Set the Output Idle state */
4790 tmpcr2 |= (OC_Config->OCIdleState << 6);
4793 /* Write to TIMx CR2 */
4796 /* Write to TIMx CCMR2 */
4797 TIMx->CCMR2 = tmpccmrx;
4799 /* Set the Capture Compare Register value */
4800 TIMx->CCR4 = OC_Config->Pulse;
4802 /* Write to TIMx CCER */
4803 TIMx->CCER = tmpccer;
4806 void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
4807 TIM_SlaveConfigTypeDef * sSlaveConfig)
4809 uint32_t tmpsmcr = 0;
4810 uint32_t tmpccmr1 = 0;
4811 uint32_t tmpccer = 0;
4813 /* Get the TIMx SMCR register value */
4814 tmpsmcr = htim->Instance->SMCR;
4816 /* Reset the Trigger Selection Bits */
4817 tmpsmcr &= ~TIM_SMCR_TS;
4818 /* Set the Input Trigger source */
4819 tmpsmcr |= sSlaveConfig->InputTrigger;
4821 /* Reset the slave mode Bits */
4822 tmpsmcr &= ~TIM_SMCR_SMS;
4823 /* Set the slave mode */
4824 tmpsmcr |= sSlaveConfig->SlaveMode;
4826 /* Write to TIMx SMCR */
4827 htim->Instance->SMCR = tmpsmcr;
4829 /* Configure the trigger prescaler, filter, and polarity */
4830 switch (sSlaveConfig->InputTrigger)
4834 /* Check the parameters */
4835 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4836 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
4837 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4838 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4839 /* Configure the ETR Trigger source */
4840 TIM_ETR_SetConfig(htim->Instance,
4841 sSlaveConfig->TriggerPrescaler,
4842 sSlaveConfig->TriggerPolarity,
4843 sSlaveConfig->TriggerFilter);
4847 case TIM_TS_TI1F_ED:
4849 /* Check the parameters */
4850 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4851 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4852 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4854 /* Disable the Channel 1: Reset the CC1E Bit */
4855 tmpccer = htim->Instance->CCER;
4856 htim->Instance->CCER &= ~TIM_CCER_CC1E;
4857 tmpccmr1 = htim->Instance->CCMR1;
4859 /* Set the filter */
4860 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4861 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
4863 /* Write to TIMx CCMR1 and CCER registers */
4864 htim->Instance->CCMR1 = tmpccmr1;
4865 htim->Instance->CCER = tmpccer;
4872 /* Check the parameters */
4873 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4874 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4875 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4877 /* Configure TI1 Filter and Polarity */
4878 TIM_TI1_ConfigInputStage(htim->Instance,
4879 sSlaveConfig->TriggerPolarity,
4880 sSlaveConfig->TriggerFilter);
4886 /* Check the parameters */
4887 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4888 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4889 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4891 /* Configure TI2 Filter and Polarity */
4892 TIM_TI2_ConfigInputStage(htim->Instance,
4893 sSlaveConfig->TriggerPolarity,
4894 sSlaveConfig->TriggerFilter);
4900 /* Check the parameter */
4901 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4907 /* Check the parameter */
4908 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4914 /* Check the parameter */
4915 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4921 /* Check the parameter */
4922 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4932 * @brief Configure the TI1 as Input.
4933 * @param TIMx to select the TIM peripheral.
4934 * @param TIM_ICPolarity : The Input Polarity.
4935 * This parameter can be one of the following values:
4936 * @arg TIM_ICPolarity_Rising
4937 * @arg TIM_ICPolarity_Falling
4938 * @arg TIM_ICPolarity_BothEdge
4939 * @param TIM_ICSelection : specifies the input to be used.
4940 * This parameter can be one of the following values:
4941 * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1.
4942 * @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2.
4943 * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC.
4944 * @param TIM_ICFilter : Specifies the Input Capture Filter.
4945 * This parameter must be a value between 0x00 and 0x0F.
4947 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
4948 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
4949 * protected against un-initialized filter and polarity values.
4951 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4952 uint32_t TIM_ICFilter)
4954 uint32_t tmpccmr1 = 0;
4955 uint32_t tmpccer = 0;
4957 /* Disable the Channel 1: Reset the CC1E Bit */
4958 TIMx->CCER &= ~TIM_CCER_CC1E;
4959 tmpccmr1 = TIMx->CCMR1;
4960 tmpccer = TIMx->CCER;
4962 /* Select the Input */
4963 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4965 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4966 tmpccmr1 |= TIM_ICSelection;
4970 tmpccmr1 |= TIM_CCMR1_CC1S_0;
4973 /* Set the filter */
4974 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4975 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
4977 /* Select the Polarity and set the CC1E Bit */
4978 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4979 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
4981 /* Write to TIMx CCMR1 and CCER registers */
4982 TIMx->CCMR1 = tmpccmr1;
4983 TIMx->CCER = tmpccer;
4987 * @brief Configure the Polarity and Filter for TI1.
4988 * @param TIMx to select the TIM peripheral.
4989 * @param TIM_ICPolarity : The Input Polarity.
4990 * This parameter can be one of the following values:
4991 * @arg TIM_ICPolarity_Rising
4992 * @arg TIM_ICPolarity_Falling
4993 * @arg TIM_ICPolarity_BothEdge
4994 * @param TIM_ICFilter : Specifies the Input Capture Filter.
4995 * This parameter must be a value between 0x00 and 0x0F.
4998 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5000 uint32_t tmpccmr1 = 0;
5001 uint32_t tmpccer = 0;
5003 /* Disable the Channel 1: Reset the CC1E Bit */
5004 tmpccer = TIMx->CCER;
5005 TIMx->CCER &= ~TIM_CCER_CC1E;
5006 tmpccmr1 = TIMx->CCMR1;
5008 /* Set the filter */
5009 tmpccmr1 &= ~TIM_CCMR1_IC1F;
5010 tmpccmr1 |= (TIM_ICFilter << 4);
5012 /* Select the Polarity and set the CC1E Bit */
5013 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
5014 tmpccer |= TIM_ICPolarity;
5016 /* Write to TIMx CCMR1 and CCER registers */
5017 TIMx->CCMR1 = tmpccmr1;
5018 TIMx->CCER = tmpccer;
5022 * @brief Configure the TI2 as Input.
5023 * @param TIMx to select the TIM peripheral
5024 * @param TIM_ICPolarity : The Input Polarity.
5025 * This parameter can be one of the following values:
5026 * @arg TIM_ICPolarity_Rising
5027 * @arg TIM_ICPolarity_Falling
5028 * @arg TIM_ICPolarity_BothEdge
5029 * @param TIM_ICSelection : specifies the input to be used.
5030 * This parameter can be one of the following values:
5031 * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2.
5032 * @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1.
5033 * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC.
5034 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5035 * This parameter must be a value between 0x00 and 0x0F.
5037 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
5038 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
5039 * protected against un-initialized filter and polarity values.
5041 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5042 uint32_t TIM_ICFilter)
5044 uint32_t tmpccmr1 = 0;
5045 uint32_t tmpccer = 0;
5047 /* Disable the Channel 2: Reset the CC2E Bit */
5048 TIMx->CCER &= ~TIM_CCER_CC2E;
5049 tmpccmr1 = TIMx->CCMR1;
5050 tmpccer = TIMx->CCER;
5052 /* Select the Input */
5053 tmpccmr1 &= ~TIM_CCMR1_CC2S;
5054 tmpccmr1 |= (TIM_ICSelection << 8);
5056 /* Set the filter */
5057 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5058 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
5060 /* Select the Polarity and set the CC2E Bit */
5061 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5062 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
5064 /* Write to TIMx CCMR1 and CCER registers */
5065 TIMx->CCMR1 = tmpccmr1 ;
5066 TIMx->CCER = tmpccer;
5070 * @brief Configure the Polarity and Filter for TI2.
5071 * @param TIMx to select the TIM peripheral.
5072 * @param TIM_ICPolarity : The Input Polarity.
5073 * This parameter can be one of the following values:
5074 * @arg TIM_ICPolarity_Rising
5075 * @arg TIM_ICPolarity_Falling
5076 * @arg TIM_ICPolarity_BothEdge
5077 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5078 * This parameter must be a value between 0x00 and 0x0F.
5081 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5083 uint32_t tmpccmr1 = 0;
5084 uint32_t tmpccer = 0;
5086 /* Disable the Channel 2: Reset the CC2E Bit */
5087 TIMx->CCER &= ~TIM_CCER_CC2E;
5088 tmpccmr1 = TIMx->CCMR1;
5089 tmpccer = TIMx->CCER;
5091 /* Set the filter */
5092 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5093 tmpccmr1 |= (TIM_ICFilter << 12);
5095 /* Select the Polarity and set the CC2E Bit */
5096 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5097 tmpccer |= (TIM_ICPolarity << 4);
5099 /* Write to TIMx CCMR1 and CCER registers */
5100 TIMx->CCMR1 = tmpccmr1 ;
5101 TIMx->CCER = tmpccer;
5105 * @brief Configure the TI3 as Input.
5106 * @param TIMx to select the TIM peripheral
5107 * @param TIM_ICPolarity : The Input Polarity.
5108 * This parameter can be one of the following values:
5109 * @arg TIM_ICPolarity_Rising
5110 * @arg TIM_ICPolarity_Falling
5111 * @arg TIM_ICPolarity_BothEdge
5112 * @param TIM_ICSelection : specifies the input to be used.
5113 * This parameter can be one of the following values:
5114 * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3.
5115 * @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4.
5116 * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC.
5117 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5118 * This parameter must be a value between 0x00 and 0x0F.
5120 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
5121 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5122 * protected against un-initialized filter and polarity values.
5124 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5125 uint32_t TIM_ICFilter)
5127 uint32_t tmpccmr2 = 0;
5128 uint32_t tmpccer = 0;
5130 /* Disable the Channel 3: Reset the CC3E Bit */
5131 TIMx->CCER &= ~TIM_CCER_CC3E;
5132 tmpccmr2 = TIMx->CCMR2;
5133 tmpccer = TIMx->CCER;
5135 /* Select the Input */
5136 tmpccmr2 &= ~TIM_CCMR2_CC3S;
5137 tmpccmr2 |= TIM_ICSelection;
5139 /* Set the filter */
5140 tmpccmr2 &= ~TIM_CCMR2_IC3F;
5141 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
5143 /* Select the Polarity and set the CC3E Bit */
5144 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
5145 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
5147 /* Write to TIMx CCMR2 and CCER registers */
5148 TIMx->CCMR2 = tmpccmr2;
5149 TIMx->CCER = tmpccer;
5153 * @brief Configure the TI4 as Input.
5154 * @param TIMx to select the TIM peripheral
5155 * @param TIM_ICPolarity : The Input Polarity.
5156 * This parameter can be one of the following values:
5157 * @arg TIM_ICPolarity_Rising
5158 * @arg TIM_ICPolarity_Falling
5159 * @arg TIM_ICPolarity_BothEdge
5160 * @param TIM_ICSelection : specifies the input to be used.
5161 * This parameter can be one of the following values:
5162 * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4.
5163 * @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3.
5164 * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC.
5165 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5166 * This parameter must be a value between 0x00 and 0x0F.
5167 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
5168 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5169 * protected against un-initialized filter and polarity values.
5172 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5173 uint32_t TIM_ICFilter)
5175 uint32_t tmpccmr2 = 0;
5176 uint32_t tmpccer = 0;
5178 /* Disable the Channel 4: Reset the CC4E Bit */
5179 TIMx->CCER &= ~TIM_CCER_CC4E;
5180 tmpccmr2 = TIMx->CCMR2;
5181 tmpccer = TIMx->CCER;
5183 /* Select the Input */
5184 tmpccmr2 &= ~TIM_CCMR2_CC4S;
5185 tmpccmr2 |= (TIM_ICSelection << 8);
5187 /* Set the filter */
5188 tmpccmr2 &= ~TIM_CCMR2_IC4F;
5189 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
5191 /* Select the Polarity and set the CC4E Bit */
5192 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
5193 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
5195 /* Write to TIMx CCMR2 and CCER registers */
5196 TIMx->CCMR2 = tmpccmr2;
5197 TIMx->CCER = tmpccer ;
5201 * @brief Selects the Input Trigger source
5202 * @param TIMx to select the TIM peripheral
5203 * @param InputTriggerSource : The Input Trigger source.
5204 * This parameter can be one of the following values:
5205 * @arg TIM_TS_ITR0 : Internal Trigger 0
5206 * @arg TIM_TS_ITR1 : Internal Trigger 1
5207 * @arg TIM_TS_ITR2 : Internal Trigger 2
5208 * @arg TIM_TS_ITR3 : Internal Trigger 3
5209 * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
5210 * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
5211 * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
5212 * @arg TIM_TS_ETRF : External Trigger input
5215 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
5217 uint32_t tmpsmcr = 0;
5219 /* Get the TIMx SMCR register value */
5220 tmpsmcr = TIMx->SMCR;
5221 /* Reset the TS Bits */
5222 tmpsmcr &= ~TIM_SMCR_TS;
5223 /* Set the Input Trigger source and the slave mode*/
5224 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
5225 /* Write to TIMx SMCR */
5226 TIMx->SMCR = tmpsmcr;
5229 * @brief Configures the TIMx External Trigger (ETR).
5230 * @param TIMx to select the TIM peripheral
5231 * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
5232 * This parameter can be one of the following values:
5233 * @arg TIM_ExtTRGPSC_DIV1 : ETRP Prescaler OFF.
5234 * @arg TIM_ExtTRGPSC_DIV2 : ETRP frequency divided by 2.
5235 * @arg TIM_ExtTRGPSC_DIV4 : ETRP frequency divided by 4.
5236 * @arg TIM_ExtTRGPSC_DIV8 : ETRP frequency divided by 8.
5237 * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
5238 * This parameter can be one of the following values:
5239 * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active.
5240 * @arg TIM_ExtTRGPolarity_NonInverted : active high or rising edge active.
5241 * @param ExtTRGFilter : External Trigger Filter.
5242 * This parameter must be a value between 0x00 and 0x0F
5245 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
5246 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
5248 uint32_t tmpsmcr = 0;
5250 tmpsmcr = TIMx->SMCR;
5252 /* Reset the ETR Bits */
5253 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5255 /* Set the Prescaler, the Filter value and the Polarity */
5256 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
5258 /* Write to TIMx SMCR */
5259 TIMx->SMCR = tmpsmcr;
5263 * @brief Enables or disables the TIM Capture Compare Channel x.
5264 * @param TIMx to select the TIM peripheral
5265 * @param Channel : specifies the TIM Channel
5266 * This parameter can be one of the following values:
5267 * @arg TIM_Channel_1 : TIM Channel 1
5268 * @arg TIM_Channel_2 : TIM Channel 2
5269 * @arg TIM_Channel_3 : TIM Channel 3
5270 * @arg TIM_Channel_4 : TIM Channel 4
5271 * @param ChannelState : specifies the TIM Channel CCxE bit new state.
5272 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5275 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
5279 /* Check the parameters */
5280 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
5281 assert_param(IS_TIM_CHANNELS(Channel));
5283 tmp = TIM_CCER_CC1E << Channel;
5285 /* Reset the CCxE Bit */
5288 /* Set or reset the CCxE Bit */
5289 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
5297 #endif /* HAL_TIM_MODULE_ENABLED */
5305 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/