2 ******************************************************************************
4 * @author MCD Application Team
7 * @brief CMSIS STM32F302x6/STM32F302x8 Devices Peripheral Access Layer Header File.
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral
\92s registers hardware
14 ******************************************************************************
17 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 ******************************************************************************
44 /** @addtogroup CMSIS_Device
48 /** @addtogroup stm32f302x8
52 #ifndef __STM32F302x8_H
53 #define __STM32F302x8_H
57 #endif /* __cplusplus */
59 /** @addtogroup Configuration_section_for_CMSIS
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
67 #define __MPU_PRESENT 0 /*!< STM32F302x6/STM32F302x8 devices do not provide an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32F302x6/STM32F302x8 devices use 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< STM32F302x6/STM32F302x8 devices provide an FPU */
76 /** @addtogroup Peripheral_interrupt_number_definition
81 * @brief STM32F302x6/STM32F302x8 device Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
101 RCC_IRQn = 5, /*!< RCC global Interrupt */
102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
114 ADC1_IRQn = 18, /*!< ADC1 Interrupts */
115 USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
116 USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
130 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
131 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
132 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
133 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
134 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
135 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
136 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
137 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */
138 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
139 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
140 I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
141 I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
142 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
143 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
144 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
145 FPU_IRQn = 81 /*!< Floating point Interrupt */
152 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
153 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
156 /** @addtogroup Peripheral_registers_structures
161 * @brief Analog to Digital Converter
166 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
167 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
168 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
169 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
170 uint32_t RESERVED0; /*!< Reserved, 0x010 */
171 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
172 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
173 uint32_t RESERVED1; /*!< Reserved, 0x01C */
174 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
175 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
176 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
177 uint32_t RESERVED2; /*!< Reserved, 0x02C */
178 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
179 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
180 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
181 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
182 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
183 uint32_t RESERVED3; /*!< Reserved, 0x044 */
184 uint32_t RESERVED4; /*!< Reserved, 0x048 */
185 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
186 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
187 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
188 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
189 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
190 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
191 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
192 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
193 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
194 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
195 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
196 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
197 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
198 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
199 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
200 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
201 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
202 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
208 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
209 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
210 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
211 __IO uint32_t CDR; /*!< ADC common regular data register for dual
212 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
213 } ADC_Common_TypeDef;
216 * @brief Controller Area Network TxMailBox
220 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
221 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
222 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
223 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
224 } CAN_TxMailBox_TypeDef;
227 * @brief Controller Area Network FIFOMailBox
231 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
232 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
233 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
234 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
235 } CAN_FIFOMailBox_TypeDef;
238 * @brief Controller Area Network FilterRegister
242 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
243 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
244 } CAN_FilterRegister_TypeDef;
247 * @brief Controller Area Network
251 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
252 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
253 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
254 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
255 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
256 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
257 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
258 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
259 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
260 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
261 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
262 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
263 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
264 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
265 uint32_t RESERVED2; /*!< Reserved, 0x208 */
266 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
267 uint32_t RESERVED3; /*!< Reserved, 0x210 */
268 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
269 uint32_t RESERVED4; /*!< Reserved, 0x218 */
270 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
271 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
272 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
276 * @brief Analog Comparators
281 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
285 * @brief CRC calculation unit
290 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
291 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
292 uint8_t RESERVED0; /*!< Reserved, 0x05 */
293 uint16_t RESERVED1; /*!< Reserved, 0x06 */
294 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
295 uint32_t RESERVED2; /*!< Reserved, 0x0C */
296 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
297 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
301 * @brief Digital to Analog Converter
306 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
307 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
308 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
309 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
310 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
311 __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
312 __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
313 __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
314 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
315 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
316 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
317 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
318 __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
319 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
328 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
329 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
330 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
331 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
335 * @brief DMA Controller
340 __IO uint32_t CCR; /*!< DMA channel x configuration register */
341 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
342 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
343 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
344 } DMA_Channel_TypeDef;
348 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
349 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
353 * @brief External Interrupt/Event Controller
358 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
359 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
360 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
361 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
362 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
363 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
364 uint32_t RESERVED1; /*!< Reserved, 0x18 */
365 uint32_t RESERVED2; /*!< Reserved, 0x1C */
366 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
367 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
368 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
369 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
370 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
371 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
375 * @brief FLASH Registers
380 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
381 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
382 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
383 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
384 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
385 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
386 uint32_t RESERVED; /*!< Reserved, 0x18 */
387 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
388 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
393 * @brief Option Bytes Registers
397 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
398 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
399 uint16_t RESERVED0; /*!< Reserved, 0x04 */
400 uint16_t RESERVED1; /*!< Reserved, 0x06 */
401 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
402 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
403 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
404 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
408 * @brief General Purpose I/O
413 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
414 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
415 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
416 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
417 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
418 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
419 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
420 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
421 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
422 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
423 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
427 * @brief Operational Amplifier (OPAMP)
432 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
436 * @brief System configuration controller
441 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
442 __IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
443 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
444 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
448 * @brief Inter-integrated Circuit Interface
453 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
454 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
455 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
456 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
457 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
458 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
459 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
460 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
461 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
462 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
463 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
467 * @brief Independent WATCHDOG
472 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
473 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
474 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
475 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
476 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
480 * @brief Power Control
485 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
486 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
490 * @brief Reset and Clock Control
494 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
495 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
496 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
497 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
498 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
499 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
500 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
501 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
502 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
503 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
504 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
505 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
506 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
510 * @brief Real-Time Clock
515 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
516 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
517 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
518 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
519 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
520 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
521 uint32_t RESERVED0; /*!< Reserved, 0x18 */
522 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
523 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
524 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
525 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
526 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
527 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
528 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
529 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
530 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
531 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
532 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
533 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
534 uint32_t RESERVED7; /*!< Reserved, 0x4C */
535 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
536 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
537 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
538 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
539 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
540 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
541 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
542 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
543 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
544 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
545 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
546 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
547 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
548 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
549 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
550 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
555 * @brief Serial Peripheral Interface
560 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
561 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
562 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
563 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
564 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
565 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
566 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
567 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
568 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
576 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
577 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
578 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
579 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
580 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
581 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
582 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
583 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
584 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
585 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
586 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
587 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
588 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
589 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
590 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
591 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
592 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
593 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
594 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
595 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
596 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
597 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
598 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
599 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
604 * @brief Touch Sensing Controller (TSC)
608 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
609 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
610 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
611 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
612 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
613 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
614 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
615 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
616 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
617 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
618 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
619 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
620 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
621 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
625 * @brief Universal Synchronous Asynchronous Receiver Transmitter
630 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
631 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
632 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
633 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
634 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
635 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
636 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
637 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
638 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
639 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
640 uint16_t RESERVED1; /*!< Reserved, 0x26 */
641 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
642 uint16_t RESERVED2; /*!< Reserved, 0x2A */
646 * @brief Universal Serial Bus Full Speed Device
651 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
652 __IO uint16_t RESERVED0; /*!< Reserved */
653 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
654 __IO uint16_t RESERVED1; /*!< Reserved */
655 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
656 __IO uint16_t RESERVED2; /*!< Reserved */
657 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
658 __IO uint16_t RESERVED3; /*!< Reserved */
659 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
660 __IO uint16_t RESERVED4; /*!< Reserved */
661 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
662 __IO uint16_t RESERVED5; /*!< Reserved */
663 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
664 __IO uint16_t RESERVED6; /*!< Reserved */
665 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
666 __IO uint16_t RESERVED7[17]; /*!< Reserved */
667 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
668 __IO uint16_t RESERVED8; /*!< Reserved */
669 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
670 __IO uint16_t RESERVED9; /*!< Reserved */
671 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
672 __IO uint16_t RESERVEDA; /*!< Reserved */
673 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
674 __IO uint16_t RESERVEDB; /*!< Reserved */
675 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
676 __IO uint16_t RESERVEDC; /*!< Reserved */
677 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
678 __IO uint16_t RESERVEDD; /*!< Reserved */
682 * @brief Window WATCHDOG
686 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
687 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
688 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
691 /** @addtogroup Peripheral_memory_map
695 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
696 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
697 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
699 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
700 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
703 /*!< Peripheral memory map */
704 #define APB1PERIPH_BASE PERIPH_BASE
705 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
706 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
707 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
708 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
710 /*!< APB1 peripherals */
711 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
712 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
713 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
714 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
715 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
716 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
717 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
718 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
719 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
720 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
721 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
722 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
723 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
724 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
725 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
726 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
727 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
728 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
729 #define DAC_BASE DAC1_BASE
730 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
732 /*!< APB2 peripherals */
733 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
734 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
735 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
736 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
737 #define COMP_BASE COMP2_BASE
738 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
739 #define OPAMP_BASE OPAMP2_BASE
740 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
741 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
742 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
743 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
744 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
745 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
747 /*!< AHB1 peripherals */
748 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
749 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
750 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
751 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
752 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
753 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
754 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
755 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
756 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
757 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
758 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
759 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
760 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
762 /*!< AHB2 peripherals */
763 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
764 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
765 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
766 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
767 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
769 /*!< AHB3 peripherals */
770 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
771 #define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
773 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
778 /** @addtogroup Peripheral_declaration
781 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
782 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
783 #define RTC ((RTC_TypeDef *) RTC_BASE)
784 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
785 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
786 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
787 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
788 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
789 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
790 #define USART2 ((USART_TypeDef *) USART2_BASE)
791 #define USART3 ((USART_TypeDef *) USART3_BASE)
792 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
793 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
794 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
795 #define CAN ((CAN_TypeDef *) CAN_BASE)
796 #define PWR ((PWR_TypeDef *) PWR_BASE)
797 #define DAC ((DAC_TypeDef *) DAC_BASE)
798 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
799 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
800 #define COMP ((COMP_TypeDef *) COMP_BASE)
801 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
802 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
803 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
804 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
805 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
806 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
807 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
808 #define USART1 ((USART_TypeDef *) USART1_BASE)
809 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
810 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
811 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
812 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
813 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
814 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
815 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
816 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
817 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
818 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
819 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
820 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
821 #define RCC ((RCC_TypeDef *) RCC_BASE)
822 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
823 #define OB ((OB_TypeDef *) OB_BASE)
824 #define CRC ((CRC_TypeDef *) CRC_BASE)
825 #define TSC ((TSC_TypeDef *) TSC_BASE)
826 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
827 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
828 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
829 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
830 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
831 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
832 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
833 #define USB ((USB_TypeDef *) USB_BASE)
838 /** @addtogroup Exported_constants
842 /** @addtogroup Peripheral_Registers_Bits_Definition
846 /******************************************************************************/
847 /* Peripheral Registers_Bits_Definition */
848 /******************************************************************************/
850 /******************************************************************************/
852 /* Analog to Digital Converter SAR (ADC) */
854 /******************************************************************************/
855 /******************** Bit definition for ADC_ISR register ********************/
856 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
857 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
858 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
859 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
860 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
861 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
862 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
863 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
864 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
865 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
866 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
868 /******************** Bit definition for ADC_IER register ********************/
869 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
870 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
871 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
872 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
873 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
874 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
875 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
876 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
877 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
878 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
879 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
881 /******************** Bit definition for ADC_CR register ********************/
882 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
883 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
884 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
885 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
886 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
887 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
888 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
889 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
890 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
891 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
892 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
894 /******************** Bit definition for ADC_CFGR register ********************/
895 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
896 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
898 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
899 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
900 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
902 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
904 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
905 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
906 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
907 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
908 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
910 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
911 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
912 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
914 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
915 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
916 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
917 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
918 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
920 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
921 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
922 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
923 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
925 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
926 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
927 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
928 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
929 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
930 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
932 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
933 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
934 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
935 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
936 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
937 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
939 /******************** Bit definition for ADC_SMPR1 register ********************/
940 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
941 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
942 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
943 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
945 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
946 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
947 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
948 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
950 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
951 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
952 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
953 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
955 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
956 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
957 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
958 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
960 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
961 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
962 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
963 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
965 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
966 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
967 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
968 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
970 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
971 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
972 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
973 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
975 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
976 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
977 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
978 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
980 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
981 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
982 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
983 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
985 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
986 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
987 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
988 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
990 /******************** Bit definition for ADC_SMPR2 register ********************/
991 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
992 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
993 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
994 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
996 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
997 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
998 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
999 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
1001 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
1002 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
1003 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
1004 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
1006 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
1007 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
1008 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
1009 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
1011 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
1012 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
1013 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
1014 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
1016 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
1017 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
1018 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
1019 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
1021 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
1022 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
1023 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
1024 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
1026 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
1027 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
1028 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
1029 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
1031 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
1032 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
1033 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
1034 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
1036 /******************** Bit definition for ADC_TR1 register ********************/
1037 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
1038 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
1039 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
1040 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
1041 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
1042 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
1043 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
1044 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
1045 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
1046 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
1047 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
1048 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
1049 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
1051 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
1052 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
1053 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
1054 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
1055 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
1056 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
1057 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
1058 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
1059 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
1060 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
1061 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
1062 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
1063 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
1065 /******************** Bit definition for ADC_TR2 register ********************/
1066 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
1067 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
1068 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
1069 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
1070 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
1071 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
1072 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
1073 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
1074 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
1076 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
1077 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
1078 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
1079 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
1080 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
1081 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
1082 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
1083 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
1084 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
1086 /******************** Bit definition for ADC_TR3 register ********************/
1087 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
1088 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
1089 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
1090 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
1091 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
1092 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
1093 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
1094 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
1095 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
1097 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
1098 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
1099 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
1100 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
1101 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
1102 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
1103 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
1104 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
1105 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
1107 /******************** Bit definition for ADC_SQR1 register ********************/
1108 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
1109 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
1110 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
1111 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
1112 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
1114 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
1115 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
1116 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
1117 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
1118 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
1119 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
1121 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
1122 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
1123 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
1124 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
1125 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
1126 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
1128 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
1129 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
1130 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
1131 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
1132 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
1133 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
1135 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
1136 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
1137 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
1138 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
1139 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
1140 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
1142 /******************** Bit definition for ADC_SQR2 register ********************/
1143 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
1144 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
1145 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
1146 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
1147 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
1148 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
1150 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
1151 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
1152 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
1153 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
1154 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
1155 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
1157 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
1158 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
1159 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
1160 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
1161 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
1162 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
1164 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
1165 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
1166 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
1167 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
1168 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
1169 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
1171 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
1172 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
1173 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
1174 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
1175 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
1176 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
1178 /******************** Bit definition for ADC_SQR3 register ********************/
1179 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
1180 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
1181 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
1182 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
1183 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
1184 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
1186 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
1187 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
1188 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
1189 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
1190 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
1191 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
1193 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
1194 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
1195 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
1196 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
1197 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
1198 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
1200 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
1201 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
1202 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
1203 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
1204 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
1205 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
1207 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
1208 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
1209 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
1210 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
1211 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
1212 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
1214 /******************** Bit definition for ADC_SQR4 register ********************/
1215 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
1216 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
1217 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
1218 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
1219 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
1220 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
1222 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
1223 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
1224 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
1225 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
1226 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
1227 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
1228 /******************** Bit definition for ADC_DR register ********************/
1229 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
1230 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
1231 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
1232 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
1233 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
1234 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
1235 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
1236 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
1237 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
1238 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
1239 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
1240 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
1241 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
1242 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
1243 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
1244 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
1245 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
1247 /******************** Bit definition for ADC_JSQR register ********************/
1248 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
1249 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
1250 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
1252 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
1253 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
1254 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
1255 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
1256 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
1258 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
1259 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
1260 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
1262 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
1263 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
1264 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
1265 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
1266 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
1267 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
1269 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
1270 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
1271 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
1272 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
1273 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
1274 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
1276 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
1277 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
1278 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
1279 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
1280 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
1281 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
1283 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
1284 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
1285 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
1286 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
1287 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
1288 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
1290 /******************** Bit definition for ADC_OFR1 register ********************/
1291 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
1292 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
1293 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
1294 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
1295 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
1296 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
1297 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
1298 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
1299 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
1300 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
1301 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
1302 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
1303 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
1305 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
1306 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
1307 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
1308 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
1309 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
1310 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
1312 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
1314 /******************** Bit definition for ADC_OFR2 register ********************/
1315 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
1316 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
1317 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
1318 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
1319 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
1320 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
1321 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
1322 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
1323 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
1324 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
1325 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
1326 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
1327 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
1329 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
1330 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
1331 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
1332 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
1333 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
1334 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
1336 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
1338 /******************** Bit definition for ADC_OFR3 register ********************/
1339 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
1340 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
1341 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
1342 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
1343 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
1344 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
1345 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
1346 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
1347 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
1348 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
1349 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
1350 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
1351 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
1353 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
1354 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
1355 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
1356 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
1357 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
1358 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
1360 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
1362 /******************** Bit definition for ADC_OFR4 register ********************/
1363 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
1364 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
1365 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
1366 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
1367 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
1368 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
1369 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
1370 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
1371 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
1372 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
1373 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
1374 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
1375 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
1377 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
1378 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
1379 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
1380 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
1381 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
1382 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
1384 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
1386 /******************** Bit definition for ADC_JDR1 register ********************/
1387 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1388 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1389 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1390 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1391 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1392 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1393 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1394 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1395 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1396 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1397 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1398 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1399 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1400 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1401 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1402 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1403 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1405 /******************** Bit definition for ADC_JDR2 register ********************/
1406 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1407 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1408 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1409 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1410 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1411 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1412 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1413 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1414 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1415 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1416 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1417 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1418 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1419 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1420 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1421 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1422 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1424 /******************** Bit definition for ADC_JDR3 register ********************/
1425 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1426 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1427 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1428 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1429 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1430 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1431 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1432 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1433 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1434 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1435 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1436 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1437 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1438 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1439 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1440 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1441 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1443 /******************** Bit definition for ADC_JDR4 register ********************/
1444 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1445 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1446 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1447 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1448 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1449 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1450 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1451 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1452 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1453 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1454 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1455 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1456 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1457 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1458 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1459 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1460 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1462 /******************** Bit definition for ADC_AWD2CR register ********************/
1463 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
1464 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
1465 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
1466 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
1467 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
1468 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
1469 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
1470 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
1471 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
1472 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
1473 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
1474 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
1475 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
1476 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
1477 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
1478 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
1479 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
1480 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
1481 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
1483 /******************** Bit definition for ADC_AWD3CR register ********************/
1484 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
1485 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
1486 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
1487 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
1488 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
1489 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
1490 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
1491 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
1492 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
1493 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
1494 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
1495 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
1496 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
1497 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
1498 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
1499 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
1500 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
1501 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
1502 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
1504 /******************** Bit definition for ADC_DIFSEL register ********************/
1505 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
1506 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
1507 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
1508 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
1509 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
1510 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
1511 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
1512 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
1513 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
1514 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
1515 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
1516 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
1517 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
1518 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
1519 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
1520 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
1521 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
1522 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
1523 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
1525 /******************** Bit definition for ADC_CALFACT register ********************/
1526 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
1527 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
1528 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
1529 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
1530 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
1531 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
1532 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
1533 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
1534 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
1535 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
1536 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
1537 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
1538 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
1539 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
1540 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
1541 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
1543 /************************* ADC Common registers *****************************/
1544 /******************** Bit definition for ADC1_CSR register ********************/
1545 #define ADC1_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
1546 #define ADC1_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
1547 #define ADC1_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
1548 #define ADC1_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
1549 #define ADC1_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
1550 #define ADC1_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
1551 #define ADC1_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
1552 #define ADC1_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
1553 #define ADC1_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
1554 #define ADC1_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
1555 #define ADC1_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
1556 #define ADC1_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
1557 #define ADC1_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
1558 #define ADC1_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
1559 #define ADC1_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
1560 #define ADC1_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
1561 #define ADC1_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
1562 #define ADC1_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
1563 #define ADC1_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
1564 #define ADC1_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
1565 #define ADC1_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
1566 #define ADC1_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
1568 /******************** Bit definition for ADC_CCR register ********************/
1569 #define ADC1_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
1570 #define ADC1_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
1571 #define ADC1_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
1572 #define ADC1_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
1573 #define ADC1_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
1574 #define ADC1_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
1575 #define ADC1_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
1576 #define ADC1_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
1577 #define ADC1_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
1578 #define ADC1_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
1579 #define ADC1_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
1580 #define ADC1_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
1581 #define ADC1_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
1582 #define ADC1_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
1583 #define ADC1_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
1584 #define ADC1_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
1585 #define ADC1_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
1586 #define ADC1_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
1587 #define ADC1_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
1588 #define ADC1_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
1589 #define ADC1_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
1591 /******************** Bit definition for ADC_CDR register ********************/
1592 #define ADC1_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
1593 #define ADC1_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
1594 #define ADC1_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
1595 #define ADC1_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
1596 #define ADC1_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
1597 #define ADC1_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
1598 #define ADC1_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
1599 #define ADC1_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
1600 #define ADC1_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
1601 #define ADC1_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
1602 #define ADC1_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
1603 #define ADC1_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
1604 #define ADC1_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
1605 #define ADC1_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
1606 #define ADC1_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
1607 #define ADC1_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
1608 #define ADC1_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
1610 #define ADC1_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
1611 #define ADC1_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
1612 #define ADC1_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
1613 #define ADC1_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
1614 #define ADC1_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
1615 #define ADC1_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
1616 #define ADC1_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
1617 #define ADC1_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
1618 #define ADC1_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
1619 #define ADC1_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
1620 #define ADC1_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
1621 #define ADC1_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
1622 #define ADC1_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
1623 #define ADC1_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
1624 #define ADC1_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
1625 #define ADC1_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
1626 #define ADC1_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
1628 /******************************************************************************/
1630 /* Analog Comparators (COMP) */
1632 /******************************************************************************/
1633 /********************** Bit definition for COMP2_CSR register ***************/
1634 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
1635 #define COMP2_CSR_COMP2INPDAC ((uint32_t)0x00000002) /*!< COMP2 non inverting input to DAC output */
1636 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /*!< COMP2 inverting input select */
1637 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
1638 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
1639 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
1640 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
1641 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
1642 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
1643 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
1644 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
1645 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
1646 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
1647 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
1648 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
1649 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
1650 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
1651 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
1653 /********************** Bit definition for COMP4_CSR register ***************/
1654 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
1655 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /*!< COMP4 inverting input select */
1656 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
1657 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
1658 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
1659 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
1660 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
1661 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
1662 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
1663 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
1664 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
1665 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
1666 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
1667 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
1668 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
1669 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
1670 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
1672 /********************** Bit definition for COMP6_CSR register ***************/
1673 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
1674 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /*!< COMP6 inverting input select */
1675 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
1676 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
1677 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
1678 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
1679 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
1680 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
1681 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
1682 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
1683 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
1684 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
1685 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
1686 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
1687 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
1688 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
1689 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
1691 /********************** Bit definition for COMP_CSR register ****************/
1692 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
1693 #define COMP_CSR_COMP2SW1 ((uint32_t)0x00000002) /*!< COMP2 SW1 switch control */
1694 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
1695 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
1696 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
1697 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
1698 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
1699 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
1700 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
1701 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
1702 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
1703 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
1704 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
1705 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
1706 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
1707 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
1708 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
1709 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
1711 /******************************************************************************/
1713 /* Operational Amplifier (OPAMP) */
1715 /******************************************************************************/
1716 /********************* Bit definition for OPAMP2_CSR register ***************/
1717 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
1718 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
1719 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
1720 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
1721 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
1722 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
1723 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1724 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1725 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
1726 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
1727 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
1728 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
1729 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
1730 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
1731 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
1732 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1733 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1734 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
1735 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
1736 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
1737 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
1738 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
1739 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
1740 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
1741 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
1742 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
1743 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
1744 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
1746 /********************* Bit definition for OPAMPx_CSR register ***************/
1747 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
1748 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
1749 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
1750 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
1751 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
1752 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
1753 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1754 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1755 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
1756 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
1757 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
1758 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
1759 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
1760 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
1761 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
1762 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1763 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1764 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
1765 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
1766 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
1767 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
1768 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
1769 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
1770 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
1771 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
1772 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
1773 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
1774 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
1776 /******************************************************************************/
1778 /* Controller Area Network (CAN ) */
1780 /******************************************************************************/
1781 /******************* Bit definition for CAN_MCR register ********************/
1782 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
1783 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
1784 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
1785 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
1786 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
1787 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
1788 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
1789 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
1790 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
1792 /******************* Bit definition for CAN_MSR register ********************/
1793 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
1794 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
1795 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
1796 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
1797 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
1798 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
1799 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
1800 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
1801 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
1803 /******************* Bit definition for CAN_TSR register ********************/
1804 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1805 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1806 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1807 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1808 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1809 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1810 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1811 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1812 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1813 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1814 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1815 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1816 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1817 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1818 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1819 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1821 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1822 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1823 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1824 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1826 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1827 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1828 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1829 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1831 /******************* Bit definition for CAN_RF0R register *******************/
1832 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
1833 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
1834 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
1835 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
1837 /******************* Bit definition for CAN_RF1R register *******************/
1838 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
1839 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
1840 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
1841 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
1843 /******************** Bit definition for CAN_IER register *******************/
1844 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1845 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1846 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1847 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1848 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1849 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1850 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1851 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1852 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1853 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1854 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1855 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1856 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1857 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1859 /******************** Bit definition for CAN_ESR register *******************/
1860 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1861 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1862 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1864 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1865 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1866 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1867 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1869 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1870 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1872 /******************* Bit definition for CAN_BTR register ********************/
1873 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1874 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1875 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
1876 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
1877 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
1878 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
1879 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1880 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
1881 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
1882 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
1883 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1884 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
1885 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
1886 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1887 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1889 /*!<Mailbox registers */
1890 /****************** Bit definition for CAN_TI0R register ********************/
1891 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1892 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1893 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1894 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1895 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1897 /****************** Bit definition for CAN_TDT0R register *******************/
1898 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1899 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1900 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1902 /****************** Bit definition for CAN_TDL0R register *******************/
1903 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1904 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1905 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1906 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1908 /****************** Bit definition for CAN_TDH0R register *******************/
1909 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1910 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1911 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1912 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1914 /******************* Bit definition for CAN_TI1R register *******************/
1915 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1916 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1917 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1918 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1919 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1921 /******************* Bit definition for CAN_TDT1R register ******************/
1922 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1923 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1924 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1926 /******************* Bit definition for CAN_TDL1R register ******************/
1927 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1928 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1929 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1930 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1932 /******************* Bit definition for CAN_TDH1R register ******************/
1933 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1934 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1935 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1936 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1938 /******************* Bit definition for CAN_TI2R register *******************/
1939 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1940 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1941 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1942 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1943 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1945 /******************* Bit definition for CAN_TDT2R register ******************/
1946 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1947 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1948 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1950 /******************* Bit definition for CAN_TDL2R register ******************/
1951 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1952 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1953 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1954 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1956 /******************* Bit definition for CAN_TDH2R register ******************/
1957 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1958 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1959 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1960 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1962 /******************* Bit definition for CAN_RI0R register *******************/
1963 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1964 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1965 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1966 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1968 /******************* Bit definition for CAN_RDT0R register ******************/
1969 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1970 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1971 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1973 /******************* Bit definition for CAN_RDL0R register ******************/
1974 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1975 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1976 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1977 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1979 /******************* Bit definition for CAN_RDH0R register ******************/
1980 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1981 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1982 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1983 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1985 /******************* Bit definition for CAN_RI1R register *******************/
1986 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1987 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1988 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1989 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1991 /******************* Bit definition for CAN_RDT1R register ******************/
1992 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1993 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1994 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1996 /******************* Bit definition for CAN_RDL1R register ******************/
1997 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1998 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1999 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2000 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2002 /******************* Bit definition for CAN_RDH1R register ******************/
2003 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2004 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2005 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2006 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2008 /*!<CAN filter registers */
2009 /******************* Bit definition for CAN_FMR register ********************/
2010 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
2012 /******************* Bit definition for CAN_FM1R register *******************/
2013 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
2014 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
2015 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
2016 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
2017 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
2018 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
2019 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
2020 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
2021 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
2022 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
2023 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
2024 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
2025 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
2026 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
2027 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
2029 /******************* Bit definition for CAN_FS1R register *******************/
2030 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
2031 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
2032 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
2033 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
2034 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
2035 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
2036 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
2037 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
2038 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
2039 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
2040 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
2041 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
2042 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
2043 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
2044 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
2046 /****************** Bit definition for CAN_FFA1R register *******************/
2047 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
2048 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
2049 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
2050 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
2051 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
2052 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
2053 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
2054 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
2055 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
2056 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
2057 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
2058 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
2059 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
2060 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
2061 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
2063 /******************* Bit definition for CAN_FA1R register *******************/
2064 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
2065 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
2066 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
2067 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
2068 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
2069 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
2070 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
2071 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
2072 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
2073 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
2074 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
2075 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
2076 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
2077 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
2078 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
2080 /******************* Bit definition for CAN_F0R1 register *******************/
2081 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2082 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2083 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2084 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2085 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2086 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2087 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2088 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2089 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2090 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2091 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2092 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2093 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2094 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2095 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2096 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2097 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2098 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2099 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2100 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2101 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2102 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2103 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2104 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2105 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2106 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2107 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2108 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2109 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2110 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2111 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2112 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2114 /******************* Bit definition for CAN_F1R1 register *******************/
2115 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2116 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2117 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2118 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2119 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2120 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2121 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2122 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2123 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2124 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2125 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2126 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2127 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2128 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2129 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2130 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2131 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2132 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2133 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2134 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2135 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2136 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2137 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2138 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2139 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2140 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2141 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2142 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2143 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2144 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2145 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2146 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2148 /******************* Bit definition for CAN_F2R1 register *******************/
2149 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2150 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2151 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2152 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2153 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2154 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2155 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2156 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2157 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2158 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2159 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2160 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2161 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2162 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2163 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2164 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2165 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2166 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2167 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2168 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2169 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2170 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2171 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2172 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2173 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2174 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2175 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2176 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2177 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2178 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2179 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2180 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2182 /******************* Bit definition for CAN_F3R1 register *******************/
2183 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2184 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2185 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2186 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2187 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2188 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2189 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2190 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2191 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2192 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2193 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2194 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2195 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2196 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2197 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2198 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2199 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2200 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2201 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2202 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2203 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2204 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2205 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2206 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2207 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2208 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2209 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2210 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2211 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2212 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2213 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2214 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2216 /******************* Bit definition for CAN_F4R1 register *******************/
2217 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2218 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2219 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2220 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2221 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2222 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2223 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2224 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2225 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2226 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2227 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2228 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2229 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2230 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2231 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2232 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2233 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2234 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2235 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2236 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2237 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2238 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2239 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2240 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2241 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2242 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2243 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2244 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2245 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2246 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2247 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2248 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2250 /******************* Bit definition for CAN_F5R1 register *******************/
2251 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2252 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2253 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2254 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2255 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2256 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2257 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2258 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2259 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2260 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2261 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2262 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2263 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2264 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2265 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2266 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2267 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2268 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2269 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2270 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2271 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2272 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2273 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2274 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2275 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2276 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2277 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2278 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2279 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2280 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2281 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2282 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2284 /******************* Bit definition for CAN_F6R1 register *******************/
2285 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2286 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2287 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2288 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2289 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2290 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2291 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2292 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2293 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2294 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2295 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2296 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2297 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2298 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2299 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2300 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2301 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2302 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2303 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2304 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2305 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2306 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2307 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2308 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2309 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2310 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2311 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2312 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2313 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2314 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2315 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2316 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2318 /******************* Bit definition for CAN_F7R1 register *******************/
2319 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2320 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2321 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2322 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2323 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2324 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2325 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2326 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2327 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2328 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2329 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2330 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2331 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2332 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2333 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2334 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2335 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2336 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2337 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2338 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2339 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2340 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2341 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2342 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2343 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2344 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2345 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2346 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2347 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2348 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2349 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2350 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2352 /******************* Bit definition for CAN_F8R1 register *******************/
2353 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2354 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2355 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2356 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2357 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2358 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2359 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2360 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2361 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2362 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2363 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2364 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2365 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2366 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2367 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2368 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2369 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2370 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2371 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2372 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2373 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2374 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2375 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2376 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2377 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2378 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2379 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2380 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2381 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2382 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2383 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2384 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2386 /******************* Bit definition for CAN_F9R1 register *******************/
2387 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2388 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2389 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2390 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2391 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2392 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2393 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2394 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2395 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2396 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2397 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2398 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2399 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2400 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2401 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2402 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2403 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2404 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2405 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2406 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2407 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2408 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2409 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2410 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2411 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2412 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2413 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2414 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2415 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2416 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2417 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2418 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2420 /******************* Bit definition for CAN_F10R1 register ******************/
2421 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2422 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2423 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2424 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2425 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2426 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2427 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2428 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2429 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2430 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2431 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2432 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2433 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2434 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2435 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2436 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2437 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2438 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2439 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2440 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2441 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2442 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2443 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2444 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2445 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2446 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2447 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2448 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2449 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2450 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2451 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2452 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2454 /******************* Bit definition for CAN_F11R1 register ******************/
2455 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2456 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2457 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2458 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2459 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2460 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2461 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2462 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2463 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2464 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2465 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2466 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2467 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2468 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2469 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2470 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2471 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2472 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2473 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2474 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2475 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2476 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2477 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2478 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2479 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2480 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2481 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2482 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2483 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2484 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2485 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2486 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2488 /******************* Bit definition for CAN_F12R1 register ******************/
2489 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2490 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2491 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2492 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2493 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2494 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2495 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2496 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2497 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2498 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2499 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2500 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2501 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2502 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2503 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2504 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2505 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2506 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2507 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2508 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2509 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2510 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2511 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2512 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2513 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2514 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2515 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2516 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2517 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2518 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2519 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2520 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2522 /******************* Bit definition for CAN_F13R1 register ******************/
2523 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2524 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2525 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2526 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2527 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2528 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2529 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2530 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2531 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2532 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2533 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2534 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2535 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2536 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2537 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2538 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2539 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2540 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2541 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2542 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2543 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2544 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2545 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2546 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2547 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2548 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2549 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2550 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2551 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2552 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2553 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2554 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2556 /******************* Bit definition for CAN_F0R2 register *******************/
2557 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2558 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2559 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2560 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2561 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2562 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2563 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2564 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2565 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2566 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2567 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2568 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2569 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2570 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2571 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2572 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2573 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2574 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2575 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2576 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2577 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2578 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2579 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2580 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2581 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2582 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2583 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2584 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2585 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2586 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2587 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2588 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2590 /******************* Bit definition for CAN_F1R2 register *******************/
2591 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2592 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2593 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2594 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2595 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2596 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2597 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2598 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2599 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2600 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2601 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2602 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2603 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2604 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2605 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2606 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2607 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2608 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2609 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2610 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2611 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2612 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2613 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2614 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2615 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2616 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2617 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2618 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2619 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2620 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2621 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2622 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2624 /******************* Bit definition for CAN_F2R2 register *******************/
2625 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2626 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2627 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2628 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2629 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2630 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2631 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2632 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2633 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2634 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2635 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2636 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2637 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2638 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2639 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2640 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2641 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2642 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2643 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2644 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2645 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2646 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2647 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2648 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2649 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2650 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2651 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2652 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2653 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2654 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2655 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2656 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2658 /******************* Bit definition for CAN_F3R2 register *******************/
2659 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2660 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2661 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2662 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2663 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2664 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2665 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2666 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2667 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2668 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2669 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2670 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2671 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2672 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2673 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2674 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2675 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2676 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2677 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2678 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2679 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2680 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2681 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2682 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2683 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2684 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2685 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2686 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2687 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2688 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2689 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2690 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2692 /******************* Bit definition for CAN_F4R2 register *******************/
2693 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2694 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2695 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2696 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2697 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2698 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2699 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2700 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2701 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2702 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2703 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2704 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2705 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2706 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2707 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2708 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2709 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2710 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2711 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2712 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2713 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2714 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2715 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2716 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2717 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2718 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2719 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2720 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2721 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2722 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2723 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2724 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2726 /******************* Bit definition for CAN_F5R2 register *******************/
2727 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2728 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2729 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2730 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2731 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2732 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2733 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2734 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2735 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2736 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2737 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2738 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2739 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2740 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2741 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2742 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2743 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2744 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2745 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2746 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2747 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2748 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2749 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2750 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2751 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2752 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2753 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2754 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2755 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2756 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2757 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2758 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2760 /******************* Bit definition for CAN_F6R2 register *******************/
2761 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2762 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2763 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2764 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2765 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2766 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2767 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2768 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2769 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2770 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2771 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2772 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2773 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2774 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2775 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2776 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2777 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2778 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2779 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2780 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2781 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2782 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2783 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2784 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2785 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2786 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2787 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2788 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2789 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2790 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2791 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2792 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2794 /******************* Bit definition for CAN_F7R2 register *******************/
2795 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2796 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2797 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2798 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2799 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2800 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2801 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2802 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2803 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2804 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2805 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2806 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2807 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2808 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2809 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2810 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2811 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2812 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2813 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2814 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2815 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2816 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2817 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2818 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2819 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2820 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2821 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2822 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2823 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2824 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2825 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2826 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2828 /******************* Bit definition for CAN_F8R2 register *******************/
2829 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2830 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2831 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2832 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2833 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2834 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2835 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2836 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2837 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2838 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2839 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2840 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2841 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2842 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2843 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2844 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2845 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2846 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2847 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2848 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2849 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2850 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2851 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2852 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2853 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2854 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2855 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2856 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2857 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2858 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2859 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2860 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2862 /******************* Bit definition for CAN_F9R2 register *******************/
2863 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2864 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2865 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2866 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2867 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2868 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2869 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2870 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2871 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2872 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2873 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2874 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2875 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2876 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2877 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2878 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2879 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2880 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2881 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2882 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2883 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2884 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2885 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2886 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2887 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2888 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2889 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2890 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2891 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2892 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2893 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2894 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2896 /******************* Bit definition for CAN_F10R2 register ******************/
2897 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2898 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2899 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2900 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2901 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2902 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2903 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2904 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2905 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2906 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2907 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2908 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2909 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2910 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2911 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2912 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2913 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2914 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2915 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2916 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2917 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2918 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2919 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2920 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2921 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2922 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2923 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2924 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2925 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2926 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2927 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2928 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2930 /******************* Bit definition for CAN_F11R2 register ******************/
2931 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2932 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2933 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2934 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2935 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2936 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2937 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2938 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2939 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2940 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2941 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2942 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2943 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2944 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2945 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2946 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2947 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2948 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2949 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2950 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2951 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2952 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2953 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2954 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2955 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2956 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2957 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2958 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2959 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2960 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2961 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2962 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2964 /******************* Bit definition for CAN_F12R2 register ******************/
2965 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2966 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2967 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2968 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2969 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2970 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2971 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2972 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2973 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2974 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2975 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2976 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2977 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2978 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2979 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2980 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2981 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2982 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2983 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2984 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2985 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2986 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2987 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2988 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2989 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2990 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2991 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2992 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2993 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2994 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2995 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2996 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2998 /******************* Bit definition for CAN_F13R2 register ******************/
2999 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3000 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3001 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3002 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3003 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3004 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3005 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3006 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3007 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3008 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3009 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3010 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3011 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3012 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3013 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3014 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3015 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3016 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3017 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3018 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3019 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3020 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3021 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3022 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3023 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3024 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3025 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3026 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3027 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3028 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3029 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3030 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3032 /******************************************************************************/
3034 /* CRC calculation unit (CRC) */
3036 /******************************************************************************/
3037 /******************* Bit definition for CRC_DR register *********************/
3038 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
3040 /******************* Bit definition for CRC_IDR register ********************/
3041 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
3043 /******************** Bit definition for CRC_CR register ********************/
3044 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
3045 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
3046 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
3047 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
3048 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
3049 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
3050 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
3051 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
3053 /******************* Bit definition for CRC_INIT register *******************/
3054 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
3056 /******************* Bit definition for CRC_POL register ********************/
3057 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
3059 /******************************************************************************/
3061 /* Digital to Analog Converter (DAC) */
3063 /******************************************************************************/
3064 /******************** Bit definition for DAC_CR register ********************/
3065 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
3066 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
3067 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
3069 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
3070 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
3071 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
3072 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
3074 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3075 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
3076 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
3078 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3079 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3080 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3081 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
3082 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
3084 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
3085 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
3087 /***************** Bit definition for DAC_SWTRIGR register ******************/
3088 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
3090 /***************** Bit definition for DAC_DHR12R1 register ******************/
3091 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
3093 /***************** Bit definition for DAC_DHR12L1 register ******************/
3094 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
3096 /****************** Bit definition for DAC_DHR8R1 register ******************/
3097 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
3099 /***************** Bit definition for DAC_DHR12RD register ******************/
3100 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
3102 /***************** Bit definition for DAC_DHR12LD register ******************/
3103 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
3105 /****************** Bit definition for DAC_DHR8RD register ******************/
3106 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
3108 /******************* Bit definition for DAC_DOR1 register *******************/
3109 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
3111 /******************** Bit definition for DAC_SR register ********************/
3112 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
3114 /******************************************************************************/
3116 /* Debug MCU (DBGMCU) */
3118 /******************************************************************************/
3119 /******************** Bit definition for DBGMCU_IDCODE register *************/
3120 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
3121 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
3123 /******************** Bit definition for DBGMCU_CR register *****************/
3124 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
3125 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
3126 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
3127 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
3129 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
3130 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
3131 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
3133 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
3134 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
3135 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
3136 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
3137 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
3138 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
3139 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
3140 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
3141 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
3143 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
3144 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
3145 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
3146 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
3147 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
3149 /******************************************************************************/
3151 /* DMA Controller (DMA) */
3153 /******************************************************************************/
3154 /******************* Bit definition for DMA_ISR register ********************/
3155 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
3156 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
3157 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
3158 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
3159 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
3160 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
3161 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
3162 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
3163 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
3164 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
3165 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
3166 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
3167 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
3168 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
3169 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
3170 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
3171 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
3172 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
3173 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
3174 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
3175 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
3176 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
3177 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
3178 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
3179 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
3180 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
3181 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
3182 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
3184 /******************* Bit definition for DMA_IFCR register *******************/
3185 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
3186 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
3187 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
3188 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
3189 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
3190 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
3191 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
3192 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
3193 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
3194 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
3195 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
3196 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
3197 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
3198 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
3199 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
3200 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
3201 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
3202 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
3203 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
3204 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
3205 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
3206 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
3207 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
3208 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
3209 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
3210 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
3211 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
3212 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
3214 /******************* Bit definition for DMA_CCR register ********************/
3215 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
3216 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
3217 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
3218 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
3219 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
3220 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
3221 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
3222 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
3224 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
3225 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3226 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3228 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
3229 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
3230 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
3232 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
3233 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3234 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3236 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
3238 /****************** Bit definition for DMA_CNDTR register *******************/
3239 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
3241 /****************** Bit definition for DMA_CPAR register ********************/
3242 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
3244 /****************** Bit definition for DMA_CMAR register ********************/
3245 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3247 /******************************************************************************/
3249 /* External Interrupt/Event Controller (EXTI) */
3251 /******************************************************************************/
3252 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
3253 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3254 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3255 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3256 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3257 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3258 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3259 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3260 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3261 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3262 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3263 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3264 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3265 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3266 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3267 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3268 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3269 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3270 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3271 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3272 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3273 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
3274 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
3275 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
3276 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
3277 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
3278 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
3279 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
3280 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
3281 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
3283 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
3284 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3285 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3286 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3287 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3288 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3289 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3290 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3291 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3292 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3293 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3294 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3295 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3296 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3297 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3298 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3299 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3300 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3301 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3302 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3303 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3304 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
3305 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
3306 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
3307 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
3308 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
3309 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
3310 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
3311 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
3312 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
3314 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
3315 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3316 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3317 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3318 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3319 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3320 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3321 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3322 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3323 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3324 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3325 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3326 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3327 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3328 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3329 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3330 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3331 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3332 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3333 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3334 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3335 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
3336 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
3337 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
3338 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
3339 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
3340 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
3341 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
3342 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
3343 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
3345 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
3346 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3347 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3348 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3349 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3350 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3351 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3352 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3353 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3354 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3355 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3356 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3357 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3358 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3359 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3360 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3361 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3362 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3363 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3364 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3365 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3366 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
3367 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
3368 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
3369 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
3370 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
3371 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
3372 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
3373 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
3374 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
3376 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
3377 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3378 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3379 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3380 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3381 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3382 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3383 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3384 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3385 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3386 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3387 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3388 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3389 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3390 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3391 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3392 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3393 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3394 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3395 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3396 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3397 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
3398 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
3399 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
3400 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
3401 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
3402 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
3403 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
3404 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
3405 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
3407 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
3408 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3409 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3410 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3411 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3412 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3413 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3414 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3415 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3416 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3417 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3418 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3419 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3420 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3421 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3422 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3423 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3424 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3425 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3426 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3427 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3428 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
3429 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
3430 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
3431 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
3432 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
3433 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
3434 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
3435 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
3436 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
3438 /******************************************************************************/
3442 /******************************************************************************/
3443 /******************* Bit definition for FLASH_ACR register ******************/
3444 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
3445 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3446 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3447 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3449 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
3450 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
3451 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
3453 /****************** Bit definition for FLASH_KEYR register ******************/
3454 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
3456 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
3457 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
3458 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
3460 /***************** Bit definition for FLASH_OPTKEYR register ****************/
3461 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
3463 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
3464 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
3466 /****************** Bit definition for FLASH_SR register *******************/
3467 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
3468 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
3469 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
3470 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
3472 /******************* Bit definition for FLASH_CR register *******************/
3473 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
3474 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
3475 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
3476 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
3477 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
3478 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
3479 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
3480 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
3481 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
3482 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
3483 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
3485 /******************* Bit definition for FLASH_AR register *******************/
3486 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
3488 /****************** Bit definition for FLASH_OBR register *******************/
3489 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
3490 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
3491 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
3492 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
3494 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
3495 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
3496 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
3497 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
3498 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
3499 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
3500 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
3502 /****************** Bit definition for FLASH_WRPR register ******************/
3503 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
3505 /*----------------------------------------------------------------------------*/
3507 /****************** Bit definition for OB_RDP register **********************/
3508 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
3509 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
3511 /****************** Bit definition for OB_USER register *********************/
3512 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
3513 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
3515 /****************** Bit definition for FLASH_WRP0 register ******************/
3516 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
3517 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
3519 /****************** Bit definition for FLASH_WRP1 register ******************/
3520 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
3521 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
3523 /****************** Bit definition for FLASH_WRP2 register ******************/
3524 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
3525 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
3527 /****************** Bit definition for FLASH_WRP3 register ******************/
3528 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
3529 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
3530 /******************************************************************************/
3532 /* General Purpose I/O (GPIO) */
3534 /******************************************************************************/
3535 /******************* Bit definition for GPIO_MODER register *****************/
3536 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
3537 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
3538 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
3539 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
3540 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
3541 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
3542 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
3543 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
3544 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
3545 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
3546 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
3547 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
3548 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
3549 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
3550 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
3551 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
3552 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
3553 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
3554 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
3555 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
3556 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
3557 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
3558 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
3559 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
3560 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
3561 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
3562 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
3563 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
3564 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
3565 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
3566 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
3567 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
3568 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
3569 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
3570 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
3571 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
3572 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
3573 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
3574 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
3575 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
3576 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
3577 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
3578 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
3579 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
3580 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
3581 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
3582 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
3583 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
3585 /****************** Bit definition for GPIO_OTYPER register *****************/
3586 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
3587 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
3588 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
3589 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
3590 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
3591 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
3592 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
3593 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
3594 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
3595 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
3596 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
3597 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
3598 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
3599 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
3600 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
3601 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
3603 /**************** Bit definition for GPIO_OSPEEDR register ******************/
3604 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
3605 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
3606 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
3607 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
3608 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
3609 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
3610 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
3611 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
3612 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
3613 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
3614 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
3615 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
3616 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
3617 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
3618 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
3619 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
3620 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
3621 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
3622 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
3623 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
3624 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
3625 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
3626 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
3627 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
3628 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
3629 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
3630 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
3631 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
3632 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
3633 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
3634 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
3635 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
3636 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
3637 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
3638 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
3639 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
3640 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
3641 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
3642 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
3643 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
3644 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
3645 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
3646 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
3647 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
3648 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
3649 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
3650 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
3651 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
3653 /******************* Bit definition for GPIO_PUPDR register ******************/
3654 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
3655 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
3656 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
3657 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
3658 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
3659 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
3660 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
3661 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
3662 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
3663 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
3664 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
3665 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
3666 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
3667 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
3668 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
3669 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
3670 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
3671 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
3672 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
3673 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
3674 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
3675 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
3676 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
3677 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
3678 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
3679 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
3680 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
3681 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
3682 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
3683 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
3684 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
3685 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
3686 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
3687 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
3688 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
3689 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
3690 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
3691 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
3692 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
3693 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
3694 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
3695 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
3696 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
3697 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
3698 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
3699 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
3700 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
3701 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
3703 /******************* Bit definition for GPIO_IDR register *******************/
3704 #define GPIO_IDR_0 ((uint32_t)0x00000001)
3705 #define GPIO_IDR_1 ((uint32_t)0x00000002)
3706 #define GPIO_IDR_2 ((uint32_t)0x00000004)
3707 #define GPIO_IDR_3 ((uint32_t)0x00000008)
3708 #define GPIO_IDR_4 ((uint32_t)0x00000010)
3709 #define GPIO_IDR_5 ((uint32_t)0x00000020)
3710 #define GPIO_IDR_6 ((uint32_t)0x00000040)
3711 #define GPIO_IDR_7 ((uint32_t)0x00000080)
3712 #define GPIO_IDR_8 ((uint32_t)0x00000100)
3713 #define GPIO_IDR_9 ((uint32_t)0x00000200)
3714 #define GPIO_IDR_10 ((uint32_t)0x00000400)
3715 #define GPIO_IDR_11 ((uint32_t)0x00000800)
3716 #define GPIO_IDR_12 ((uint32_t)0x00001000)
3717 #define GPIO_IDR_13 ((uint32_t)0x00002000)
3718 #define GPIO_IDR_14 ((uint32_t)0x00004000)
3719 #define GPIO_IDR_15 ((uint32_t)0x00008000)
3721 /****************** Bit definition for GPIO_ODR register ********************/
3722 #define GPIO_ODR_0 ((uint32_t)0x00000001)
3723 #define GPIO_ODR_1 ((uint32_t)0x00000002)
3724 #define GPIO_ODR_2 ((uint32_t)0x00000004)
3725 #define GPIO_ODR_3 ((uint32_t)0x00000008)
3726 #define GPIO_ODR_4 ((uint32_t)0x00000010)
3727 #define GPIO_ODR_5 ((uint32_t)0x00000020)
3728 #define GPIO_ODR_6 ((uint32_t)0x00000040)
3729 #define GPIO_ODR_7 ((uint32_t)0x00000080)
3730 #define GPIO_ODR_8 ((uint32_t)0x00000100)
3731 #define GPIO_ODR_9 ((uint32_t)0x00000200)
3732 #define GPIO_ODR_10 ((uint32_t)0x00000400)
3733 #define GPIO_ODR_11 ((uint32_t)0x00000800)
3734 #define GPIO_ODR_12 ((uint32_t)0x00001000)
3735 #define GPIO_ODR_13 ((uint32_t)0x00002000)
3736 #define GPIO_ODR_14 ((uint32_t)0x00004000)
3737 #define GPIO_ODR_15 ((uint32_t)0x00008000)
3739 /****************** Bit definition for GPIO_BSRR register ********************/
3740 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
3741 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
3742 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
3743 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
3744 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
3745 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
3746 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
3747 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
3748 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
3749 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
3750 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
3751 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
3752 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
3753 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
3754 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
3755 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
3756 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
3757 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
3758 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
3759 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
3760 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
3761 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
3762 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
3763 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
3764 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
3765 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
3766 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
3767 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
3768 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
3769 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
3770 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
3771 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
3773 /****************** Bit definition for GPIO_LCKR register ********************/
3774 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
3775 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
3776 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
3777 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
3778 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
3779 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
3780 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
3781 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
3782 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
3783 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
3784 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
3785 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
3786 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
3787 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
3788 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
3789 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
3790 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
3792 /****************** Bit definition for GPIO_AFRL register ********************/
3793 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
3794 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
3795 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
3796 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
3797 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
3798 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
3799 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
3800 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
3802 /****************** Bit definition for GPIO_AFRH register ********************/
3803 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
3804 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
3805 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
3806 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
3807 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
3808 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
3809 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
3810 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
3812 /****************** Bit definition for GPIO_BRR register *********************/
3813 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
3814 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
3815 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
3816 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
3817 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
3818 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
3819 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
3820 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
3821 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
3822 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
3823 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
3824 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
3825 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
3826 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
3827 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
3828 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
3830 /******************************************************************************/
3832 /* Inter-integrated Circuit Interface (I2C) */
3834 /******************************************************************************/
3835 /******************* Bit definition for I2C_CR1 register *******************/
3836 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
3837 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
3838 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
3839 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
3840 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
3841 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
3842 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
3843 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
3844 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
3845 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
3846 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
3847 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
3848 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
3849 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
3850 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
3851 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
3852 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
3853 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
3854 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
3855 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
3856 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
3858 /****************** Bit definition for I2C_CR2 register ********************/
3859 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
3860 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
3861 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
3862 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
3863 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
3864 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
3865 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
3866 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
3867 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
3868 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
3869 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
3871 /******************* Bit definition for I2C_OAR1 register ******************/
3872 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
3873 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
3874 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
3876 /******************* Bit definition for I2C_OAR2 register *******************/
3877 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
3878 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
3879 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
3881 /******************* Bit definition for I2C_TIMINGR register *****************/
3882 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
3883 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
3884 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
3885 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
3886 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
3888 /******************* Bit definition for I2C_TIMEOUTR register *****************/
3889 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
3890 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
3891 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
3892 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
3893 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
3895 /****************** Bit definition for I2C_ISR register *********************/
3896 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
3897 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
3898 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
3899 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
3900 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
3901 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
3902 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
3903 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
3904 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
3905 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
3906 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
3907 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
3908 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
3909 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
3910 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
3911 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
3912 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
3914 /****************** Bit definition for I2C_ICR register *********************/
3915 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
3916 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
3917 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
3918 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
3919 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
3920 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
3921 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
3922 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
3923 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
3925 /****************** Bit definition for I2C_PECR register ********************/
3926 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
3928 /****************** Bit definition for I2C_RXDR register *********************/
3929 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
3931 /****************** Bit definition for I2C_TXDR register *********************/
3932 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
3935 /******************************************************************************/
3937 /* Independent WATCHDOG (IWDG) */
3939 /******************************************************************************/
3940 /******************* Bit definition for IWDG_KR register ********************/
3941 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
3943 /******************* Bit definition for IWDG_PR register ********************/
3944 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
3945 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3946 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3947 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3949 /******************* Bit definition for IWDG_RLR register *******************/
3950 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
3952 /******************* Bit definition for IWDG_SR register ********************/
3953 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
3954 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
3955 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
3957 /******************* Bit definition for IWDG_KR register ********************/
3958 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
3960 /******************************************************************************/
3964 /******************************************************************************/
3965 /******************** Bit definition for PWR_CR register ********************/
3966 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
3967 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
3968 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
3969 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
3970 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
3972 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
3973 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
3974 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
3975 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
3977 /*!< PVD level configuration */
3978 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
3979 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
3980 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
3981 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
3982 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
3983 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
3984 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
3985 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
3987 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
3989 /******************* Bit definition for PWR_CSR register ********************/
3990 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
3991 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
3992 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
3993 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
3995 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
3996 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
3997 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
3999 /******************************************************************************/
4001 /* Reset and Clock Control */
4003 /******************************************************************************/
4004 /******************** Bit definition for RCC_CR register ********************/
4005 #define RCC_CR_HSION ((uint32_t)0x00000001)
4006 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
4008 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
4009 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
4010 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
4011 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
4012 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
4013 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
4015 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
4016 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
4017 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
4018 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
4019 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
4020 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
4021 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
4022 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
4023 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
4025 #define RCC_CR_HSEON ((uint32_t)0x00010000)
4026 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
4027 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
4028 #define RCC_CR_CSSON ((uint32_t)0x00080000)
4029 #define RCC_CR_PLLON ((uint32_t)0x01000000)
4030 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
4032 /******************** Bit definition for RCC_CFGR register ******************/
4033 /*!< SW configuration */
4034 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
4035 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4036 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4038 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
4039 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
4040 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
4042 /*!< SWS configuration */
4043 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
4044 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
4045 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
4047 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
4048 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
4049 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
4051 /*!< HPRE configuration */
4052 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
4053 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
4054 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
4055 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
4056 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
4058 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
4059 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
4060 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
4061 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
4062 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
4063 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
4064 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
4065 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
4066 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
4068 /*!< PPRE1 configuration */
4069 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
4070 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
4071 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
4072 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
4074 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4075 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
4076 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
4077 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
4078 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
4080 /*!< PPRE2 configuration */
4081 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
4082 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
4083 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
4084 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
4086 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4087 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
4088 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
4089 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
4090 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
4092 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
4093 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
4094 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
4096 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
4097 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
4098 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
4100 /*!< PLLMUL configuration */
4101 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
4102 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
4103 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
4104 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
4105 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
4107 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
4108 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
4109 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
4110 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
4111 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
4112 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
4113 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
4114 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
4115 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
4116 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
4117 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
4118 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
4119 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
4120 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
4121 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
4123 /*!< USB configuration */
4124 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
4126 #define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
4127 #define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
4129 /*!< I2S configuration */
4130 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
4132 #define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
4133 #define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
4135 /*!< MCO configuration */
4136 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
4137 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
4138 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
4139 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
4141 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
4142 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
4143 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
4144 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
4145 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
4146 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
4147 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
4149 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
4150 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
4151 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
4152 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
4154 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
4156 /********************* Bit definition for RCC_CIR register ********************/
4157 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
4158 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
4159 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
4160 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
4161 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
4162 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
4163 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
4164 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
4165 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
4166 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
4167 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
4168 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
4169 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
4170 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
4171 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
4172 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
4173 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
4175 /****************** Bit definition for RCC_APB2RSTR register *****************/
4176 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
4177 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
4178 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
4179 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
4180 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
4181 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
4183 /****************** Bit definition for RCC_APB1RSTR register ******************/
4184 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
4185 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
4186 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
4187 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
4188 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
4189 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
4190 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
4191 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
4192 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
4193 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
4194 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
4195 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
4196 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
4197 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
4199 /****************** Bit definition for RCC_AHBENR register ******************/
4200 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
4201 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
4202 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
4203 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
4204 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
4205 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
4206 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
4207 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
4208 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
4209 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
4210 #define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
4212 /***************** Bit definition for RCC_APB2ENR register ******************/
4213 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
4214 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
4215 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
4216 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
4217 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
4218 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
4220 /****************** Bit definition for RCC_APB1ENR register ******************/
4221 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
4222 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
4223 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
4224 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
4225 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
4226 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
4227 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
4228 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
4229 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
4230 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
4231 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
4232 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
4233 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
4234 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
4236 /******************** Bit definition for RCC_BDCR register ******************/
4237 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
4238 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
4239 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
4240 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
4242 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
4243 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
4244 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
4246 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
4247 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
4248 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
4250 /*!< RTC configuration */
4251 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
4252 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
4253 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
4254 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
4256 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
4257 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
4259 /******************** Bit definition for RCC_CSR register *******************/
4260 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
4261 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
4262 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
4263 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
4264 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
4265 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
4266 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
4267 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
4268 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
4269 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
4271 /******************* Bit definition for RCC_AHBRSTR register ****************/
4272 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
4273 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
4274 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
4275 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
4276 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
4277 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
4278 #define RCC_AHBRSTR_ADC1RST ((uint32_t)0x10000000) /*!< ADC1 reset */
4280 /******************* Bit definition for RCC_CFGR2 register ******************/
4281 /*!< PREDIV configuration */
4282 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
4283 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4284 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4285 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4286 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4288 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
4289 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
4290 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
4291 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
4292 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
4293 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
4294 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
4295 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
4296 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
4297 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
4298 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
4299 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
4300 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
4301 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
4302 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
4303 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
4305 /*!< ADC1PRES configuration */
4306 #define RCC_CFGR2_ADC1PRES ((uint32_t)0x000001F0) /*!< ADC1PRES[8:4] bits */
4307 #define RCC_CFGR2_ADC1PRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
4308 #define RCC_CFGR2_ADC1PRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
4309 #define RCC_CFGR2_ADC1PRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
4310 #define RCC_CFGR2_ADC1PRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
4311 #define RCC_CFGR2_ADC1PRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */
4313 #define RCC_CFGR2_ADC1PRES_NO ((uint32_t)0x00000000) /*!< ADC1 clock disabled, ADC1 can use AHB clock */
4314 #define RCC_CFGR2_ADC1PRES_DIV1 ((uint32_t)0x00000100) /*!< ADC1 PLL clock divided by 1 */
4315 #define RCC_CFGR2_ADC1PRES_DIV2 ((uint32_t)0x00000110) /*!< ADC1 PLL clock divided by 2 */
4316 #define RCC_CFGR2_ADC1PRES_DIV4 ((uint32_t)0x00000120) /*!< ADC1 PLL clock divided by 4 */
4317 #define RCC_CFGR2_ADC1PRES_DIV6 ((uint32_t)0x00000130) /*!< ADC1 PLL clock divided by 6 */
4318 #define RCC_CFGR2_ADC1PRES_DIV8 ((uint32_t)0x00000140) /*!< ADC1 PLL clock divided by 8 */
4319 #define RCC_CFGR2_ADC1PRES_DIV10 ((uint32_t)0x00000150) /*!< ADC1 PLL clock divided by 10 */
4320 #define RCC_CFGR2_ADC1PRES_DIV12 ((uint32_t)0x00000160) /*!< ADC1 PLL clock divided by 12 */
4321 #define RCC_CFGR2_ADC1PRES_DIV16 ((uint32_t)0x00000170) /*!< ADC1 PLL clock divided by 16 */
4322 #define RCC_CFGR2_ADC1PRES_DIV32 ((uint32_t)0x00000180) /*!< ADC1 PLL clock divided by 32 */
4323 #define RCC_CFGR2_ADC1PRES_DIV64 ((uint32_t)0x00000190) /*!< ADC1 PLL clock divided by 64 */
4324 #define RCC_CFGR2_ADC1PRES_DIV128 ((uint32_t)0x000001A0) /*!< ADC1 PLL clock divided by 128 */
4325 #define RCC_CFGR2_ADC1PRES_DIV256 ((uint32_t)0x000001B0) /*!< ADC1 PLL clock divided by 256 */
4327 /******************* Bit definition for RCC_CFGR3 register ******************/
4328 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
4329 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4330 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4332 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
4333 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
4334 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
4335 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
4337 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
4338 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
4339 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
4340 #define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
4342 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
4343 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
4344 #define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
4345 #define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
4346 #define RCC_CFGR3_I2C3SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C3 clock source */
4347 #define RCC_CFGR3_I2C3SW_SYSCLK ((uint32_t)0x00000040) /*!< System clock selected as I2C3 clock source */
4349 #define RCC_CFGR3_TIMSW ((uint32_t)0x00002D00) /*!< TIMSW bits */
4350 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
4351 #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
4352 #define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
4353 #define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
4355 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
4356 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
4358 #define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
4359 #define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
4361 #define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
4362 #define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
4364 #define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
4365 #define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
4367 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
4368 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
4369 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
4371 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
4372 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
4373 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
4374 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
4376 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
4377 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
4378 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
4380 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
4381 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
4382 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
4383 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
4385 /******************************************************************************/
4387 /* Real-Time Clock (RTC) */
4389 /******************************************************************************/
4390 /******************** Bits definition for RTC_TR register *******************/
4391 #define RTC_TR_PM ((uint32_t)0x00400000)
4392 #define RTC_TR_HT ((uint32_t)0x00300000)
4393 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
4394 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
4395 #define RTC_TR_HU ((uint32_t)0x000F0000)
4396 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
4397 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
4398 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
4399 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
4400 #define RTC_TR_MNT ((uint32_t)0x00007000)
4401 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
4402 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
4403 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
4404 #define RTC_TR_MNU ((uint32_t)0x00000F00)
4405 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
4406 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
4407 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
4408 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
4409 #define RTC_TR_ST ((uint32_t)0x00000070)
4410 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
4411 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
4412 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
4413 #define RTC_TR_SU ((uint32_t)0x0000000F)
4414 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
4415 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
4416 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
4417 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
4419 /******************** Bits definition for RTC_DR register *******************/
4420 #define RTC_DR_YT ((uint32_t)0x00F00000)
4421 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
4422 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
4423 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
4424 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
4425 #define RTC_DR_YU ((uint32_t)0x000F0000)
4426 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
4427 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
4428 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
4429 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
4430 #define RTC_DR_WDU ((uint32_t)0x0000E000)
4431 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
4432 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
4433 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
4434 #define RTC_DR_MT ((uint32_t)0x00001000)
4435 #define RTC_DR_MU ((uint32_t)0x00000F00)
4436 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
4437 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
4438 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
4439 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
4440 #define RTC_DR_DT ((uint32_t)0x00000030)
4441 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
4442 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
4443 #define RTC_DR_DU ((uint32_t)0x0000000F)
4444 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
4445 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
4446 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
4447 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
4449 /******************** Bits definition for RTC_CR register *******************/
4450 #define RTC_CR_COE ((uint32_t)0x00800000)
4451 #define RTC_CR_OSEL ((uint32_t)0x00600000)
4452 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
4453 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
4454 #define RTC_CR_POL ((uint32_t)0x00100000)
4455 #define RTC_CR_COSEL ((uint32_t)0x00080000)
4456 #define RTC_CR_BCK ((uint32_t)0x00040000)
4457 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
4458 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
4459 #define RTC_CR_TSIE ((uint32_t)0x00008000)
4460 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
4461 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
4462 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
4463 #define RTC_CR_TSE ((uint32_t)0x00000800)
4464 #define RTC_CR_WUTE ((uint32_t)0x00000400)
4465 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
4466 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
4467 #define RTC_CR_FMT ((uint32_t)0x00000040)
4468 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
4469 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
4470 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
4471 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
4472 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
4473 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
4474 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
4476 /******************** Bits definition for RTC_ISR register ******************/
4477 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
4478 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
4479 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
4480 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
4481 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
4482 #define RTC_ISR_TSF ((uint32_t)0x00000800)
4483 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
4484 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
4485 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
4486 #define RTC_ISR_INIT ((uint32_t)0x00000080)
4487 #define RTC_ISR_INITF ((uint32_t)0x00000040)
4488 #define RTC_ISR_RSF ((uint32_t)0x00000020)
4489 #define RTC_ISR_INITS ((uint32_t)0x00000010)
4490 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
4491 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
4492 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
4493 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
4495 /******************** Bits definition for RTC_PRER register *****************/
4496 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
4497 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
4499 /******************** Bits definition for RTC_WUTR register *****************/
4500 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
4502 /******************** Bits definition for RTC_ALRMAR register ***************/
4503 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
4504 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
4505 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
4506 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
4507 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
4508 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
4509 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
4510 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
4511 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
4512 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
4513 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
4514 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
4515 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
4516 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
4517 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
4518 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
4519 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
4520 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
4521 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
4522 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
4523 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
4524 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
4525 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
4526 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
4527 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
4528 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
4529 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
4530 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
4531 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
4532 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
4533 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
4534 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
4535 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
4536 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
4537 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
4538 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
4539 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
4540 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
4541 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
4542 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
4544 /******************** Bits definition for RTC_ALRMBR register ***************/
4545 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
4546 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
4547 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
4548 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
4549 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
4550 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
4551 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
4552 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
4553 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
4554 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
4555 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
4556 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
4557 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
4558 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
4559 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
4560 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
4561 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
4562 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
4563 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
4564 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
4565 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
4566 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
4567 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
4568 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
4569 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
4570 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
4571 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
4572 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
4573 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
4574 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
4575 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
4576 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
4577 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
4578 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
4579 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
4580 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
4581 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
4582 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
4583 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
4584 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
4586 /******************** Bits definition for RTC_WPR register ******************/
4587 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
4589 /******************** Bits definition for RTC_SSR register ******************/
4590 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
4592 /******************** Bits definition for RTC_SHIFTR register ***************/
4593 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
4594 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
4596 /******************** Bits definition for RTC_TSTR register *****************/
4597 #define RTC_TSTR_PM ((uint32_t)0x00400000)
4598 #define RTC_TSTR_HT ((uint32_t)0x00300000)
4599 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
4600 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
4601 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
4602 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
4603 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
4604 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
4605 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
4606 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
4607 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
4608 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
4609 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
4610 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
4611 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
4612 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
4613 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
4614 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
4615 #define RTC_TSTR_ST ((uint32_t)0x00000070)
4616 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
4617 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
4618 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
4619 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
4620 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
4621 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
4622 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
4623 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
4625 /******************** Bits definition for RTC_TSDR register *****************/
4626 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
4627 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
4628 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
4629 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
4630 #define RTC_TSDR_MT ((uint32_t)0x00001000)
4631 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
4632 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
4633 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
4634 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
4635 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
4636 #define RTC_TSDR_DT ((uint32_t)0x00000030)
4637 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
4638 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
4639 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
4640 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
4641 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
4642 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
4643 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
4645 /******************** Bits definition for RTC_TSSSR register ****************/
4646 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
4648 /******************** Bits definition for RTC_CAL register *****************/
4649 #define RTC_CALR_CALP ((uint32_t)0x00008000)
4650 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
4651 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
4652 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
4653 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
4654 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
4655 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
4656 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
4657 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
4658 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
4659 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
4660 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
4661 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
4663 /******************** Bits definition for RTC_TAFCR register ****************/
4664 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
4665 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
4666 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
4667 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
4668 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
4669 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
4670 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
4671 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
4672 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
4673 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
4674 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
4675 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
4676 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
4677 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
4678 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
4679 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
4680 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
4681 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
4682 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
4683 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
4685 /******************** Bits definition for RTC_ALRMASSR register *************/
4686 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
4687 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
4688 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
4689 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
4690 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
4691 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
4693 /******************** Bits definition for RTC_ALRMBSSR register *************/
4694 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
4695 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
4696 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
4697 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
4698 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
4699 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
4701 /******************** Bits definition for RTC_BKP0R register ****************/
4702 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
4704 /******************** Bits definition for RTC_BKP1R register ****************/
4705 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
4707 /******************** Bits definition for RTC_BKP2R register ****************/
4708 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
4710 /******************** Bits definition for RTC_BKP3R register ****************/
4711 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
4713 /******************** Bits definition for RTC_BKP4R register ****************/
4714 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
4716 /******************** Bits definition for RTC_BKP5R register ****************/
4717 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
4719 /******************** Bits definition for RTC_BKP6R register ****************/
4720 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
4722 /******************** Bits definition for RTC_BKP7R register ****************/
4723 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
4725 /******************** Bits definition for RTC_BKP8R register ****************/
4726 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
4728 /******************** Bits definition for RTC_BKP9R register ****************/
4729 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
4731 /******************** Bits definition for RTC_BKP10R register ***************/
4732 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
4734 /******************** Bits definition for RTC_BKP11R register ***************/
4735 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
4737 /******************** Bits definition for RTC_BKP12R register ***************/
4738 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
4740 /******************** Bits definition for RTC_BKP13R register ***************/
4741 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
4743 /******************** Bits definition for RTC_BKP14R register ***************/
4744 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
4746 /******************** Bits definition for RTC_BKP15R register ***************/
4747 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
4749 /******************** Number of backup registers ******************************/
4750 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
4752 /******************************************************************************/
4754 /* Serial Peripheral Interface (SPI) */
4756 /******************************************************************************/
4757 /******************* Bit definition for SPI_CR1 register ********************/
4758 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
4759 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
4760 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
4761 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
4762 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
4763 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
4764 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
4765 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
4766 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
4767 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
4768 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
4769 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
4770 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
4771 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
4772 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
4773 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
4774 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
4776 /******************* Bit definition for SPI_CR2 register ********************/
4777 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
4778 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
4779 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
4780 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
4781 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
4782 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
4783 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
4784 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
4785 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
4786 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
4787 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
4788 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
4789 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
4790 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
4791 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
4792 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
4794 /******************** Bit definition for SPI_SR register ********************/
4795 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
4796 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
4797 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
4798 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
4799 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
4800 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
4801 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
4802 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
4803 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
4804 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
4805 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
4806 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
4807 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
4808 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
4809 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
4811 /******************** Bit definition for SPI_DR register ********************/
4812 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
4814 /******************* Bit definition for SPI_CRCPR register ******************/
4815 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
4817 /****************** Bit definition for SPI_RXCRCR register ******************/
4818 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
4820 /****************** Bit definition for SPI_TXCRCR register ******************/
4821 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
4823 /****************** Bit definition for SPI_I2SCFGR register *****************/
4824 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
4825 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
4826 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
4827 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
4828 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
4829 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
4830 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4831 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4832 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
4833 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
4834 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4835 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4836 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
4837 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
4839 /****************** Bit definition for SPI_I2SPR register *******************/
4840 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
4841 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
4842 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
4844 /******************************************************************************/
4846 /* System Configuration(SYSCFG) */
4848 /******************************************************************************/
4849 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
4850 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
4851 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4852 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4853 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
4854 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
4855 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
4856 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003800) /*!< DMA remap mask */
4857 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
4858 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
4859 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
4860 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
4861 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
4862 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
4863 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
4864 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
4865 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
4866 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
4867 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
4868 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
4869 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */
4870 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
4871 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
4872 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
4873 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
4874 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
4875 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
4876 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
4878 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
4879 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
4880 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
4881 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
4882 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
4885 * @brief EXTI0 configuration
4887 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
4888 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
4889 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
4890 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
4891 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
4892 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
4895 * @brief EXTI1 configuration
4897 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
4898 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
4899 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
4900 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
4901 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
4902 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
4905 * @brief EXTI2 configuration
4907 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
4908 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
4909 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
4910 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
4911 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
4912 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
4915 * @brief EXTI3 configuration
4917 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
4918 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
4919 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
4920 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
4921 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
4923 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
4924 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
4925 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
4926 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
4927 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
4930 * @brief EXTI4 configuration
4932 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
4933 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
4934 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
4935 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
4936 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
4937 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
4940 * @brief EXTI5 configuration
4942 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
4943 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
4944 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
4945 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
4946 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
4947 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
4950 * @brief EXTI6 configuration
4952 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
4953 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
4954 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
4955 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
4956 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
4957 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
4960 * @brief EXTI7 configuration
4962 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
4963 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
4964 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
4965 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
4966 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
4968 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
4969 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
4970 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
4971 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
4972 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
4975 * @brief EXTI8 configuration
4977 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
4978 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
4979 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
4980 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
4981 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
4984 * @brief EXTI9 configuration
4986 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
4987 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
4988 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
4989 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
4990 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
4991 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
4994 * @brief EXTI10 configuration
4996 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
4997 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
4998 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
4999 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
5000 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
5001 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
5004 * @brief EXTI11 configuration
5006 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
5007 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
5008 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
5009 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
5010 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
5012 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
5013 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
5014 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
5015 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
5016 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
5019 * @brief EXTI12 configuration
5021 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
5022 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
5023 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
5024 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
5025 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
5028 * @brief EXTI13 configuration
5030 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
5031 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
5032 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
5033 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
5034 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
5037 * @brief EXTI14 configuration
5039 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
5040 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
5041 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
5042 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
5043 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
5046 * @brief EXTI15 configuration
5048 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
5049 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
5050 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
5051 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
5052 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
5054 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
5055 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
5056 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
5058 /******************************************************************************/
5062 /******************************************************************************/
5063 /******************* Bit definition for TIM_CR1 register ********************/
5064 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
5065 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
5066 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
5067 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
5068 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
5070 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
5071 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5072 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5074 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
5076 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
5077 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5078 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5080 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
5082 /******************* Bit definition for TIM_CR2 register ********************/
5083 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
5084 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
5085 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
5087 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
5088 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5089 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5090 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5092 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
5093 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
5094 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
5095 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
5096 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
5097 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
5098 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
5099 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
5100 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
5101 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
5103 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
5104 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5105 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5106 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5107 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
5109 /******************* Bit definition for TIM_SMCR register *******************/
5110 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
5111 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5112 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5113 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5114 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5116 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
5118 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
5119 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5120 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5121 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5123 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
5125 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
5126 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5127 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5128 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5129 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5131 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
5132 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5133 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5135 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
5136 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
5138 /******************* Bit definition for TIM_DIER register *******************/
5139 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
5140 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
5141 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
5142 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
5143 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
5144 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
5145 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
5146 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
5147 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
5148 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
5149 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
5150 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
5151 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
5152 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
5153 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
5155 /******************** Bit definition for TIM_SR register ********************/
5156 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
5157 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
5158 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
5159 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
5160 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
5161 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
5162 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
5163 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
5164 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
5165 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
5166 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
5167 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
5168 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
5169 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
5170 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
5172 /******************* Bit definition for TIM_EGR register ********************/
5173 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
5174 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
5175 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
5176 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
5177 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
5178 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
5179 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
5180 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
5181 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
5183 /****************** Bit definition for TIM_CCMR1 register *******************/
5184 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
5185 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5186 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5188 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
5189 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
5191 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
5192 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5193 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5194 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5195 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5197 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
5199 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
5200 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5201 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5203 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
5204 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
5206 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
5207 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5208 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5209 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5210 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5212 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
5214 /*----------------------------------------------------------------------------*/
5216 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
5217 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5218 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5220 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
5221 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5222 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5223 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5224 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5226 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
5227 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5228 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5230 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
5231 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5232 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5233 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5234 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
5236 /****************** Bit definition for TIM_CCMR2 register *******************/
5237 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
5238 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5239 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5241 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
5242 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
5244 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
5245 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5246 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5247 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5248 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5250 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
5252 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
5253 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5254 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5256 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
5257 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
5259 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
5260 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5261 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5262 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5263 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5265 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
5267 /*----------------------------------------------------------------------------*/
5269 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
5270 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
5271 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
5273 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
5274 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
5275 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
5276 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
5277 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
5279 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
5280 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
5281 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
5283 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
5284 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
5285 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
5286 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
5287 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
5289 /******************* Bit definition for TIM_CCER register *******************/
5290 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
5291 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
5292 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
5293 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
5294 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
5295 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
5296 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
5297 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
5298 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
5299 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
5300 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
5301 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
5302 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
5303 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
5304 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
5305 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
5306 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
5307 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
5308 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
5310 /******************* Bit definition for TIM_CNT register ********************/
5311 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
5312 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
5314 /******************* Bit definition for TIM_PSC register ********************/
5315 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
5317 /******************* Bit definition for TIM_ARR register ********************/
5318 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
5320 /******************* Bit definition for TIM_RCR register ********************/
5321 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
5323 /******************* Bit definition for TIM_CCR1 register *******************/
5324 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
5326 /******************* Bit definition for TIM_CCR2 register *******************/
5327 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
5329 /******************* Bit definition for TIM_CCR3 register *******************/
5330 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
5332 /******************* Bit definition for TIM_CCR4 register *******************/
5333 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
5335 /******************* Bit definition for TIM_CCR5 register *******************/
5336 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
5337 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
5338 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
5339 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
5341 /******************* Bit definition for TIM_CCR6 register *******************/
5342 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
5344 /******************* Bit definition for TIM_BDTR register *******************/
5345 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
5346 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5347 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5348 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5349 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5350 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5351 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5352 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5353 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5355 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
5356 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5357 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5359 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
5360 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
5361 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
5362 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
5363 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
5364 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
5366 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
5367 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
5369 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
5370 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
5372 /******************* Bit definition for TIM_DCR register ********************/
5373 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
5374 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5375 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5376 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5377 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5378 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5380 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
5381 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5382 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5383 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5384 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5385 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5387 /******************* Bit definition for TIM_DMAR register *******************/
5388 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
5390 /******************* Bit definition for TIM16_OR register *********************/
5391 #define TIM16_OR_TI1_RMP ((uint32_t)0x000000C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
5392 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000040) /*!<Bit 0 */
5393 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000080) /*!<Bit 1 */
5395 /******************* Bit definition for TIM1_OR register *********************/
5396 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
5397 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5398 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5399 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5400 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5402 /****************** Bit definition for TIM_CCMR3 register *******************/
5403 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
5404 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
5406 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
5407 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5408 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5409 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5410 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5412 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
5414 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
5415 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
5417 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
5418 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5419 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5420 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5421 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5423 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
5425 /******************************************************************************/
5427 /* Touch Sensing Controller (TSC) */
5429 /******************************************************************************/
5430 /******************* Bit definition for TSC_CR register *********************/
5431 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
5432 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
5433 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
5434 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
5435 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
5437 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
5438 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5439 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5440 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
5442 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
5443 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5444 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5445 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5447 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
5448 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
5450 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
5451 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5452 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5453 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5454 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5455 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
5456 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
5457 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
5459 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
5460 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5461 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5462 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5463 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5465 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
5466 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5467 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5468 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
5469 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
5471 /******************* Bit definition for TSC_IER register ********************/
5472 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
5473 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
5475 /******************* Bit definition for TSC_ICR register ********************/
5476 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
5477 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
5479 /******************* Bit definition for TSC_ISR register ********************/
5480 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
5481 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
5483 /******************* Bit definition for TSC_IOHCR register ******************/
5484 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
5485 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
5486 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
5487 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
5488 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
5489 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
5490 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
5491 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
5492 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
5493 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
5494 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
5495 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
5496 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
5497 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
5498 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
5499 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
5500 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
5501 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
5502 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
5503 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
5504 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
5505 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
5506 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
5507 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
5508 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
5509 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
5510 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
5511 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
5512 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
5513 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
5514 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
5515 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
5517 /******************* Bit definition for TSC_IOASCR register *****************/
5518 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
5519 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
5520 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
5521 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
5522 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
5523 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
5524 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
5525 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
5526 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
5527 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
5528 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
5529 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
5530 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
5531 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
5532 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
5533 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
5534 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
5535 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
5536 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
5537 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
5538 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
5539 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
5540 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
5541 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
5542 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
5543 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
5544 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
5545 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
5546 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
5547 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
5548 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
5549 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
5551 /******************* Bit definition for TSC_IOSCR register ******************/
5552 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
5553 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
5554 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
5555 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
5556 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
5557 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
5558 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
5559 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
5560 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
5561 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
5562 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
5563 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
5564 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
5565 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
5566 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
5567 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
5568 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
5569 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
5570 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
5571 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
5572 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
5573 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
5574 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
5575 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
5576 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
5577 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
5578 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
5579 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
5580 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
5581 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
5582 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
5583 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
5585 /******************* Bit definition for TSC_IOCCR register ******************/
5586 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
5587 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
5588 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
5589 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
5590 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
5591 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
5592 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
5593 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
5594 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
5595 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
5596 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
5597 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
5598 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
5599 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
5600 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
5601 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
5602 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
5603 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
5604 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
5605 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
5606 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
5607 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
5608 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
5609 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
5610 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
5611 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
5612 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
5613 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
5614 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
5615 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
5616 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
5617 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
5619 /******************* Bit definition for TSC_IOGCSR register *****************/
5620 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
5621 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
5622 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
5623 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
5624 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
5625 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
5626 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
5627 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
5628 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
5629 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
5630 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
5631 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
5632 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
5633 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
5634 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
5635 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
5637 /******************* Bit definition for TSC_IOGXCR register *****************/
5638 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
5640 /******************************************************************************/
5642 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
5644 /******************************************************************************/
5645 /****************** Bit definition for USART_CR1 register *******************/
5646 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
5647 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
5648 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
5649 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
5650 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
5651 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
5652 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
5653 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
5654 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
5655 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
5656 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
5657 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
5658 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
5659 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
5660 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
5661 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
5662 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
5663 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
5664 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
5665 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
5666 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
5667 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
5668 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
5669 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
5670 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
5671 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
5672 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
5673 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
5674 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
5675 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
5676 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
5677 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
5679 /****************** Bit definition for USART_CR2 register *******************/
5680 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
5681 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
5682 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
5683 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
5684 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
5685 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
5686 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
5687 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
5688 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
5689 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
5690 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
5691 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
5692 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
5693 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
5694 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
5695 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
5696 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
5697 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
5698 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
5699 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
5700 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
5701 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
5703 /****************** Bit definition for USART_CR3 register *******************/
5704 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
5705 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
5706 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
5707 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
5708 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
5709 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
5710 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
5711 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
5712 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
5713 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
5714 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
5715 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
5716 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
5717 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
5718 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
5719 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
5720 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
5721 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
5722 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
5723 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
5724 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
5725 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
5726 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
5727 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
5729 /****************** Bit definition for USART_BRR register *******************/
5730 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
5731 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
5733 /****************** Bit definition for USART_GTPR register ******************/
5734 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
5735 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
5738 /******************* Bit definition for USART_RTOR register *****************/
5739 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
5740 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
5742 /******************* Bit definition for USART_RQR register ******************/
5743 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
5744 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
5745 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
5746 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
5747 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
5749 /******************* Bit definition for USART_ISR register ******************/
5750 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
5751 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
5752 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
5753 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
5754 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
5755 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
5756 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
5757 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
5758 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
5759 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
5760 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
5761 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
5762 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
5763 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
5764 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
5765 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
5766 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
5767 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
5768 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
5769 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
5770 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
5771 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
5773 /******************* Bit definition for USART_ICR register ******************/
5774 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
5775 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
5776 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
5777 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
5778 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
5779 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
5780 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
5781 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
5782 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
5783 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
5784 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
5785 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
5787 /******************* Bit definition for USART_RDR register ******************/
5788 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
5790 /******************* Bit definition for USART_TDR register ******************/
5791 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
5793 /******************************************************************************/
5795 /* USB Device General registers */
5797 /******************************************************************************/
5798 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
5799 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
5800 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
5801 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
5802 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
5803 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
5805 /**************************** ISTR interrupt events *************************/
5806 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
5807 #define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
5808 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
5809 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
5810 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
5811 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
5812 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
5813 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
5814 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
5815 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
5816 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
5818 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
5819 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
5820 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
5821 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
5822 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
5823 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
5824 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
5825 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
5826 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
5828 /************************* CNTR control register bits definitions ***********/
5829 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
5830 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
5831 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
5832 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
5833 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
5834 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
5835 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
5836 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
5837 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
5838 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
5839 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
5840 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
5841 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
5842 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
5843 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
5845 /*************************** LPM register bits definitions ******************/
5846 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
5847 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
5848 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
5849 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
5851 /******************** FNR Frame Number Register bit definitions ************/
5852 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
5853 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
5854 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
5855 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
5856 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
5858 /******************** DADDR Device ADDRess bit definitions ****************/
5859 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
5860 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
5862 /****************************** Endpoint register *************************/
5863 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
5864 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
5865 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
5866 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
5867 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
5868 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
5869 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
5870 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
5872 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
5873 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
5874 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
5875 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
5876 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
5877 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
5878 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
5879 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
5880 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
5881 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
5883 /* EndPoint REGister MASK (no toggle fields) */
5884 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
5885 /*!< EP_TYPE[1:0] EndPoint TYPE */
5886 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
5887 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
5888 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
5889 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
5890 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
5891 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
5893 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
5894 /*!< STAT_TX[1:0] STATus for TX transfer */
5895 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
5896 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
5897 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
5898 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
5899 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
5900 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
5901 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
5902 /*!< STAT_RX[1:0] STATus for RX transfer */
5903 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
5904 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
5905 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
5906 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
5907 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
5908 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
5909 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
5911 /******************************************************************************/
5913 /* Window WATCHDOG */
5915 /******************************************************************************/
5916 /******************* Bit definition for WWDG_CR register ********************/
5917 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
5918 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
5919 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
5920 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
5921 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
5922 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
5923 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
5924 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
5926 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
5928 /******************* Bit definition for WWDG_CFR register *******************/
5929 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
5930 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
5931 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
5932 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
5933 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
5934 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
5935 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
5936 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
5938 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
5939 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
5940 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
5942 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
5944 /******************* Bit definition for WWDG_SR register ********************/
5945 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
5955 /** @addtogroup Exported_macros
5959 /****************************** ADC Instances *********************************/
5960 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
5962 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
5964 /****************************** CAN Instances *********************************/
5965 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
5967 /****************************** COMP Instances ********************************/
5968 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
5969 ((INSTANCE) == COMP4) || \
5970 ((INSTANCE) == COMP6))
5972 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
5973 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
5975 /******************** COMP Instances with window mode capability **************/
5976 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0)
5978 /****************************** CRC Instances *********************************/
5979 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
5981 /****************************** DAC Instances *********************************/
5982 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
5984 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
5985 (((INSTANCE) == DAC1) && \
5986 ((CHANNEL) == DAC_CHANNEL_1))
5988 /****************************** DMA Instances *********************************/
5989 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
5990 ((INSTANCE) == DMA1_Channel2) || \
5991 ((INSTANCE) == DMA1_Channel3) || \
5992 ((INSTANCE) == DMA1_Channel4) || \
5993 ((INSTANCE) == DMA1_Channel5) || \
5994 ((INSTANCE) == DMA1_Channel6) || \
5995 ((INSTANCE) == DMA1_Channel7))
5997 /****************************** GPIO Instances ********************************/
5998 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5999 ((INSTANCE) == GPIOB) || \
6000 ((INSTANCE) == GPIOC) || \
6001 ((INSTANCE) == GPIOD) || \
6002 ((INSTANCE) == GPIOF))
6004 /****************************** I2C Instances *********************************/
6005 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
6006 ((INSTANCE) == I2C2) || \
6007 ((INSTANCE) == I2C3))
6009 /****************************** I2S Instances *********************************/
6010 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
6011 ((INSTANCE) == SPI3))
6013 /****************************** IWDG Instances ********************************/
6014 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
6016 /****************************** OPAMP Instances *******************************/
6017 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
6019 /****************************** RTC Instances *********************************/
6020 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
6022 /****************************** SMBUS Instances *******************************/
6023 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
6024 ((INSTANCE) == I2C2) || \
6025 ((INSTANCE) == I2C3))
6027 /****************************** SPI Instances *********************************/
6028 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
6029 ((INSTANCE) == SPI3))
6031 /******************* TIM Instances : All supported instances ******************/
6032 #define IS_TIM_INSTANCE(INSTANCE)\
6033 (((INSTANCE) == TIM1) || \
6034 ((INSTANCE) == TIM2) || \
6035 ((INSTANCE) == TIM6) || \
6036 ((INSTANCE) == TIM15) || \
6037 ((INSTANCE) == TIM16) || \
6038 ((INSTANCE) == TIM17))
6040 /******************* TIM Instances : at least 1 capture/compare channel *******/
6041 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
6042 (((INSTANCE) == TIM1) || \
6043 ((INSTANCE) == TIM2) || \
6044 ((INSTANCE) == TIM15) || \
6045 ((INSTANCE) == TIM16) || \
6046 ((INSTANCE) == TIM17))
6048 /****************** TIM Instances : at least 2 capture/compare channels *******/
6049 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
6050 (((INSTANCE) == TIM1) || \
6051 ((INSTANCE) == TIM2) || \
6052 ((INSTANCE) == TIM15))
6054 /****************** TIM Instances : at least 3 capture/compare channels *******/
6055 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
6056 (((INSTANCE) == TIM1) || \
6057 ((INSTANCE) == TIM2))
6059 /****************** TIM Instances : at least 4 capture/compare channels *******/
6060 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
6061 (((INSTANCE) == TIM1) || \
6062 ((INSTANCE) == TIM2))
6064 /****************** TIM Instances : at least 5 capture/compare channels *******/
6065 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
6066 (((INSTANCE) == TIM1))
6068 /****************** TIM Instances : at least 6 capture/compare channels *******/
6069 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
6070 (((INSTANCE) == TIM1))
6072 /************************** TIM Instances : Advanced-control timers ***********/
6074 /****************** TIM Instances : supporting clock selection ****************/
6075 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
6076 (((INSTANCE) == TIM1) || \
6077 ((INSTANCE) == TIM2) || \
6078 ((INSTANCE) == TIM15))
6080 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
6081 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
6082 (((INSTANCE) == TIM1) || \
6083 ((INSTANCE) == TIM2))
6085 /****************** TIM Instances : supporting external clock mode 2 **********/
6086 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
6087 (((INSTANCE) == TIM1) || \
6088 ((INSTANCE) == TIM2))
6090 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
6091 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
6092 (((INSTANCE) == TIM1) || \
6093 ((INSTANCE) == TIM2) || \
6094 ((INSTANCE) == TIM15))
6096 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
6097 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
6098 (((INSTANCE) == TIM1) || \
6099 ((INSTANCE) == TIM2) || \
6100 ((INSTANCE) == TIM15))
6102 /****************** TIM Instances : supporting OCxREF clear *******************/
6103 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
6104 (((INSTANCE) == TIM1) || \
6105 ((INSTANCE) == TIM2))
6107 /****************** TIM Instances : supporting encoder interface **************/
6108 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
6109 (((INSTANCE) == TIM1) || \
6110 ((INSTANCE) == TIM2))
6112 /****************** TIM Instances : supporting Hall interface *****************/
6113 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
6114 (((INSTANCE) == TIM1))
6116 /****************** TIM Instances : supporting input XOR function *************/
6117 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
6118 (((INSTANCE) == TIM1) || \
6119 ((INSTANCE) == TIM2) || \
6120 ((INSTANCE) == TIM15))
6122 /****************** TIM Instances : supporting master mode ********************/
6123 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
6124 (((INSTANCE) == TIM1) || \
6125 ((INSTANCE) == TIM2) || \
6126 ((INSTANCE) == TIM6) || \
6127 ((INSTANCE) == TIM15))
6129 /****************** TIM Instances : supporting slave mode *********************/
6130 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
6131 (((INSTANCE) == TIM1) || \
6132 ((INSTANCE) == TIM2) || \
6133 ((INSTANCE) == TIM15))
6135 /****************** TIM Instances : supporting synchronization ****************/
6136 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
6137 (((INSTANCE) == TIM1) || \
6138 ((INSTANCE) == TIM2) || \
6139 ((INSTANCE) == TIM6) || \
6140 ((INSTANCE) == TIM15))
6142 /****************** TIM Instances : supporting 32 bits counter ****************/
6143 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
6144 ((INSTANCE) == TIM2)
6146 /****************** TIM Instances : supporting DMA burst **********************/
6147 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
6148 (((INSTANCE) == TIM1) || \
6149 ((INSTANCE) == TIM2) || \
6150 ((INSTANCE) == TIM15) || \
6151 ((INSTANCE) == TIM16) || \
6152 ((INSTANCE) == TIM17))
6154 /****************** TIM Instances : supporting the break function *************/
6155 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
6156 (((INSTANCE) == TIM1) || \
6157 ((INSTANCE) == TIM15) || \
6158 ((INSTANCE) == TIM16) || \
6159 ((INSTANCE) == TIM17))
6161 /****************** TIM Instances : supporting input/output channel(s) ********/
6162 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
6163 ((((INSTANCE) == TIM1) && \
6164 (((CHANNEL) == TIM_CHANNEL_1) || \
6165 ((CHANNEL) == TIM_CHANNEL_2) || \
6166 ((CHANNEL) == TIM_CHANNEL_3) || \
6167 ((CHANNEL) == TIM_CHANNEL_4) || \
6168 ((CHANNEL) == TIM_CHANNEL_5) || \
6169 ((CHANNEL) == TIM_CHANNEL_6))) \
6171 (((INSTANCE) == TIM2) && \
6172 (((CHANNEL) == TIM_CHANNEL_1) || \
6173 ((CHANNEL) == TIM_CHANNEL_2) || \
6174 ((CHANNEL) == TIM_CHANNEL_3) || \
6175 ((CHANNEL) == TIM_CHANNEL_4))) \
6177 (((INSTANCE) == TIM15) && \
6178 (((CHANNEL) == TIM_CHANNEL_1) || \
6179 ((CHANNEL) == TIM_CHANNEL_2))) \
6181 (((INSTANCE) == TIM16) && \
6182 (((CHANNEL) == TIM_CHANNEL_1))) \
6184 (((INSTANCE) == TIM17) && \
6185 (((CHANNEL) == TIM_CHANNEL_1))))
6187 /****************** TIM Instances : supporting complementary output(s) ********/
6188 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
6189 ((((INSTANCE) == TIM1) && \
6190 (((CHANNEL) == TIM_CHANNEL_1) || \
6191 ((CHANNEL) == TIM_CHANNEL_2) || \
6192 ((CHANNEL) == TIM_CHANNEL_3))) \
6194 (((INSTANCE) == TIM15) && \
6195 ((CHANNEL) == TIM_CHANNEL_1)) \
6197 (((INSTANCE) == TIM16) && \
6198 ((CHANNEL) == TIM_CHANNEL_1)) \
6200 (((INSTANCE) == TIM17) && \
6201 ((CHANNEL) == TIM_CHANNEL_1)))
6203 /****************** TIM Instances : supporting counting mode selection ********/
6204 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
6205 (((INSTANCE) == TIM1) || \
6206 ((INSTANCE) == TIM2))
6208 /****************** TIM Instances : supporting repetition counter *************/
6209 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
6210 (((INSTANCE) == TIM1) || \
6211 ((INSTANCE) == TIM15) || \
6212 ((INSTANCE) == TIM16) || \
6213 ((INSTANCE) == TIM17))
6215 /****************** TIM Instances : supporting clock division *****************/
6216 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
6217 (((INSTANCE) == TIM1) || \
6218 ((INSTANCE) == TIM2) || \
6219 ((INSTANCE) == TIM15) || \
6220 ((INSTANCE) == TIM16) || \
6221 ((INSTANCE) == TIM17))
6223 /****************** TIM Instances : supporting 2 break inputs *****************/
6224 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
6225 (((INSTANCE) == TIM1))
6227 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
6228 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
6229 (((INSTANCE) == TIM1))
6231 /****************** TIM Instances : supporting DMA generation on Update events*/
6232 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
6233 (((INSTANCE) == TIM1) || \
6234 ((INSTANCE) == TIM2) || \
6235 ((INSTANCE) == TIM6) || \
6236 ((INSTANCE) == TIM15) || \
6237 ((INSTANCE) == TIM16) || \
6238 ((INSTANCE) == TIM17))
6240 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
6241 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
6242 (((INSTANCE) == TIM1) || \
6243 ((INSTANCE) == TIM2) || \
6244 ((INSTANCE) == TIM15) || \
6245 ((INSTANCE) == TIM16) || \
6246 ((INSTANCE) == TIM17))
6248 /****************** TIM Instances : supporting commutation event generation ***/
6249 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
6250 (((INSTANCE) == TIM1) || \
6251 ((INSTANCE) == TIM15) || \
6252 ((INSTANCE) == TIM16) || \
6253 ((INSTANCE) == TIM17))
6255 /****************** TIM Instances : supporting remapping capability ***********/
6256 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
6257 (((INSTANCE) == TIM1) || \
6258 ((INSTANCE) == TIM16))
6260 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
6261 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
6262 (((INSTANCE) == TIM1))
6264 /****************************** TSC Instances *********************************/
6265 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
6267 /******************** USART Instances : Synchronous mode **********************/
6268 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6269 ((INSTANCE) == USART2) || \
6270 ((INSTANCE) == USART3))
6272 /****************** USART Instances : Auto Baud Rate detection ****************/
6273 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
6275 /******************** UART Instances : Asynchronous mode **********************/
6276 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6277 ((INSTANCE) == USART2) || \
6278 ((INSTANCE) == USART3))
6280 /******************** UART Instances : Half-Duplex mode **********************/
6281 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6282 ((INSTANCE) == USART2) || \
6283 ((INSTANCE) == USART3))
6285 /******************** UART Instances : LIN mode **********************/
6286 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
6288 /******************** UART Instances : Wake-up from Stop mode **********************/
6289 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
6291 /****************** UART Instances : Hardware Flow control ********************/
6292 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6293 ((INSTANCE) == USART2) || \
6294 ((INSTANCE) == USART3))
6296 /****************** UART Instances : Auto Baud Rate detection *****************/
6297 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6298 ((INSTANCE) == USART2) || \
6299 ((INSTANCE) == USART3))
6301 /********************* UART Instances : Smard card mode ***********************/
6302 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
6304 /*********************** UART Instances : IRDA mode ***************************/
6305 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
6307 /****************************** USB Instances *********************************/
6308 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
6310 /****************************** WWDG Instances ********************************/
6311 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
6318 /******************************************************************************/
6319 /* For a painless codes migration between the STM32F3xx device product */
6320 /* lines, the aliases defined below are put in place to overcome the */
6321 /* differences in the interrupt handlers and IRQn definitions. */
6322 /* No need to update developed interrupt code when moving across */
6323 /* product lines within the same STM32F3 Family */
6324 /******************************************************************************/
6326 /* Aliases for __IRQn */
6328 #define ADC1_2_IRQn ADC1_IRQn
6329 #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
6330 #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
6331 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
6332 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
6333 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
6334 #define COMP_IRQn COMP2_IRQn
6335 #define COMP1_2_IRQn COMP2_IRQn
6336 #define COMP1_2_3_IRQn COMP2_IRQn
6337 #define COMP4_5_6_IRQn COMP4_6_IRQn
6338 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn
6340 /* Aliases for __IRQHandler */
6341 #define ADC1_2_IRQHandler ADC1_IRQHandler
6342 #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
6343 #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
6344 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
6345 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
6346 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
6347 #define COMP_IRQHandler COMP2_IRQHandler
6348 #define COMP1_2_IRQHandler COMP2_IRQHandler
6349 #define COMP1_2_3_IRQHandler COMP2_IRQHandler
6350 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
6351 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
6355 #endif /* __cplusplus */
6357 #endif /* __STM32F302x8_H */
6367 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/