2 ******************************************************************************
4 * @author MCD Application Team
7 * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral
\92s registers hardware
14 ******************************************************************************
17 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 ******************************************************************************
44 /** @addtogroup CMSIS_Device
48 /** @addtogroup stm32f303xe
52 #ifndef __STM32F303xE_H
53 #define __STM32F303xE_H
57 #endif /* __cplusplus */
59 /** @addtogroup Configuration_section_for_CMSIS
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
67 #define __MPU_PRESENT 1 /*!< STM32F303xE devices provide an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< STM32F303xE devices provide an FPU */
76 /** @addtogroup Peripheral_interrupt_number_definition
81 * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
101 RCC_IRQn = 5, /*!< RCC global Interrupt */
102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
115 USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
116 USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
133 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
134 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
135 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
138 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
139 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
140 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
141 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
143 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
144 FMC_IRQn = 48, /*!< FMC global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
150 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
151 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
152 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
153 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
154 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
155 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
156 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
157 COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
158 COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
159 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
160 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
161 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
162 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
163 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
164 TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
165 TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
166 TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
167 TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
168 FPU_IRQn = 81, /*!< Floating point Interrupt */
169 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
176 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
177 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
180 /** @addtogroup Peripheral_registers_structures
185 * @brief Analog to Digital Converter
190 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
191 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
192 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
193 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
194 uint32_t RESERVED0; /*!< Reserved, 0x010 */
195 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
196 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
197 uint32_t RESERVED1; /*!< Reserved, 0x01C */
198 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
199 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
200 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
201 uint32_t RESERVED2; /*!< Reserved, 0x02C */
202 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
203 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
204 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
205 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
206 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
207 uint32_t RESERVED3; /*!< Reserved, 0x044 */
208 uint32_t RESERVED4; /*!< Reserved, 0x048 */
209 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
210 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
211 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
212 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
213 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
214 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
215 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
216 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
217 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
218 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
219 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
220 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
221 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
222 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
223 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
224 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
225 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
226 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
233 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
234 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
235 __IO uint32_t CDR; /*!< ADC common regular data register for dual
236 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
237 } ADC_Common_TypeDef;
240 * @brief Controller Area Network TxMailBox
244 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
245 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
246 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
247 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
248 } CAN_TxMailBox_TypeDef;
251 * @brief Controller Area Network FIFOMailBox
255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
259 } CAN_FIFOMailBox_TypeDef;
262 * @brief Controller Area Network FilterRegister
266 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
267 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
268 } CAN_FilterRegister_TypeDef;
271 * @brief Controller Area Network
275 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
276 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
277 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
278 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
279 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
280 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
281 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
282 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
283 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
284 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
285 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
286 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
287 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
288 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
289 uint32_t RESERVED2; /*!< Reserved, 0x208 */
290 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
291 uint32_t RESERVED3; /*!< Reserved, 0x210 */
292 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
293 uint32_t RESERVED4; /*!< Reserved, 0x218 */
294 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
295 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
296 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
300 * @brief Analog Comparators
305 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
309 * @brief CRC calculation unit
314 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
315 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
316 uint8_t RESERVED0; /*!< Reserved, 0x05 */
317 uint16_t RESERVED1; /*!< Reserved, 0x06 */
318 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
319 uint32_t RESERVED2; /*!< Reserved, 0x0C */
320 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
321 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
325 * @brief Digital to Analog Converter
330 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
331 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
332 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
333 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
334 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
335 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
336 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
337 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
338 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
339 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
340 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
341 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
342 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
343 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
352 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
353 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
354 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
355 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
359 * @brief DMA Controller
364 __IO uint32_t CCR; /*!< DMA channel x configuration register */
365 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
366 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
367 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
368 } DMA_Channel_TypeDef;
372 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
373 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
377 * @brief External Interrupt/Event Controller
382 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
383 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
384 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
385 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
386 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
387 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
388 uint32_t RESERVED1; /*!< Reserved, 0x18 */
389 uint32_t RESERVED2; /*!< Reserved, 0x1C */
390 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
391 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
392 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
393 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
394 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
395 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
399 * @brief FLASH Registers
404 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
405 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
406 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
407 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
408 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
409 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
410 uint32_t RESERVED; /*!< Reserved, 0x18 */
411 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
412 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
417 * @brief Flexible Memory Controller
422 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
426 * @brief Flexible Memory Controller Bank1E
431 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
432 } FMC_Bank1E_TypeDef;
435 * @brief Flexible Memory Controller Bank2
440 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
441 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
442 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
443 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
444 uint32_t RESERVED0; /*!< Reserved, 0x70 */
445 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
446 uint32_t RESERVED1; /*!< Reserved, 0x78 */
447 uint32_t RESERVED2; /*!< Reserved, 0x7C */
448 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
449 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
450 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
451 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
452 uint32_t RESERVED3; /*!< Reserved, 0x90 */
453 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
454 } FMC_Bank2_3_TypeDef;
457 * @brief Flexible Memory Controller Bank4
462 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
463 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
464 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
465 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
466 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
470 * @brief Option Bytes Registers
474 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
475 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
476 uint16_t RESERVED0; /*!< Reserved, 0x04 */
477 uint16_t RESERVED1; /*!< Reserved, 0x06 */
478 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
479 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
480 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
481 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
485 * @brief General Purpose I/O
490 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
491 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
492 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
493 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
494 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
495 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
496 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
497 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
498 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
499 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
500 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
504 * @brief Operational Amplifier (OPAMP)
509 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
513 * @brief System configuration controller
518 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
519 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
520 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
521 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
522 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
523 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
524 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
525 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
526 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
527 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
528 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
529 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
530 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
531 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
532 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
533 __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */
534 __IO uint32_t RESERVED12; /*!< Reserved, 0x4C */
535 __IO uint32_t RESERVED13; /*!< Reserved, 0x50 */
539 * @brief Inter-integrated Circuit Interface
544 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
545 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
546 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
547 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
548 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
549 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
550 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
551 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
552 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
553 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
554 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
558 * @brief Independent WATCHDOG
563 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
564 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
565 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
566 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
567 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
571 * @brief Power Control
576 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
577 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
581 * @brief Reset and Clock Control
585 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
586 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
587 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
588 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
589 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
590 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
591 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
592 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
593 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
594 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
595 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
596 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
597 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
601 * @brief Real-Time Clock
606 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
607 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
608 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
609 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
610 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
611 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
612 uint32_t RESERVED0; /*!< Reserved, 0x18 */
613 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
614 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
615 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
616 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
617 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
618 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
619 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
620 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
621 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
622 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
623 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
624 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
625 uint32_t RESERVED7; /*!< Reserved, 0x4C */
626 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
627 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
628 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
629 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
630 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
631 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
632 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
633 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
634 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
635 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
636 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
637 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
638 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
639 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
640 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
641 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
646 * @brief Serial Peripheral Interface
651 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
652 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
653 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
654 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
655 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
656 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
657 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
658 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
659 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
667 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
668 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
669 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
670 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
671 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
672 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
673 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
674 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
675 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
676 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
677 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
678 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
679 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
680 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
681 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
682 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
683 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
684 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
685 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
686 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
687 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
688 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
689 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
690 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
694 * @brief Touch Sensing Controller (TSC)
698 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
699 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
700 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
701 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
702 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
703 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
704 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
705 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
706 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
707 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
708 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
709 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
710 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
711 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
715 * @brief Universal Synchronous Asynchronous Receiver Transmitter
720 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
721 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
722 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
723 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
724 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
725 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
726 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
727 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
728 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
729 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
730 uint16_t RESERVED1; /*!< Reserved, 0x26 */
731 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
732 uint16_t RESERVED2; /*!< Reserved, 0x2A */
736 * @brief Universal Serial Bus Full Speed Device
741 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
742 __IO uint16_t RESERVED0; /*!< Reserved */
743 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
744 __IO uint16_t RESERVED1; /*!< Reserved */
745 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
746 __IO uint16_t RESERVED2; /*!< Reserved */
747 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
748 __IO uint16_t RESERVED3; /*!< Reserved */
749 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
750 __IO uint16_t RESERVED4; /*!< Reserved */
751 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
752 __IO uint16_t RESERVED5; /*!< Reserved */
753 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
754 __IO uint16_t RESERVED6; /*!< Reserved */
755 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
756 __IO uint16_t RESERVED7[17]; /*!< Reserved */
757 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
758 __IO uint16_t RESERVED8; /*!< Reserved */
759 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
760 __IO uint16_t RESERVED9; /*!< Reserved */
761 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
762 __IO uint16_t RESERVEDA; /*!< Reserved */
763 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
764 __IO uint16_t RESERVEDB; /*!< Reserved */
765 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
766 __IO uint16_t RESERVEDC; /*!< Reserved */
767 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
768 __IO uint16_t RESERVEDD; /*!< Reserved */
772 * @brief Window WATCHDOG
776 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
777 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
778 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
781 /** @addtogroup Peripheral_memory_map
785 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(512KB) base address in the alias region */
786 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(16 KB) base address in the alias region */
787 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(64KB) base address in the alias region */
788 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
789 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
791 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(16 KB) base address in the bit-band region */
792 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(64KB) base address in the bit-band region */
793 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
796 /*!< Peripheral memory map */
797 #define APB1PERIPH_BASE PERIPH_BASE
798 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
799 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
800 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
801 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
803 /*!< APB1 peripherals */
804 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
805 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
806 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
807 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
808 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
809 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
810 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
811 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
812 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
813 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
814 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
815 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
816 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
817 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
818 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
819 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
820 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
821 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
822 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
823 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
824 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
825 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
826 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
827 #define DAC_BASE DAC1_BASE
828 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
830 /*!< APB2 peripherals */
831 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
832 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
833 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
834 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
835 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
836 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
837 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
838 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
839 #define COMP_BASE COMP1_BASE
840 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
841 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
842 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
843 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
844 #define OPAMP_BASE OPAMP1_BASE
845 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
846 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
847 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
848 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
849 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
850 #define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00)
851 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
852 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
853 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
854 #define TIM20_BASE (APB2PERIPH_BASE + 0x00005000)
856 /*!< AHB1 peripherals */
857 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
858 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
859 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
860 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
861 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
862 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
863 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
864 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
865 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
866 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
867 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
868 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
869 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
870 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
871 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
872 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
873 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
874 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
875 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
877 /*!< AHB2 peripherals */
878 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
879 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
880 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
881 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
882 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
883 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
884 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800)
885 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00)
887 /*!< AHB3 peripherals */
888 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
889 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
890 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
891 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400)
892 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
893 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
895 /*!< FMC Bankx registers base address */
896 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
897 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
898 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
899 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
901 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
906 /** @addtogroup Peripheral_declaration
909 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
910 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
911 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
912 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
913 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
914 #define RTC ((RTC_TypeDef *) RTC_BASE)
915 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
916 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
917 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
918 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
919 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
920 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
921 #define USART2 ((USART_TypeDef *) USART2_BASE)
922 #define USART3 ((USART_TypeDef *) USART3_BASE)
923 #define UART4 ((USART_TypeDef *) UART4_BASE)
924 #define UART5 ((USART_TypeDef *) UART5_BASE)
925 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
926 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
927 #define CAN ((CAN_TypeDef *) CAN_BASE)
928 #define PWR ((PWR_TypeDef *) PWR_BASE)
929 #define DAC ((DAC_TypeDef *) DAC_BASE)
930 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
931 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
932 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
933 #define COMP ((COMP_TypeDef *) COMP_BASE)
934 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
935 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
936 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
937 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
938 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
939 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
940 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
941 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
942 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
943 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
944 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
945 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
946 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
947 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
948 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
949 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
950 #define USART1 ((USART_TypeDef *) USART1_BASE)
951 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
952 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
953 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
954 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
955 #define TIM20 ((TIM_TypeDef *) TIM20_BASE)
956 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
957 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
958 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
959 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
960 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
961 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
962 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
963 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
964 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
965 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
966 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
967 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
968 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
969 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
970 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
971 #define RCC ((RCC_TypeDef *) RCC_BASE)
972 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
973 #define OB ((OB_TypeDef *) OB_BASE)
974 #define CRC ((CRC_TypeDef *) CRC_BASE)
975 #define TSC ((TSC_TypeDef *) TSC_BASE)
976 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
977 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
978 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
979 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
980 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
981 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
982 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
983 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
984 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
985 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
986 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
987 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
988 #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
989 #define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
990 #define USB ((USB_TypeDef *) USB_BASE)
991 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
992 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
993 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
994 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1000 /** @addtogroup Exported_constants
1004 /** @addtogroup Peripheral_Registers_Bits_Definition
1008 /******************************************************************************/
1009 /* Peripheral Registers_Bits_Definition */
1010 /******************************************************************************/
1012 /******************************************************************************/
1014 /* Analog to Digital Converter SAR (ADC) */
1016 /******************************************************************************/
1017 /******************** Bit definition for ADC_ISR register ********************/
1018 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
1019 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
1020 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
1021 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
1022 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
1023 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
1024 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
1025 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
1026 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
1027 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
1028 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
1030 /******************** Bit definition for ADC_IER register ********************/
1031 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
1032 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
1033 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
1034 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
1035 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
1036 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
1037 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
1038 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
1039 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
1040 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
1041 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
1043 /******************** Bit definition for ADC_CR register ********************/
1044 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
1045 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
1046 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
1047 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
1048 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
1049 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
1050 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
1051 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
1052 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
1053 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
1054 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
1056 /******************** Bit definition for ADC_CFGR register ********************/
1057 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
1058 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
1060 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
1061 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
1062 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
1064 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
1066 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
1067 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
1068 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
1069 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
1070 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
1072 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
1073 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
1074 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
1076 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
1077 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
1078 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
1079 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
1080 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
1082 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
1083 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
1084 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
1085 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
1087 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
1088 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
1089 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
1090 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
1091 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
1092 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
1094 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
1095 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
1096 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
1097 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
1098 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
1099 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
1101 /******************** Bit definition for ADC_SMPR1 register ********************/
1102 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
1103 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
1104 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
1105 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
1107 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
1108 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
1109 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
1110 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
1112 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
1113 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
1114 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
1115 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
1117 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
1118 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
1119 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
1120 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
1122 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
1123 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
1124 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
1125 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
1127 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
1128 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
1129 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
1130 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
1132 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
1133 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
1134 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
1135 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
1137 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
1138 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
1139 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
1140 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
1142 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
1143 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
1144 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
1145 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
1147 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
1148 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
1149 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
1150 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
1152 /******************** Bit definition for ADC_SMPR2 register ********************/
1153 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
1154 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
1155 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
1156 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
1158 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
1159 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
1160 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
1161 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
1163 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
1164 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
1165 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
1166 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
1168 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
1169 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
1170 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
1171 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
1173 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
1174 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
1175 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
1176 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
1178 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
1179 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
1180 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
1181 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
1183 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
1184 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
1185 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
1186 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
1188 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
1189 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
1190 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
1191 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
1193 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
1194 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
1195 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
1196 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
1198 /******************** Bit definition for ADC_TR1 register ********************/
1199 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
1200 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
1201 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
1202 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
1203 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
1204 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
1205 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
1206 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
1207 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
1208 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
1209 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
1210 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
1211 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
1213 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
1214 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
1215 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
1216 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
1217 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
1218 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
1219 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
1220 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
1221 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
1222 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
1223 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
1224 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
1225 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
1227 /******************** Bit definition for ADC_TR2 register ********************/
1228 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
1229 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
1230 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
1231 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
1232 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
1233 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
1234 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
1235 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
1236 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
1238 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
1239 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
1240 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
1241 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
1242 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
1243 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
1244 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
1245 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
1246 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
1248 /******************** Bit definition for ADC_TR3 register ********************/
1249 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
1250 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
1251 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
1252 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
1253 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
1254 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
1255 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
1256 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
1257 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
1259 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
1260 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
1261 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
1262 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
1263 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
1264 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
1265 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
1266 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
1267 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
1269 /******************** Bit definition for ADC_SQR1 register ********************/
1270 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
1271 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
1272 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
1273 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
1274 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
1276 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
1277 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
1278 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
1279 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
1280 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
1281 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
1283 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
1284 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
1285 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
1286 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
1287 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
1288 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
1290 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
1291 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
1292 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
1293 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
1294 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
1295 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
1297 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
1298 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
1299 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
1300 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
1301 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
1302 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
1304 /******************** Bit definition for ADC_SQR2 register ********************/
1305 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
1306 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
1307 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
1308 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
1309 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
1310 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
1312 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
1313 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
1314 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
1315 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
1316 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
1317 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
1319 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
1320 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
1321 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
1322 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
1323 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
1324 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
1326 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
1327 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
1328 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
1329 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
1330 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
1331 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
1333 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
1334 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
1335 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
1336 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
1337 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
1338 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
1340 /******************** Bit definition for ADC_SQR3 register ********************/
1341 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
1342 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
1343 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
1344 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
1345 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
1346 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
1348 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
1349 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
1350 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
1351 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
1352 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
1353 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
1355 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
1356 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
1357 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
1358 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
1359 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
1360 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
1362 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
1363 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
1364 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
1365 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
1366 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
1367 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
1369 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
1370 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
1371 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
1372 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
1373 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
1374 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
1376 /******************** Bit definition for ADC_SQR4 register ********************/
1377 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
1378 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
1379 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
1380 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
1381 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
1382 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
1384 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
1385 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
1386 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
1387 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
1388 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
1389 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
1390 /******************** Bit definition for ADC_DR register ********************/
1391 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
1392 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
1393 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
1394 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
1395 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
1396 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
1397 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
1398 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
1399 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
1400 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
1401 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
1402 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
1403 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
1404 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
1405 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
1406 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
1407 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
1409 /******************** Bit definition for ADC_JSQR register ********************/
1410 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
1411 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
1412 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
1414 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
1415 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
1416 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
1417 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
1418 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
1420 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
1421 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
1422 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
1424 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
1425 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
1426 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
1427 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
1428 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
1429 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
1431 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
1432 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
1433 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
1434 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
1435 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
1436 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
1438 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
1439 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
1440 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
1441 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
1442 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
1443 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
1445 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
1446 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
1447 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
1448 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
1449 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
1450 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
1452 /******************** Bit definition for ADC_OFR1 register ********************/
1453 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
1454 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
1455 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
1456 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
1457 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
1458 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
1459 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
1460 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
1461 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
1462 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
1463 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
1464 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
1465 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
1467 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
1468 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
1469 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
1470 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
1471 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
1472 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
1474 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
1476 /******************** Bit definition for ADC_OFR2 register ********************/
1477 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
1478 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
1479 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
1480 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
1481 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
1482 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
1483 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
1484 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
1485 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
1486 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
1487 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
1488 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
1489 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
1491 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
1492 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
1493 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
1494 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
1495 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
1496 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
1498 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
1500 /******************** Bit definition for ADC_OFR3 register ********************/
1501 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
1502 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
1503 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
1504 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
1505 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
1506 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
1507 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
1508 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
1509 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
1510 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
1511 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
1512 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
1513 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
1515 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
1516 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
1517 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
1518 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
1519 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
1520 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
1522 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
1524 /******************** Bit definition for ADC_OFR4 register ********************/
1525 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
1526 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
1527 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
1528 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
1529 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
1530 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
1531 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
1532 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
1533 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
1534 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
1535 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
1536 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
1537 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
1539 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
1540 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
1541 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
1542 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
1543 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
1544 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
1546 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
1548 /******************** Bit definition for ADC_JDR1 register ********************/
1549 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1550 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1551 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1552 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1553 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1554 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1555 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1556 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1557 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1558 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1559 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1560 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1561 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1562 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1563 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1564 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1565 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1567 /******************** Bit definition for ADC_JDR2 register ********************/
1568 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1569 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1570 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1571 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1572 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1573 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1574 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1575 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1576 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1577 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1578 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1579 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1580 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1581 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1582 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1583 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1584 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1586 /******************** Bit definition for ADC_JDR3 register ********************/
1587 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1588 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1589 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1590 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1591 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1592 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1593 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1594 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1595 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1596 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1597 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1598 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1599 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1600 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1601 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1602 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1603 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1605 /******************** Bit definition for ADC_JDR4 register ********************/
1606 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1607 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1608 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1609 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1610 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1611 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1612 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1613 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1614 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1615 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1616 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1617 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1618 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1619 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1620 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1621 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1622 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1624 /******************** Bit definition for ADC_AWD2CR register ********************/
1625 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
1626 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
1627 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
1628 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
1629 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
1630 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
1631 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
1632 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
1633 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
1634 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
1635 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
1636 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
1637 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
1638 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
1639 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
1640 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
1641 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
1642 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
1643 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
1645 /******************** Bit definition for ADC_AWD3CR register ********************/
1646 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
1647 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
1648 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
1649 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
1650 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
1651 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
1652 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
1653 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
1654 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
1655 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
1656 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
1657 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
1658 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
1659 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
1660 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
1661 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
1662 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
1663 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
1664 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
1666 /******************** Bit definition for ADC_DIFSEL register ********************/
1667 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
1668 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
1669 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
1670 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
1671 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
1672 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
1673 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
1674 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
1675 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
1676 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
1677 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
1678 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
1679 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
1680 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
1681 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
1682 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
1683 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
1684 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
1685 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
1687 /******************** Bit definition for ADC_CALFACT register ********************/
1688 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
1689 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
1690 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
1691 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
1692 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
1693 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
1694 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
1695 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
1696 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
1697 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
1698 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
1699 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
1700 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
1701 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
1702 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
1703 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
1705 /************************* ADC Common registers *****************************/
1706 /******************** Bit definition for ADC12_CSR register ********************/
1707 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
1708 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
1709 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
1710 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
1711 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
1712 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
1713 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
1714 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
1715 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
1716 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
1717 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
1718 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
1719 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
1720 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
1721 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
1722 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
1723 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
1724 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
1725 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
1726 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
1727 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
1728 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
1730 /******************** Bit definition for ADC34_CSR register ********************/
1731 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
1732 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
1733 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
1734 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
1735 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
1736 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
1737 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
1738 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
1739 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
1740 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
1741 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
1742 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
1743 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
1744 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
1745 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
1746 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
1747 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
1748 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
1749 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
1750 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
1751 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
1752 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
1754 /******************** Bit definition for ADC_CCR register ********************/
1755 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
1756 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
1757 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
1758 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
1759 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
1760 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
1761 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
1762 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
1763 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
1764 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
1765 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
1766 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
1767 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
1768 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
1769 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
1770 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
1771 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
1772 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
1773 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
1774 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
1775 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
1777 /******************** Bit definition for ADC_CCR register ********************/
1778 #define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
1779 #define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
1780 #define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
1781 #define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
1782 #define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
1783 #define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
1785 #define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
1786 #define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
1787 #define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
1788 #define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
1789 #define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
1791 #define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
1792 #define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
1793 #define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
1794 #define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
1796 #define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
1797 #define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
1798 #define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
1800 #define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
1801 #define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
1802 #define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
1804 /******************** Bit definition for ADC_CDR register ********************/
1805 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
1806 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
1807 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
1808 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
1809 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
1810 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
1811 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
1812 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
1813 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
1814 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
1815 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
1816 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
1817 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
1818 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
1819 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
1820 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
1821 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
1823 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
1824 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
1825 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
1826 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
1827 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
1828 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
1829 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
1830 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
1831 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
1832 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
1833 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
1834 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
1835 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
1836 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
1837 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
1838 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
1839 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
1841 /******************** Bit definition for ADC_CDR register ********************/
1842 #define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
1843 #define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
1844 #define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
1845 #define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
1846 #define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
1847 #define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
1848 #define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
1849 #define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
1850 #define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
1851 #define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
1852 #define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
1853 #define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
1854 #define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
1855 #define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
1856 #define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
1857 #define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
1858 #define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
1860 #define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
1861 #define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
1862 #define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
1863 #define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
1864 #define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
1865 #define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
1866 #define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
1867 #define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
1868 #define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
1869 #define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
1870 #define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
1871 #define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
1872 #define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
1873 #define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
1874 #define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
1875 #define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
1876 #define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
1878 /******************************************************************************/
1880 /* Analog Comparators (COMP) */
1882 /******************************************************************************/
1883 /********************** Bit definition for COMP1_CSR register ***************/
1884 #define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
1885 #define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
1886 #define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
1887 #define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
1888 #define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
1889 #define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
1890 #define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
1891 #define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
1892 #define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
1893 #define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
1894 #define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
1895 #define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
1896 #define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
1897 #define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
1898 #define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
1899 #define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
1900 #define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
1901 #define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
1903 /********************** Bit definition for COMP2_CSR register ***************/
1904 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
1905 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
1906 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
1907 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
1908 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
1909 #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
1910 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
1911 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
1912 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
1913 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
1914 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
1915 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
1916 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
1917 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
1918 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
1919 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
1920 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
1921 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
1923 /********************** Bit definition for COMP3_CSR register ***************/
1924 #define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
1925 #define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
1926 #define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
1927 #define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
1928 #define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
1929 #define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
1930 #define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
1931 #define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
1932 #define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
1933 #define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
1934 #define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
1935 #define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
1936 #define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
1937 #define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
1938 #define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
1939 #define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
1940 #define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
1942 /********************** Bit definition for COMP4_CSR register ***************/
1943 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
1944 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
1945 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
1946 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
1947 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
1948 #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
1949 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
1950 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
1951 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
1952 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
1953 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
1954 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
1955 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
1956 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
1957 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
1958 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
1959 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
1960 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
1962 /********************** Bit definition for COMP5_CSR register ***************/
1963 #define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
1964 #define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
1965 #define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
1966 #define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
1967 #define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
1968 #define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
1969 #define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
1970 #define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
1971 #define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
1972 #define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
1973 #define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
1974 #define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
1975 #define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
1976 #define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
1977 #define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
1978 #define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
1979 #define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
1981 /********************** Bit definition for COMP6_CSR register ***************/
1982 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
1983 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
1984 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
1985 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
1986 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
1987 #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
1988 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
1989 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
1990 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
1991 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
1992 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
1993 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
1994 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
1995 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
1996 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
1997 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
1998 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
1999 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
2001 /********************** Bit definition for COMP7_CSR register ***************/
2002 #define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
2003 #define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
2004 #define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
2005 #define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
2006 #define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
2007 #define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
2008 #define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
2009 #define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
2010 #define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
2011 #define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
2012 #define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
2013 #define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
2014 #define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
2015 #define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
2016 #define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
2017 #define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
2018 #define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
2020 /********************** Bit definition for COMP_CSR register ****************/
2021 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
2022 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
2023 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
2024 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
2025 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
2026 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
2027 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
2028 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
2029 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
2030 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
2031 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
2032 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
2033 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
2034 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
2035 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
2036 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
2037 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
2038 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
2040 /******************************************************************************/
2042 /* Operational Amplifier (OPAMP) */
2044 /******************************************************************************/
2045 /********************* Bit definition for OPAMP1_CSR register ***************/
2046 #define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
2047 #define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2048 #define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2049 #define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2050 #define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2051 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2052 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2053 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2054 #define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2055 #define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2056 #define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2057 #define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2058 #define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2059 #define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2060 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2061 #define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2062 #define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2063 #define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2064 #define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2065 #define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2066 #define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2067 #define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2068 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2069 #define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2070 #define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2071 #define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2072 #define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2073 #define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2075 /********************* Bit definition for OPAMP2_CSR register ***************/
2076 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
2077 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2078 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2079 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2080 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2081 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2082 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2083 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2084 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2085 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2086 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2087 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2088 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2089 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2090 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2091 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2092 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2093 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2094 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2095 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2096 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2097 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2098 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2099 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2100 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2101 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2102 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2103 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2105 /********************* Bit definition for OPAMP3_CSR register ***************/
2106 #define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
2107 #define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2108 #define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2109 #define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2110 #define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2111 #define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2112 #define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2113 #define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2114 #define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2115 #define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2116 #define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2117 #define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2118 #define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2119 #define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2120 #define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2121 #define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2122 #define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2123 #define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2124 #define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2125 #define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2126 #define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2127 #define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2128 #define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2129 #define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2130 #define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2131 #define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2132 #define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2133 #define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2135 /********************* Bit definition for OPAMP4_CSR register ***************/
2136 #define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
2137 #define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2138 #define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2139 #define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2140 #define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2141 #define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2142 #define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2143 #define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2144 #define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2145 #define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2146 #define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2147 #define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2148 #define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2149 #define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2150 #define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2151 #define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2152 #define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2153 #define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2154 #define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2155 #define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2156 #define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2157 #define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2158 #define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2159 #define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2160 #define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2161 #define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2162 #define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2163 #define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2165 /********************* Bit definition for OPAMPx_CSR register ***************/
2166 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
2167 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2168 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2169 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2170 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2171 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2172 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2173 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2174 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2175 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2176 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2177 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2178 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2179 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2180 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2181 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2182 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2183 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2184 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2185 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2186 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2187 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2188 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2189 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2190 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2191 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2192 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2193 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2195 /******************************************************************************/
2197 /* Controller Area Network (CAN ) */
2199 /******************************************************************************/
2200 /******************* Bit definition for CAN_MCR register ********************/
2201 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
2202 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
2203 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
2204 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
2205 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
2206 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
2207 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
2208 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
2209 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
2211 /******************* Bit definition for CAN_MSR register ********************/
2212 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
2213 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
2214 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
2215 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
2216 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
2217 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
2218 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
2219 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
2220 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
2222 /******************* Bit definition for CAN_TSR register ********************/
2223 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
2224 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
2225 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
2226 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
2227 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
2228 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
2229 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
2230 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
2231 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
2232 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
2233 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
2234 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
2235 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
2236 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
2237 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
2238 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
2240 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
2241 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
2242 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
2243 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
2245 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
2246 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
2247 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
2248 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
2250 /******************* Bit definition for CAN_RF0R register *******************/
2251 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
2252 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
2253 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
2254 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
2256 /******************* Bit definition for CAN_RF1R register *******************/
2257 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
2258 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
2259 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
2260 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
2262 /******************** Bit definition for CAN_IER register *******************/
2263 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
2264 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
2265 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
2266 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
2267 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
2268 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
2269 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
2270 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
2271 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
2272 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
2273 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
2274 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
2275 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
2276 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
2278 /******************** Bit definition for CAN_ESR register *******************/
2279 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
2280 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
2281 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
2283 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
2284 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2285 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2286 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2288 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
2289 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
2291 /******************* Bit definition for CAN_BTR register ********************/
2292 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
2293 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
2294 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
2295 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
2296 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
2297 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
2298 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
2299 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
2300 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
2301 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
2302 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
2303 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
2304 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
2305 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
2306 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
2308 /*!<Mailbox registers */
2309 /****************** Bit definition for CAN_TI0R register ********************/
2310 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
2311 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2312 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2313 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
2314 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2316 /****************** Bit definition for CAN_TDT0R register *******************/
2317 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2318 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
2319 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2321 /****************** Bit definition for CAN_TDL0R register *******************/
2322 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2323 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2324 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2325 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2327 /****************** Bit definition for CAN_TDH0R register *******************/
2328 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2329 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2330 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2331 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2333 /******************* Bit definition for CAN_TI1R register *******************/
2334 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
2335 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2336 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2337 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
2338 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2340 /******************* Bit definition for CAN_TDT1R register ******************/
2341 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2342 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
2343 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2345 /******************* Bit definition for CAN_TDL1R register ******************/
2346 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2347 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2348 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2349 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2351 /******************* Bit definition for CAN_TDH1R register ******************/
2352 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2353 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2354 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2355 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2357 /******************* Bit definition for CAN_TI2R register *******************/
2358 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
2359 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2360 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2361 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
2362 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2364 /******************* Bit definition for CAN_TDT2R register ******************/
2365 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2366 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
2367 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2369 /******************* Bit definition for CAN_TDL2R register ******************/
2370 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2371 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2372 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2373 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2375 /******************* Bit definition for CAN_TDH2R register ******************/
2376 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2377 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2378 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2379 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2381 /******************* Bit definition for CAN_RI0R register *******************/
2382 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2383 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2384 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
2385 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2387 /******************* Bit definition for CAN_RDT0R register ******************/
2388 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2389 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
2390 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2392 /******************* Bit definition for CAN_RDL0R register ******************/
2393 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2394 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2395 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2396 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2398 /******************* Bit definition for CAN_RDH0R register ******************/
2399 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2400 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2401 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2402 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2404 /******************* Bit definition for CAN_RI1R register *******************/
2405 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2406 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2407 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
2408 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2410 /******************* Bit definition for CAN_RDT1R register ******************/
2411 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2412 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
2413 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2415 /******************* Bit definition for CAN_RDL1R register ******************/
2416 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2417 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2418 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2419 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2421 /******************* Bit definition for CAN_RDH1R register ******************/
2422 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2423 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2424 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2425 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2427 /*!<CAN filter registers */
2428 /******************* Bit definition for CAN_FMR register ********************/
2429 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
2431 /******************* Bit definition for CAN_FM1R register *******************/
2432 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
2433 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
2434 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
2435 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
2436 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
2437 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
2438 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
2439 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
2440 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
2441 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
2442 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
2443 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
2444 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
2445 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
2446 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
2448 /******************* Bit definition for CAN_FS1R register *******************/
2449 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
2450 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
2451 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
2452 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
2453 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
2454 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
2455 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
2456 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
2457 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
2458 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
2459 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
2460 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
2461 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
2462 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
2463 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
2465 /****************** Bit definition for CAN_FFA1R register *******************/
2466 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
2467 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
2468 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
2469 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
2470 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
2471 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
2472 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
2473 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
2474 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
2475 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
2476 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
2477 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
2478 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
2479 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
2480 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
2482 /******************* Bit definition for CAN_FA1R register *******************/
2483 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
2484 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
2485 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
2486 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
2487 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
2488 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
2489 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
2490 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
2491 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
2492 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
2493 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
2494 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
2495 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
2496 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
2497 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
2499 /******************* Bit definition for CAN_F0R1 register *******************/
2500 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2501 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2502 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2503 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2504 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2505 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2506 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2507 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2508 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2509 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2510 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2511 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2512 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2513 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2514 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2515 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2516 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2517 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2518 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2519 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2520 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2521 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2522 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2523 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2524 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2525 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2526 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2527 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2528 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2529 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2530 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2531 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2533 /******************* Bit definition for CAN_F1R1 register *******************/
2534 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2535 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2536 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2537 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2538 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2539 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2540 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2541 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2542 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2543 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2544 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2545 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2546 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2547 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2548 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2549 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2550 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2551 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2552 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2553 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2554 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2555 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2556 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2557 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2558 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2559 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2560 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2561 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2562 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2563 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2564 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2565 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2567 /******************* Bit definition for CAN_F2R1 register *******************/
2568 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2569 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2570 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2571 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2572 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2573 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2574 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2575 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2576 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2577 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2578 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2579 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2580 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2581 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2582 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2583 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2584 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2585 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2586 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2587 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2588 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2589 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2590 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2591 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2592 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2593 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2594 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2595 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2596 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2597 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2598 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2599 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2601 /******************* Bit definition for CAN_F3R1 register *******************/
2602 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2603 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2604 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2605 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2606 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2607 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2608 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2609 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2610 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2611 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2612 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2613 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2614 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2615 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2616 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2617 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2618 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2619 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2620 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2621 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2622 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2623 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2624 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2625 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2626 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2627 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2628 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2629 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2630 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2631 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2632 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2633 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2635 /******************* Bit definition for CAN_F4R1 register *******************/
2636 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2637 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2638 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2639 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2640 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2641 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2642 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2643 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2644 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2645 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2646 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2647 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2648 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2649 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2650 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2651 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2652 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2653 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2654 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2655 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2656 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2657 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2658 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2659 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2660 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2661 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2662 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2663 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2664 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2665 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2666 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2667 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2669 /******************* Bit definition for CAN_F5R1 register *******************/
2670 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2671 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2672 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2673 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2674 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2675 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2676 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2677 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2678 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2679 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2680 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2681 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2682 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2683 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2684 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2685 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2686 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2687 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2688 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2689 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2690 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2691 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2692 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2693 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2694 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2695 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2696 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2697 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2698 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2699 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2700 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2701 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2703 /******************* Bit definition for CAN_F6R1 register *******************/
2704 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2705 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2706 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2707 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2708 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2709 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2710 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2711 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2712 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2713 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2714 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2715 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2716 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2717 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2718 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2719 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2720 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2721 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2722 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2723 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2724 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2725 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2726 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2727 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2728 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2729 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2730 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2731 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2732 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2733 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2734 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2735 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2737 /******************* Bit definition for CAN_F7R1 register *******************/
2738 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2739 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2740 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2741 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2742 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2743 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2744 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2745 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2746 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2747 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2748 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2749 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2750 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2751 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2752 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2753 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2754 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2755 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2756 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2757 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2758 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2759 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2760 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2761 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2762 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2763 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2764 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2765 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2766 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2767 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2768 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2769 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2771 /******************* Bit definition for CAN_F8R1 register *******************/
2772 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2773 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2774 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2775 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2776 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2777 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2778 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2779 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2780 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2781 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2782 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2783 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2784 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2785 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2786 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2787 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2788 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2789 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2790 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2791 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2792 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2793 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2794 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2795 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2796 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2797 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2798 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2799 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2800 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2801 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2802 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2803 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2805 /******************* Bit definition for CAN_F9R1 register *******************/
2806 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2807 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2808 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2809 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2810 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2811 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2812 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2813 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2814 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2815 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2816 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2817 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2818 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2819 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2820 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2821 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2822 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2823 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2824 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2825 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2826 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2827 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2828 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2829 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2830 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2831 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2832 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2833 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2834 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2835 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2836 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2837 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2839 /******************* Bit definition for CAN_F10R1 register ******************/
2840 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2841 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2842 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2843 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2844 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2845 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2846 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2847 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2848 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2849 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2850 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2851 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2852 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2853 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2854 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2855 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2856 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2857 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2858 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2859 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2860 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2861 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2862 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2863 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2864 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2865 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2866 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2867 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2868 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2869 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2870 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2871 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2873 /******************* Bit definition for CAN_F11R1 register ******************/
2874 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2875 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2876 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2877 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2878 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2879 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2880 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2881 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2882 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2883 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2884 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2885 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2886 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2887 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2888 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2889 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2890 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2891 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2892 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2893 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2894 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2895 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2896 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2897 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2898 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2899 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2900 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2901 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2902 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2903 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2904 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2905 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2907 /******************* Bit definition for CAN_F12R1 register ******************/
2908 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2909 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2910 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2911 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2912 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2913 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2914 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2915 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2916 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2917 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2918 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2919 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2920 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2921 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2922 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2923 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2924 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2925 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2926 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2927 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2928 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2929 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2930 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2931 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2932 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2933 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2934 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2935 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2936 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2937 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2938 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2939 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2941 /******************* Bit definition for CAN_F13R1 register ******************/
2942 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2943 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2944 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2945 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2946 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2947 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2948 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2949 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2950 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2951 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2952 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2953 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2954 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2955 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2956 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2957 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2958 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2959 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2960 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2961 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2962 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2963 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2964 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2965 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2966 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2967 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2968 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2969 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2970 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2971 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2972 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2973 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2975 /******************* Bit definition for CAN_F0R2 register *******************/
2976 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2977 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2978 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2979 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2980 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2981 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2982 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2983 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2984 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2985 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2986 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2987 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2988 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2989 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2990 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2991 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2992 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2993 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2994 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2995 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2996 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2997 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2998 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2999 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3000 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3001 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3002 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3003 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3004 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3005 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3006 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3007 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3009 /******************* Bit definition for CAN_F1R2 register *******************/
3010 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3011 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3012 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3013 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3014 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3015 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3016 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3017 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3018 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3019 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3020 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3021 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3022 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3023 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3024 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3025 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3026 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3027 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3028 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3029 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3030 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3031 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3032 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3033 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3034 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3035 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3036 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3037 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3038 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3039 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3040 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3041 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3043 /******************* Bit definition for CAN_F2R2 register *******************/
3044 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3045 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3046 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3047 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3048 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3049 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3050 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3051 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3052 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3053 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3054 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3055 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3056 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3057 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3058 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3059 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3060 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3061 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3062 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3063 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3064 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3065 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3066 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3067 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3068 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3069 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3070 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3071 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3072 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3073 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3074 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3075 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3077 /******************* Bit definition for CAN_F3R2 register *******************/
3078 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3079 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3080 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3081 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3082 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3083 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3084 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3085 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3086 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3087 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3088 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3089 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3090 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3091 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3092 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3093 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3094 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3095 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3096 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3097 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3098 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3099 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3100 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3101 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3102 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3103 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3104 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3105 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3106 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3107 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3108 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3109 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3111 /******************* Bit definition for CAN_F4R2 register *******************/
3112 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3113 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3114 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3115 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3116 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3117 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3118 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3119 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3120 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3121 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3122 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3123 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3124 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3125 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3126 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3127 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3128 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3129 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3130 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3131 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3132 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3133 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3134 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3135 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3136 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3137 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3138 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3139 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3140 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3141 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3142 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3143 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3145 /******************* Bit definition for CAN_F5R2 register *******************/
3146 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3147 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3148 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3149 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3150 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3151 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3152 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3153 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3154 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3155 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3156 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3157 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3158 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3159 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3160 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3161 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3162 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3163 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3164 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3165 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3166 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3167 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3168 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3169 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3170 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3171 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3172 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3173 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3174 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3175 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3176 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3177 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3179 /******************* Bit definition for CAN_F6R2 register *******************/
3180 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3181 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3182 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3183 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3184 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3185 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3186 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3187 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3188 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3189 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3190 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3191 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3192 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3193 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3194 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3195 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3196 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3197 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3198 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3199 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3200 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3201 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3202 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3203 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3204 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3205 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3206 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3207 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3208 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3209 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3210 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3211 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3213 /******************* Bit definition for CAN_F7R2 register *******************/
3214 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3215 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3216 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3217 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3218 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3219 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3220 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3221 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3222 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3223 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3224 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3225 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3226 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3227 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3228 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3229 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3230 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3231 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3232 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3233 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3234 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3235 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3236 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3237 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3238 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3239 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3240 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3241 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3242 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3243 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3244 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3245 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3247 /******************* Bit definition for CAN_F8R2 register *******************/
3248 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3249 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3250 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3251 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3252 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3253 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3254 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3255 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3256 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3257 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3258 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3259 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3260 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3261 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3262 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3263 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3264 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3265 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3266 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3267 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3268 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3269 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3270 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3271 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3272 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3273 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3274 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3275 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3276 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3277 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3278 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3279 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3281 /******************* Bit definition for CAN_F9R2 register *******************/
3282 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3283 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3284 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3285 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3286 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3287 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3288 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3289 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3290 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3291 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3292 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3293 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3294 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3295 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3296 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3297 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3298 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3299 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3300 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3301 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3302 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3303 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3304 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3305 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3306 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3307 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3308 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3309 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3310 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3311 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3312 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3313 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3315 /******************* Bit definition for CAN_F10R2 register ******************/
3316 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3317 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3318 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3319 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3320 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3321 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3322 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3323 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3324 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3325 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3326 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3327 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3328 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3329 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3330 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3331 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3332 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3333 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3334 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3335 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3336 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3337 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3338 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3339 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3340 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3341 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3342 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3343 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3344 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3345 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3346 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3347 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3349 /******************* Bit definition for CAN_F11R2 register ******************/
3350 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3351 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3352 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3353 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3354 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3355 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3356 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3357 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3358 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3359 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3360 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3361 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3362 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3363 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3364 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3365 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3366 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3367 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3368 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3369 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3370 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3371 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3372 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3373 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3374 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3375 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3376 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3377 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3378 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3379 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3380 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3381 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3383 /******************* Bit definition for CAN_F12R2 register ******************/
3384 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3385 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3386 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3387 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3388 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3389 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3390 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3391 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3392 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3393 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3394 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3395 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3396 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3397 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3398 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3399 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3400 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3401 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3402 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3403 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3404 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3405 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3406 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3407 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3408 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3409 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3410 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3411 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3412 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3413 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3414 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3415 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3417 /******************* Bit definition for CAN_F13R2 register ******************/
3418 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3419 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3420 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3421 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3422 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3423 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3424 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3425 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3426 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3427 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3428 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3429 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3430 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3431 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3432 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3433 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3434 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3435 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3436 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3437 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3438 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3439 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3440 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3441 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3442 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3443 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3444 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3445 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3446 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3447 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3448 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3449 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3451 /******************************************************************************/
3453 /* CRC calculation unit (CRC) */
3455 /******************************************************************************/
3456 /******************* Bit definition for CRC_DR register *********************/
3457 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
3459 /******************* Bit definition for CRC_IDR register ********************/
3460 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
3462 /******************** Bit definition for CRC_CR register ********************/
3463 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
3464 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
3465 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
3466 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
3467 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
3468 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
3469 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
3470 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
3472 /******************* Bit definition for CRC_INIT register *******************/
3473 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
3475 /******************* Bit definition for CRC_POL register ********************/
3476 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
3478 /******************************************************************************/
3480 /* Digital to Analog Converter (DAC) */
3482 /******************************************************************************/
3483 /******************** Bit definition for DAC_CR register ********************/
3484 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
3485 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
3486 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
3488 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
3489 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
3490 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
3491 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
3493 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3494 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
3495 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
3497 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3498 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3499 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3500 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
3501 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
3503 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
3504 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
3505 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
3506 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
3507 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
3509 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
3510 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
3511 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
3512 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
3514 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3515 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
3516 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
3518 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3519 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
3520 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
3521 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
3522 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
3524 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
3525 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
3527 /***************** Bit definition for DAC_SWTRIGR register ******************/
3528 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
3529 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
3531 /***************** Bit definition for DAC_DHR12R1 register ******************/
3532 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
3534 /***************** Bit definition for DAC_DHR12L1 register ******************/
3535 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
3537 /****************** Bit definition for DAC_DHR8R1 register ******************/
3538 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
3540 /***************** Bit definition for DAC_DHR12R2 register ******************/
3541 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
3543 /***************** Bit definition for DAC_DHR12L2 register ******************/
3544 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
3546 /****************** Bit definition for DAC_DHR8R2 register ******************/
3547 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
3549 /***************** Bit definition for DAC_DHR12RD register ******************/
3550 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
3551 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
3553 /***************** Bit definition for DAC_DHR12LD register ******************/
3554 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
3555 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
3557 /****************** Bit definition for DAC_DHR8RD register ******************/
3558 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
3559 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
3561 /******************* Bit definition for DAC_DOR1 register *******************/
3562 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
3564 /******************* Bit definition for DAC_DOR2 register *******************/
3565 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
3567 /******************** Bit definition for DAC_SR register ********************/
3568 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
3569 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
3571 /******************************************************************************/
3573 /* Debug MCU (DBGMCU) */
3575 /******************************************************************************/
3576 /******************** Bit definition for DBGMCU_IDCODE register *************/
3577 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
3578 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
3580 /******************** Bit definition for DBGMCU_CR register *****************/
3581 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
3582 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
3583 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
3584 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
3586 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
3587 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
3588 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
3590 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
3591 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
3592 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
3593 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
3594 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
3595 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
3596 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
3597 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
3598 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
3599 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
3600 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
3601 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
3602 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x04000000)
3604 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
3605 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
3606 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
3607 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
3608 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
3609 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
3610 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP ((uint32_t)0x00000020)
3612 /******************************************************************************/
3614 /* DMA Controller (DMA) */
3616 /******************************************************************************/
3617 /******************* Bit definition for DMA_ISR register ********************/
3618 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
3619 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
3620 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
3621 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
3622 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
3623 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
3624 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
3625 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
3626 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
3627 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
3628 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
3629 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
3630 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
3631 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
3632 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
3633 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
3634 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
3635 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
3636 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
3637 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
3638 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
3639 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
3640 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
3641 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
3642 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
3643 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
3644 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
3645 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
3647 /******************* Bit definition for DMA_IFCR register *******************/
3648 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
3649 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
3650 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
3651 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
3652 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
3653 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
3654 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
3655 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
3656 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
3657 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
3658 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
3659 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
3660 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
3661 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
3662 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
3663 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
3664 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
3665 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
3666 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
3667 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
3668 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
3669 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
3670 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
3671 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
3672 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
3673 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
3674 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
3675 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
3677 /******************* Bit definition for DMA_CCR register ********************/
3678 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
3679 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
3680 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
3681 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
3682 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
3683 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
3684 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
3685 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
3687 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
3688 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3689 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3691 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
3692 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
3693 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
3695 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
3696 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3697 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3699 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
3701 /****************** Bit definition for DMA_CNDTR register *******************/
3702 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
3704 /****************** Bit definition for DMA_CPAR register ********************/
3705 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
3707 /****************** Bit definition for DMA_CMAR register ********************/
3708 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3710 /******************************************************************************/
3712 /* External Interrupt/Event Controller (EXTI) */
3714 /******************************************************************************/
3715 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
3716 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3717 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3718 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3719 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3720 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3721 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3722 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3723 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3724 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3725 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3726 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3727 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3728 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3729 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3730 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3731 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3732 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3733 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3734 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3735 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3736 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
3737 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
3738 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
3739 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
3740 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
3741 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
3742 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
3743 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
3744 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
3746 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
3747 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3748 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3749 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3750 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3751 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3752 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3753 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3754 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3755 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3756 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3757 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3758 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3759 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3760 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3761 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3762 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3763 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3764 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3765 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3766 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3767 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
3768 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
3769 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
3770 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
3771 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
3772 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
3773 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
3774 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
3775 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
3777 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
3778 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3779 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3780 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3781 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3782 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3783 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3784 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3785 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3786 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3787 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3788 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3789 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3790 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3791 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3792 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3793 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3794 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3795 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3796 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3797 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3798 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
3799 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
3800 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
3801 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
3802 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
3803 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
3804 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
3805 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
3806 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
3808 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
3809 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3810 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3811 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3812 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3813 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3814 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3815 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3816 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3817 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3818 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3819 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3820 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3821 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3822 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3823 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3824 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3825 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3826 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3827 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3828 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3829 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
3830 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
3831 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
3832 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
3833 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
3834 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
3835 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
3836 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
3837 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
3839 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
3840 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3841 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3842 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3843 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3844 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3845 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3846 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3847 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3848 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3849 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3850 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3851 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3852 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3853 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3854 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3855 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3856 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3857 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3858 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3859 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3860 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
3861 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
3862 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
3863 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
3864 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
3865 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
3866 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
3867 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
3868 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
3870 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
3871 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3872 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3873 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3874 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3875 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3876 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3877 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3878 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3879 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3880 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3881 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3882 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3883 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3884 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3885 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3886 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3887 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3888 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3889 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3890 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3891 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
3892 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
3893 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
3894 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
3895 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
3896 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
3897 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
3898 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
3899 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
3901 /******************************************************************************/
3905 /******************************************************************************/
3906 /******************* Bit definition for FLASH_ACR register ******************/
3907 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
3908 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3909 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3910 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3912 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
3913 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
3914 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
3916 /****************** Bit definition for FLASH_KEYR register ******************/
3917 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
3919 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
3920 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
3921 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
3923 /***************** Bit definition for FLASH_OPTKEYR register ****************/
3924 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
3926 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
3927 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
3929 /****************** Bit definition for FLASH_SR register *******************/
3930 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
3931 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
3932 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
3933 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
3935 /******************* Bit definition for FLASH_CR register *******************/
3936 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
3937 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
3938 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
3939 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
3940 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
3941 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
3942 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
3943 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
3944 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
3945 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
3946 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
3948 /******************* Bit definition for FLASH_AR register *******************/
3949 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
3951 /****************** Bit definition for FLASH_OBR register *******************/
3952 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
3953 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
3954 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
3955 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
3957 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
3958 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
3959 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
3960 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
3961 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
3962 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
3963 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
3965 /****************** Bit definition for FLASH_WRPR register ******************/
3966 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
3968 /*----------------------------------------------------------------------------*/
3970 /****************** Bit definition for OB_RDP register **********************/
3971 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
3972 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
3974 /****************** Bit definition for OB_USER register *********************/
3975 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
3976 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
3978 /****************** Bit definition for FLASH_WRP0 register ******************/
3979 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
3980 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
3982 /****************** Bit definition for FLASH_WRP1 register ******************/
3983 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
3984 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
3986 /****************** Bit definition for FLASH_WRP2 register ******************/
3987 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
3988 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
3990 /****************** Bit definition for FLASH_WRP3 register ******************/
3991 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
3992 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
3995 /******************************************************************************/
3997 /* Flexible Memory Controller */
3999 /******************************************************************************/
4000 /****************** Bit definition for FMC_BCR1 register *******************/
4001 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4002 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4004 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4005 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4006 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4008 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4009 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4010 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4012 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4013 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4014 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4015 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4016 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4017 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4018 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4019 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4020 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4021 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4022 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
4024 /****************** Bit definition for FMC_BCR2 register *******************/
4025 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4026 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4028 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4029 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4030 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4032 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4033 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4034 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4036 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4037 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4038 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4039 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4040 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4041 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4042 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4043 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4044 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4045 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4047 /****************** Bit definition for FMC_BCR3 register *******************/
4048 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4049 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4051 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4052 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4053 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4055 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4056 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4057 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4059 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4060 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4061 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4062 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4063 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4064 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4065 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4066 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4067 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4068 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4070 /****************** Bit definition for FMC_BCR4 register *******************/
4071 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4072 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4074 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4075 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4076 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4078 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4079 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4080 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4082 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4083 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4084 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4085 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4086 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4087 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4088 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4089 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4090 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4091 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4093 /****************** Bit definition for FMC_BTR1 register ******************/
4094 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4095 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4096 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4097 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4098 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4100 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4101 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4102 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4103 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4104 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4106 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4107 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4108 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4109 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4110 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4111 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4112 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4113 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4114 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4116 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4117 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4118 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4119 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4120 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4122 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4123 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4124 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4125 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4126 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4128 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4129 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4130 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4131 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4132 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4134 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4135 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4136 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4138 /****************** Bit definition for FMC_BTR2 register *******************/
4139 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4140 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4141 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4142 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4143 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4145 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4146 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4147 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4148 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4149 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4151 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4152 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4153 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4154 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4155 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4156 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4157 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4158 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4159 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4161 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4162 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4163 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4164 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4165 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4167 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4168 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4169 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4170 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4171 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4173 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4174 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4175 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4176 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4177 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4179 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4180 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4181 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4183 /******************* Bit definition for FMC_BTR3 register *******************/
4184 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4185 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4186 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4187 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4188 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4190 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4191 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4192 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4193 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4194 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4196 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4197 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4198 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4199 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4200 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4201 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4202 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4203 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4204 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4206 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4207 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4208 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4209 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4210 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4212 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4213 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4214 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4215 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4216 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4218 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4219 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4220 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4221 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4222 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4224 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4225 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4226 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4228 /****************** Bit definition for FMC_BTR4 register *******************/
4229 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4230 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4231 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4232 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4233 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4235 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4236 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4237 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4238 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4239 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4241 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4242 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4243 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4244 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4245 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4246 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4247 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4248 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4249 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4251 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4252 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4253 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4254 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4255 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4257 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4258 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4259 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4260 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4261 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4263 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4264 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4265 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4266 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4267 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4269 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4270 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4271 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4273 /****************** Bit definition for FMC_BWTR1 register ******************/
4274 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4275 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4276 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4277 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4278 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4280 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4281 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4282 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4283 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4284 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4286 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4287 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4288 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4289 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4290 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4291 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4292 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4293 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4294 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4296 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4297 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4298 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4299 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4300 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4302 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4303 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4304 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4305 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4306 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4308 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4309 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4310 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4312 /****************** Bit definition for FMC_BWTR2 register ******************/
4313 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4314 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4315 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4316 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4317 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4319 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4320 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4321 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4322 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4323 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4325 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4326 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4327 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4328 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4329 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4330 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4331 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4332 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4333 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4335 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4336 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4337 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
4338 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4339 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4341 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4342 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4343 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4344 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4345 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4347 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4348 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4349 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4351 /****************** Bit definition for FMC_BWTR3 register ******************/
4352 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4353 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4354 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4355 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4356 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4358 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4359 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4360 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4361 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4362 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4364 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4365 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4366 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4367 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4368 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4369 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4370 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4371 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4372 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4374 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4375 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4376 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4377 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4378 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4380 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4381 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4382 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4383 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4384 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4386 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4387 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4388 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4390 /****************** Bit definition for FMC_BWTR4 register ******************/
4391 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4392 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4393 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4394 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4395 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4397 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4398 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4399 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4400 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4401 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4403 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4404 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4405 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4406 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4407 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4408 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4409 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4410 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4411 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4413 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4414 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4415 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4416 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4417 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4419 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4420 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4421 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4422 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4423 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4425 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4426 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4427 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4429 /****************** Bit definition for FMC_PCR2 register *******************/
4430 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4431 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4432 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4434 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4435 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4436 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4438 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4440 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4441 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4442 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4443 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4444 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4446 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4447 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4448 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4449 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4450 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4452 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
4453 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4454 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4455 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4457 /****************** Bit definition for FMC_PCR3 register *******************/
4458 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4459 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4460 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4462 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4463 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4464 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4466 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4468 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4469 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4470 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4471 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4472 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4474 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4475 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4476 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4477 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4478 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4480 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4481 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4482 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4483 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4485 /****************** Bit definition for FMC_PCR4 register *******************/
4486 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4487 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4488 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4490 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4491 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4492 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4494 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4496 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4497 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4498 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4499 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4500 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4502 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4503 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4504 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4505 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4506 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4508 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4509 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4510 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4511 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4513 /******************* Bit definition for FMC_SR2 register *******************/
4514 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4515 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4516 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4517 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4518 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4519 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4520 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4522 /******************* Bit definition for FMC_SR3 register *******************/
4523 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4524 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4525 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4526 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4527 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4528 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4529 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4531 /******************* Bit definition for FMC_SR4 register *******************/
4532 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4533 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4534 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4535 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4536 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4537 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4538 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4540 /****************** Bit definition for FMC_PMEM2 register ******************/
4541 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
4542 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4543 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4544 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4545 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4546 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4547 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4548 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4549 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4551 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
4552 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4553 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4554 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4555 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4556 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4557 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4558 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4559 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4561 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
4562 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4563 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4564 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4565 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4566 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4567 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4568 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4569 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4571 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
4572 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4573 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4574 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4575 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4576 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4577 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4578 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4579 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4581 /****************** Bit definition for FMC_PMEM3 register ******************/
4582 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4583 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4584 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4585 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4586 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4587 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4588 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4589 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4590 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4592 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4593 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4594 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4595 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4596 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4597 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4598 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4599 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4600 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4602 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4603 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4604 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4605 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4606 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4607 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4608 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4609 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4610 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4612 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4613 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4614 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4615 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4616 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4617 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4618 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4619 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4620 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4622 /****************** Bit definition for FMC_PMEM4 register ******************/
4623 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
4624 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4625 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4626 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4627 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4628 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4629 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4630 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4631 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4633 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4634 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4635 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4636 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4637 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4638 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4639 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4640 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4641 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4643 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4644 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4645 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4646 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4647 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4648 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4649 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4650 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4651 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4653 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4654 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4655 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4656 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4657 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4658 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4659 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4660 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4661 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4663 /****************** Bit definition for FMC_PATT2 register ******************/
4664 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4665 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4666 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4667 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4668 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4669 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4670 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4671 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4672 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4674 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4675 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4676 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4677 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4678 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4679 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4680 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4681 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4682 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4684 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4685 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4686 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4687 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4688 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4689 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4690 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4691 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4692 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4694 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4695 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4696 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4697 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4698 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4699 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4700 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4701 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4702 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4704 /****************** Bit definition for FMC_PATT3 register ******************/
4705 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4706 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4707 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4708 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4709 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4710 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4711 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4712 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4713 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4715 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4716 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4717 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4718 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4719 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4720 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4721 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4722 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4723 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4725 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4726 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4727 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4728 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4729 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4730 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4731 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4732 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4733 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4735 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4736 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4737 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4738 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4739 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4740 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4741 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4742 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4743 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4745 /****************** Bit definition for FMC_PATT4 register ******************/
4746 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4747 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4748 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4749 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4750 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4751 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4752 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4753 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4754 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4756 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4757 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4758 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4759 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4760 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4761 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4762 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4763 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4764 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4766 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4767 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4768 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4769 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4770 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4771 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4772 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4773 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4774 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4776 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4777 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4778 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4779 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4780 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4781 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4782 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4783 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4784 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4786 /****************** Bit definition for FMC_PIO4 register *******************/
4787 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4788 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4789 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4790 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4791 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4792 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4793 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4794 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4795 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4797 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4798 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4799 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4800 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4801 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4802 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4803 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4804 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4805 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4807 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4808 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4809 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4810 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4811 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4812 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4813 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4814 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4815 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4817 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4818 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4819 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4820 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4821 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4822 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4823 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4824 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4825 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4827 /****************** Bit definition for FMC_ECCR2 register ******************/
4828 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4830 /****************** Bit definition for FMC_ECCR3 register ******************/
4831 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4833 /****************** Bit definition for FMC_SDCR1 register ******************/
4834 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4835 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4836 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4838 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4839 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4840 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4842 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4843 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4844 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4846 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4848 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4849 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4850 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4852 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
4854 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
4855 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4856 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4858 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4860 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
4861 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4862 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4864 /****************** Bit definition for FMC_SDCR2 register ******************/
4865 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4866 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4867 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4869 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4870 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4871 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4873 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4874 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4875 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4877 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4879 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4880 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4881 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4883 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
4885 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
4886 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4887 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4889 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4891 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
4892 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4893 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4895 /****************** Bit definition for FMC_SDTR1 register ******************/
4896 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4897 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4898 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4899 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4900 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4902 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4903 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4904 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4905 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4906 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4908 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4909 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4910 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4911 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4912 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4914 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4915 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4916 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4917 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4919 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4920 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4921 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4922 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4924 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4925 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4926 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4927 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4929 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4930 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4931 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4932 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4934 /****************** Bit definition for FMC_SDTR2 register ******************/
4935 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4936 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4937 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4938 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4939 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4941 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4942 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4943 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4944 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4945 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4947 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4948 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4949 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4950 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4951 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4953 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4954 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4955 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4956 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4958 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4959 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4960 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4961 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4963 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4964 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4965 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4966 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4968 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4969 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4970 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4971 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4973 /****************** Bit definition for FMC_SDCMR register ******************/
4974 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
4975 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4976 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4977 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
4979 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
4981 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
4983 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
4984 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
4985 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
4986 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
4987 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
4989 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
4991 /****************** Bit definition for FMC_SDRTR register ******************/
4992 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
4994 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
4996 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
4998 /****************** Bit definition for FMC_SDSR register ******************/
4999 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
5001 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
5002 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
5003 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
5005 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
5006 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
5007 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
5008 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
5012 /******************************************************************************/
5014 /* General Purpose I/O (GPIO) */
5016 /******************************************************************************/
5017 /******************* Bit definition for GPIO_MODER register *****************/
5018 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
5019 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
5020 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
5021 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
5022 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
5023 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
5024 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
5025 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
5026 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
5027 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
5028 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
5029 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
5030 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
5031 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
5032 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
5033 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
5034 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
5035 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
5036 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
5037 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
5038 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
5039 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
5040 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
5041 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
5042 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
5043 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
5044 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
5045 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
5046 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
5047 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
5048 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
5049 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
5050 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
5051 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
5052 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
5053 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
5054 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
5055 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
5056 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
5057 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
5058 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
5059 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
5060 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
5061 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
5062 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
5063 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
5064 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
5065 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
5067 /****************** Bit definition for GPIO_OTYPER register *****************/
5068 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
5069 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
5070 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
5071 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
5072 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
5073 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
5074 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
5075 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
5076 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
5077 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
5078 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
5079 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
5080 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
5081 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
5082 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
5083 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
5085 /**************** Bit definition for GPIO_OSPEEDR register ******************/
5086 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
5087 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
5088 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
5089 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
5090 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
5091 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
5092 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
5093 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
5094 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
5095 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
5096 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
5097 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
5098 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
5099 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
5100 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
5101 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
5102 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
5103 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
5104 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
5105 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
5106 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
5107 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
5108 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
5109 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
5110 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
5111 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
5112 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
5113 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
5114 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
5115 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
5116 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
5117 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
5118 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
5119 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
5120 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
5121 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
5122 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
5123 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
5124 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
5125 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
5126 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
5127 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
5128 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
5129 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
5130 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
5131 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
5132 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
5133 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
5135 /******************* Bit definition for GPIO_PUPDR register ******************/
5136 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
5137 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
5138 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
5139 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
5140 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
5141 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
5142 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
5143 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
5144 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
5145 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
5146 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
5147 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
5148 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
5149 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
5150 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
5151 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
5152 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
5153 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
5154 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
5155 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
5156 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
5157 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
5158 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
5159 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
5160 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
5161 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
5162 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
5163 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
5164 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
5165 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
5166 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
5167 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
5168 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
5169 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
5170 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
5171 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
5172 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
5173 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
5174 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
5175 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
5176 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
5177 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
5178 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
5179 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
5180 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
5181 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
5182 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
5183 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
5185 /******************* Bit definition for GPIO_IDR register *******************/
5186 #define GPIO_IDR_0 ((uint32_t)0x00000001)
5187 #define GPIO_IDR_1 ((uint32_t)0x00000002)
5188 #define GPIO_IDR_2 ((uint32_t)0x00000004)
5189 #define GPIO_IDR_3 ((uint32_t)0x00000008)
5190 #define GPIO_IDR_4 ((uint32_t)0x00000010)
5191 #define GPIO_IDR_5 ((uint32_t)0x00000020)
5192 #define GPIO_IDR_6 ((uint32_t)0x00000040)
5193 #define GPIO_IDR_7 ((uint32_t)0x00000080)
5194 #define GPIO_IDR_8 ((uint32_t)0x00000100)
5195 #define GPIO_IDR_9 ((uint32_t)0x00000200)
5196 #define GPIO_IDR_10 ((uint32_t)0x00000400)
5197 #define GPIO_IDR_11 ((uint32_t)0x00000800)
5198 #define GPIO_IDR_12 ((uint32_t)0x00001000)
5199 #define GPIO_IDR_13 ((uint32_t)0x00002000)
5200 #define GPIO_IDR_14 ((uint32_t)0x00004000)
5201 #define GPIO_IDR_15 ((uint32_t)0x00008000)
5203 /****************** Bit definition for GPIO_ODR register ********************/
5204 #define GPIO_ODR_0 ((uint32_t)0x00000001)
5205 #define GPIO_ODR_1 ((uint32_t)0x00000002)
5206 #define GPIO_ODR_2 ((uint32_t)0x00000004)
5207 #define GPIO_ODR_3 ((uint32_t)0x00000008)
5208 #define GPIO_ODR_4 ((uint32_t)0x00000010)
5209 #define GPIO_ODR_5 ((uint32_t)0x00000020)
5210 #define GPIO_ODR_6 ((uint32_t)0x00000040)
5211 #define GPIO_ODR_7 ((uint32_t)0x00000080)
5212 #define GPIO_ODR_8 ((uint32_t)0x00000100)
5213 #define GPIO_ODR_9 ((uint32_t)0x00000200)
5214 #define GPIO_ODR_10 ((uint32_t)0x00000400)
5215 #define GPIO_ODR_11 ((uint32_t)0x00000800)
5216 #define GPIO_ODR_12 ((uint32_t)0x00001000)
5217 #define GPIO_ODR_13 ((uint32_t)0x00002000)
5218 #define GPIO_ODR_14 ((uint32_t)0x00004000)
5219 #define GPIO_ODR_15 ((uint32_t)0x00008000)
5221 /****************** Bit definition for GPIO_BSRR register ********************/
5222 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
5223 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
5224 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
5225 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
5226 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
5227 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
5228 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
5229 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
5230 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
5231 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
5232 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
5233 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
5234 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
5235 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
5236 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
5237 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
5238 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
5239 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
5240 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
5241 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
5242 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
5243 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
5244 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
5245 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
5246 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
5247 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
5248 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
5249 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
5250 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
5251 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
5252 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
5253 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
5255 /****************** Bit definition for GPIO_LCKR register ********************/
5256 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
5257 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
5258 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
5259 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
5260 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
5261 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
5262 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
5263 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
5264 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
5265 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
5266 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
5267 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
5268 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
5269 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
5270 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
5271 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
5272 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
5274 /****************** Bit definition for GPIO_AFRL register ********************/
5275 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
5276 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
5277 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
5278 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
5279 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
5280 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
5281 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
5282 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
5284 /****************** Bit definition for GPIO_AFRH register ********************/
5285 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
5286 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
5287 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
5288 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
5289 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
5290 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
5291 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
5292 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
5294 /****************** Bit definition for GPIO_BRR register *********************/
5295 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
5296 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
5297 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
5298 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
5299 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
5300 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
5301 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
5302 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
5303 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
5304 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
5305 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
5306 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
5307 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
5308 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
5309 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
5310 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
5312 /******************************************************************************/
5314 /* Inter-integrated Circuit Interface (I2C) */
5316 /******************************************************************************/
5317 /******************* Bit definition for I2C_CR1 register *******************/
5318 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
5319 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
5320 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
5321 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
5322 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
5323 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
5324 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
5325 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
5326 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
5327 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
5328 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
5329 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
5330 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
5331 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
5332 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
5333 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
5334 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
5335 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
5336 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
5337 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
5338 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
5340 /****************** Bit definition for I2C_CR2 register ********************/
5341 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
5342 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
5343 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
5344 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
5345 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
5346 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
5347 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
5348 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
5349 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
5350 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
5351 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
5353 /******************* Bit definition for I2C_OAR1 register ******************/
5354 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
5355 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
5356 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
5358 /******************* Bit definition for I2C_OAR2 register *******************/
5359 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
5360 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
5361 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
5363 /******************* Bit definition for I2C_TIMINGR register *****************/
5364 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
5365 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
5366 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
5367 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
5368 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
5370 /******************* Bit definition for I2C_TIMEOUTR register *****************/
5371 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
5372 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
5373 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
5374 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
5375 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
5377 /****************** Bit definition for I2C_ISR register *********************/
5378 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
5379 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
5380 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
5381 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
5382 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
5383 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
5384 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
5385 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
5386 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
5387 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
5388 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
5389 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
5390 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
5391 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
5392 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
5393 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
5394 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
5396 /****************** Bit definition for I2C_ICR register *********************/
5397 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
5398 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
5399 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
5400 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
5401 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
5402 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
5403 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
5404 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
5405 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
5407 /****************** Bit definition for I2C_PECR register ********************/
5408 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
5410 /****************** Bit definition for I2C_RXDR register *********************/
5411 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
5413 /****************** Bit definition for I2C_TXDR register *********************/
5414 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
5417 /******************************************************************************/
5419 /* Independent WATCHDOG (IWDG) */
5421 /******************************************************************************/
5422 /******************* Bit definition for IWDG_KR register ********************/
5423 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
5425 /******************* Bit definition for IWDG_PR register ********************/
5426 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
5427 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5428 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5429 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
5431 /******************* Bit definition for IWDG_RLR register *******************/
5432 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
5434 /******************* Bit definition for IWDG_SR register ********************/
5435 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
5436 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
5437 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
5439 /******************* Bit definition for IWDG_KR register ********************/
5440 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
5442 /******************************************************************************/
5446 /******************************************************************************/
5447 /******************** Bit definition for PWR_CR register ********************/
5448 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
5449 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
5450 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
5451 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
5452 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
5454 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
5455 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
5456 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
5457 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
5459 /*!< PVD level configuration */
5460 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
5461 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
5462 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
5463 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
5464 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
5465 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
5466 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
5467 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
5469 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
5471 /******************* Bit definition for PWR_CSR register ********************/
5472 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
5473 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
5474 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
5475 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
5477 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
5478 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
5479 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
5481 /******************************************************************************/
5483 /* Reset and Clock Control */
5485 /******************************************************************************/
5486 /******************** Bit definition for RCC_CR register ********************/
5487 #define RCC_CR_HSION ((uint32_t)0x00000001)
5488 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
5490 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
5491 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
5492 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
5493 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
5494 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
5495 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
5497 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
5498 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
5499 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
5500 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
5501 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
5502 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
5503 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
5504 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
5505 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
5507 #define RCC_CR_HSEON ((uint32_t)0x00010000)
5508 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
5509 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
5510 #define RCC_CR_CSSON ((uint32_t)0x00080000)
5511 #define RCC_CR_PLLON ((uint32_t)0x01000000)
5512 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
5514 /******************** Bit definition for RCC_CFGR register ******************/
5515 /*!< SW configuration */
5516 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
5517 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5518 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5520 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
5521 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
5522 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
5524 /*!< SWS configuration */
5525 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
5526 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
5527 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
5529 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
5530 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
5531 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
5533 /*!< HPRE configuration */
5534 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
5535 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
5536 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
5537 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
5538 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
5540 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
5541 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
5542 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
5543 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
5544 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
5545 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
5546 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
5547 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
5548 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
5550 /*!< PPRE1 configuration */
5551 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
5552 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5553 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5554 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5556 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5557 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
5558 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
5559 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
5560 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
5562 /*!< PPRE2 configuration */
5563 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
5564 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
5565 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
5566 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
5568 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5569 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
5570 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
5571 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
5572 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
5574 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
5575 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock as PLL entry clock source */
5576 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
5578 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
5579 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
5580 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
5582 /*!< PLLMUL configuration */
5583 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
5584 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
5585 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
5586 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
5587 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
5589 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
5590 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
5591 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
5592 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
5593 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
5594 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
5595 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
5596 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
5597 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
5598 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
5599 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
5600 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
5601 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
5602 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
5603 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
5605 /*!< USB configuration */
5606 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
5608 #define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
5609 #define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
5611 /*!< I2S configuration */
5612 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
5614 #define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
5615 #define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
5617 /*!< MCO configuration */
5618 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
5619 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
5620 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
5621 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
5623 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
5624 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
5625 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
5626 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
5627 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
5628 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
5629 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
5631 #define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
5633 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
5634 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
5635 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
5636 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
5638 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
5640 /********************* Bit definition for RCC_CIR register ********************/
5641 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
5642 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
5643 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
5644 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
5645 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
5646 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
5647 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
5648 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
5649 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
5650 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
5651 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
5652 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
5653 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
5654 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
5655 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
5656 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
5657 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
5659 /****************** Bit definition for RCC_APB2RSTR register *****************/
5660 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
5661 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
5662 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
5663 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */
5664 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
5665 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00008000) /*!< SPI4 reset */
5666 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
5667 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
5668 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
5669 #define RCC_APB2RSTR_TIM20RST ((uint32_t)0x00100000) /*!< TIM20 reset */
5671 /****************** Bit definition for RCC_APB1RSTR register ******************/
5672 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
5673 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
5674 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
5675 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
5676 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
5677 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
5678 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
5679 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
5680 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
5681 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
5682 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
5683 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
5684 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
5685 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
5686 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
5687 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
5688 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
5689 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
5690 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
5692 /****************** Bit definition for RCC_AHBENR register ******************/
5693 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
5694 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
5695 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
5696 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
5697 #define RCC_AHBENR_FMCEN ((uint32_t)0x00000020) /*!< FMC clock enable */
5698 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
5699 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00010000) /*!< GPIOH clock enable */
5700 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
5701 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
5702 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
5703 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
5704 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
5705 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
5706 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00800000) /*!< GPIOG clock enable */
5707 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
5708 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
5709 #define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
5711 /***************** Bit definition for RCC_APB2ENR register ******************/
5712 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
5713 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
5714 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
5715 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
5716 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
5717 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00008000) /*!< SPI4 clock enable */
5718 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
5719 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
5720 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
5721 #define RCC_APB2ENR_TIM20EN ((uint32_t)0x00100000) /*!< TIM20 clock enable */
5723 /****************** Bit definition for RCC_APB1ENR register ******************/
5724 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
5725 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
5726 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
5727 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
5728 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
5729 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
5730 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
5731 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
5732 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
5733 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
5734 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
5735 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
5736 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
5737 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
5738 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
5739 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
5740 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
5741 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
5742 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
5744 /******************** Bit definition for RCC_BDCR register ******************/
5745 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
5746 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
5747 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
5748 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
5750 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
5751 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
5752 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
5754 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
5755 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5756 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5758 /*!< RTC configuration */
5759 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
5760 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
5761 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
5762 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
5764 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
5765 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
5767 /******************** Bit definition for RCC_CSR register *******************/
5768 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
5769 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
5770 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
5771 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
5772 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
5773 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
5774 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
5775 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
5776 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
5777 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
5779 /******************* Bit definition for RCC_AHBRSTR register ****************/
5780 #define RCC_AHBRSTR_FMCRST ((uint32_t)0x00000020) /*!< FMC reset */
5781 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00010000) /*!< GPIOH reset */
5782 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
5783 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
5784 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
5785 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
5786 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
5787 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
5788 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00800000) /*!< GPIOG reset */
5789 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
5790 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
5791 #define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
5793 /******************* Bit definition for RCC_CFGR2 register ******************/
5794 /*!< PREDIV configuration */
5795 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
5796 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5797 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5798 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
5799 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
5801 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
5802 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
5803 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
5804 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
5805 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
5806 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
5807 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
5808 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
5809 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
5810 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
5811 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
5812 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
5813 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
5814 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
5815 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
5816 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
5818 /*!< ADCPRE12 configuration */
5819 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
5820 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
5821 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
5822 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
5823 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
5824 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
5826 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
5827 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
5828 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
5829 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
5830 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
5831 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
5832 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
5833 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
5834 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
5835 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
5836 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
5837 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
5838 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
5840 /*!< ADCPRE34 configuration */
5841 #define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
5842 #define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
5843 #define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
5844 #define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
5845 #define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
5846 #define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
5848 #define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
5849 #define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
5850 #define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
5851 #define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
5852 #define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
5853 #define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
5854 #define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
5855 #define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
5856 #define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
5857 #define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
5858 #define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
5859 #define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
5860 #define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
5862 /******************* Bit definition for RCC_CFGR3 register ******************/
5863 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
5864 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5865 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5867 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
5868 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
5869 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
5870 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
5872 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
5873 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
5874 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
5875 #define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
5877 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
5878 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
5879 #define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
5880 #define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
5881 #define RCC_CFGR3_I2C3SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C3 clock source */
5882 #define RCC_CFGR3_I2C3SW_SYSCLK ((uint32_t)0x00000040) /*!< System clock selected as I2C3 clock source */
5884 #define RCC_CFGR3_TIMSW ((uint32_t)0x0000AF00) /*!< TIMSW bits */
5885 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
5886 #define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
5887 #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
5888 #define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
5889 #define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
5890 #define RCC_CFGR3_TIM20SW ((uint32_t)0x00008000) /*!< TIM20SW bits */
5891 #define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM2SW bits */
5892 #define RCC_CFGR3_TIM34SW ((uint32_t)0x02000000) /*!< TIM34SW bits */
5894 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
5895 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
5897 #define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
5898 #define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
5900 #define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
5901 #define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
5903 #define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
5904 #define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
5906 #define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
5907 #define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
5909 #define RCC_CFGR3_TIM20SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM20 clock source */
5910 #define RCC_CFGR3_TIM20SW_PLL ((uint32_t)0x00008000) /*!< PLL clock used as TIM20 clock source */
5912 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
5913 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
5914 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
5916 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
5917 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
5918 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
5919 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
5921 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
5922 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
5923 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
5925 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
5926 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
5927 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
5928 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
5930 #define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
5931 #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
5932 #define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
5934 #define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
5935 #define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
5936 #define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
5937 #define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
5939 #define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
5940 #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
5941 #define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
5943 #define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
5944 #define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
5945 #define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
5946 #define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
5948 #define RCC_CFGR3_TIM2SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM2 clock source */
5949 #define RCC_CFGR3_TIM2SW_PLL ((uint32_t)0x01000000) /*!< PLL clock used as TIM2 clock source */
5951 #define RCC_CFGR3_TIM34SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM3/TIM4 clock source */
5952 #define RCC_CFGR3_TIM34SW_PLL ((uint32_t)0x02000000) /*!< PLL clock used as TIM3/TIM4 clock source */
5954 /******************************************************************************/
5956 /* Real-Time Clock (RTC) */
5958 /******************************************************************************/
5959 /******************** Bits definition for RTC_TR register *******************/
5960 #define RTC_TR_PM ((uint32_t)0x00400000)
5961 #define RTC_TR_HT ((uint32_t)0x00300000)
5962 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
5963 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
5964 #define RTC_TR_HU ((uint32_t)0x000F0000)
5965 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
5966 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
5967 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
5968 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
5969 #define RTC_TR_MNT ((uint32_t)0x00007000)
5970 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5971 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5972 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5973 #define RTC_TR_MNU ((uint32_t)0x00000F00)
5974 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5975 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5976 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5977 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5978 #define RTC_TR_ST ((uint32_t)0x00000070)
5979 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
5980 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
5981 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
5982 #define RTC_TR_SU ((uint32_t)0x0000000F)
5983 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
5984 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
5985 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
5986 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
5988 /******************** Bits definition for RTC_DR register *******************/
5989 #define RTC_DR_YT ((uint32_t)0x00F00000)
5990 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
5991 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
5992 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
5993 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
5994 #define RTC_DR_YU ((uint32_t)0x000F0000)
5995 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
5996 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
5997 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
5998 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
5999 #define RTC_DR_WDU ((uint32_t)0x0000E000)
6000 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
6001 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
6002 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
6003 #define RTC_DR_MT ((uint32_t)0x00001000)
6004 #define RTC_DR_MU ((uint32_t)0x00000F00)
6005 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
6006 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
6007 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
6008 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
6009 #define RTC_DR_DT ((uint32_t)0x00000030)
6010 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
6011 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
6012 #define RTC_DR_DU ((uint32_t)0x0000000F)
6013 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
6014 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
6015 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
6016 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
6018 /******************** Bits definition for RTC_CR register *******************/
6019 #define RTC_CR_COE ((uint32_t)0x00800000)
6020 #define RTC_CR_OSEL ((uint32_t)0x00600000)
6021 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
6022 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
6023 #define RTC_CR_POL ((uint32_t)0x00100000)
6024 #define RTC_CR_COSEL ((uint32_t)0x00080000)
6025 #define RTC_CR_BCK ((uint32_t)0x00040000)
6026 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
6027 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
6028 #define RTC_CR_TSIE ((uint32_t)0x00008000)
6029 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
6030 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
6031 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
6032 #define RTC_CR_TSE ((uint32_t)0x00000800)
6033 #define RTC_CR_WUTE ((uint32_t)0x00000400)
6034 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
6035 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
6036 #define RTC_CR_FMT ((uint32_t)0x00000040)
6037 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
6038 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
6039 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
6040 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
6041 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
6042 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
6043 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
6045 /******************** Bits definition for RTC_ISR register ******************/
6046 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
6047 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
6048 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
6049 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
6050 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
6051 #define RTC_ISR_TSF ((uint32_t)0x00000800)
6052 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
6053 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
6054 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
6055 #define RTC_ISR_INIT ((uint32_t)0x00000080)
6056 #define RTC_ISR_INITF ((uint32_t)0x00000040)
6057 #define RTC_ISR_RSF ((uint32_t)0x00000020)
6058 #define RTC_ISR_INITS ((uint32_t)0x00000010)
6059 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
6060 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
6061 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
6062 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
6064 /******************** Bits definition for RTC_PRER register *****************/
6065 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
6066 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
6068 /******************** Bits definition for RTC_WUTR register *****************/
6069 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
6071 /******************** Bits definition for RTC_ALRMAR register ***************/
6072 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
6073 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
6074 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
6075 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
6076 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
6077 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
6078 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
6079 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
6080 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
6081 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
6082 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
6083 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
6084 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
6085 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
6086 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
6087 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
6088 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
6089 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
6090 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
6091 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
6092 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
6093 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
6094 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
6095 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
6096 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
6097 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
6098 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
6099 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
6100 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
6101 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
6102 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
6103 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
6104 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
6105 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
6106 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
6107 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
6108 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
6109 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
6110 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
6111 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
6113 /******************** Bits definition for RTC_ALRMBR register ***************/
6114 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
6115 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
6116 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
6117 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
6118 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
6119 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
6120 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
6121 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
6122 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
6123 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
6124 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
6125 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
6126 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
6127 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
6128 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
6129 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
6130 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
6131 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
6132 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
6133 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
6134 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
6135 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
6136 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
6137 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
6138 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
6139 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
6140 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
6141 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
6142 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
6143 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
6144 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
6145 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
6146 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
6147 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
6148 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
6149 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
6150 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
6151 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
6152 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
6153 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
6155 /******************** Bits definition for RTC_WPR register ******************/
6156 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
6158 /******************** Bits definition for RTC_SSR register ******************/
6159 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
6161 /******************** Bits definition for RTC_SHIFTR register ***************/
6162 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
6163 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
6165 /******************** Bits definition for RTC_TSTR register *****************/
6166 #define RTC_TSTR_PM ((uint32_t)0x00400000)
6167 #define RTC_TSTR_HT ((uint32_t)0x00300000)
6168 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
6169 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
6170 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
6171 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
6172 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
6173 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
6174 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
6175 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
6176 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
6177 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
6178 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
6179 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
6180 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
6181 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
6182 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
6183 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
6184 #define RTC_TSTR_ST ((uint32_t)0x00000070)
6185 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
6186 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
6187 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
6188 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
6189 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
6190 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
6191 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
6192 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
6194 /******************** Bits definition for RTC_TSDR register *****************/
6195 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
6196 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
6197 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
6198 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
6199 #define RTC_TSDR_MT ((uint32_t)0x00001000)
6200 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
6201 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
6202 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
6203 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
6204 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
6205 #define RTC_TSDR_DT ((uint32_t)0x00000030)
6206 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
6207 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
6208 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
6209 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
6210 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
6211 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
6212 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
6214 /******************** Bits definition for RTC_TSSSR register ****************/
6215 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
6217 /******************** Bits definition for RTC_CAL register *****************/
6218 #define RTC_CALR_CALP ((uint32_t)0x00008000)
6219 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
6220 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
6221 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
6222 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
6223 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
6224 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
6225 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
6226 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
6227 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
6228 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
6229 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
6230 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
6232 /******************** Bits definition for RTC_TAFCR register ****************/
6233 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
6234 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
6235 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
6236 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
6237 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
6238 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
6239 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
6240 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
6241 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
6242 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
6243 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
6244 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
6245 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
6246 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
6247 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
6248 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
6249 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
6250 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
6251 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
6252 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
6254 /******************** Bits definition for RTC_ALRMASSR register *************/
6255 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
6256 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
6257 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
6258 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
6259 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
6260 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
6262 /******************** Bits definition for RTC_ALRMBSSR register *************/
6263 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
6264 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
6265 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
6266 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
6267 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
6268 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
6270 /******************** Bits definition for RTC_BKP0R register ****************/
6271 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
6273 /******************** Bits definition for RTC_BKP1R register ****************/
6274 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
6276 /******************** Bits definition for RTC_BKP2R register ****************/
6277 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
6279 /******************** Bits definition for RTC_BKP3R register ****************/
6280 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
6282 /******************** Bits definition for RTC_BKP4R register ****************/
6283 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
6285 /******************** Bits definition for RTC_BKP5R register ****************/
6286 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
6288 /******************** Bits definition for RTC_BKP6R register ****************/
6289 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
6291 /******************** Bits definition for RTC_BKP7R register ****************/
6292 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
6294 /******************** Bits definition for RTC_BKP8R register ****************/
6295 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
6297 /******************** Bits definition for RTC_BKP9R register ****************/
6298 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
6300 /******************** Bits definition for RTC_BKP10R register ***************/
6301 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
6303 /******************** Bits definition for RTC_BKP11R register ***************/
6304 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
6306 /******************** Bits definition for RTC_BKP12R register ***************/
6307 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
6309 /******************** Bits definition for RTC_BKP13R register ***************/
6310 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
6312 /******************** Bits definition for RTC_BKP14R register ***************/
6313 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
6315 /******************** Bits definition for RTC_BKP15R register ***************/
6316 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
6318 /******************** Number of backup registers ******************************/
6319 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
6321 /******************************************************************************/
6323 /* Serial Peripheral Interface (SPI) */
6325 /******************************************************************************/
6326 /******************* Bit definition for SPI_CR1 register ********************/
6327 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
6328 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
6329 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
6330 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
6331 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
6332 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
6333 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
6334 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
6335 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
6336 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
6337 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
6338 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
6339 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
6340 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
6341 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
6342 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
6343 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
6345 /******************* Bit definition for SPI_CR2 register ********************/
6346 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
6347 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
6348 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
6349 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
6350 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
6351 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
6352 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
6353 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
6354 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
6355 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
6356 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
6357 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
6358 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
6359 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
6360 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
6361 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
6363 /******************** Bit definition for SPI_SR register ********************/
6364 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
6365 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
6366 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
6367 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
6368 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
6369 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
6370 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
6371 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
6372 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
6373 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
6374 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
6375 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
6376 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
6377 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
6378 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
6380 /******************** Bit definition for SPI_DR register ********************/
6381 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
6383 /******************* Bit definition for SPI_CRCPR register ******************/
6384 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
6386 /****************** Bit definition for SPI_RXCRCR register ******************/
6387 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
6389 /****************** Bit definition for SPI_TXCRCR register ******************/
6390 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
6392 /****************** Bit definition for SPI_I2SCFGR register *****************/
6393 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
6394 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
6395 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
6396 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
6397 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
6398 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
6399 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6400 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6401 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
6402 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6403 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6404 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6405 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
6406 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
6408 /****************** Bit definition for SPI_I2SPR register *******************/
6409 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
6410 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
6411 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
6413 /******************************************************************************/
6415 /* System Configuration(SYSCFG) */
6417 /******************************************************************************/
6418 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
6419 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
6420 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
6421 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
6422 #define SYSCFG_CFGR1_MEM_MODE_2 ((uint32_t)0x00000004) /*!< Bit 1 */
6423 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
6424 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
6425 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
6426 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00007900) /*!< DMA remap mask */
6427 #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
6428 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
6429 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
6430 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
6431 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
6432 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
6433 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
6434 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
6435 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
6436 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
6437 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
6438 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
6439 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
6440 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
6441 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */
6442 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
6443 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
6444 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
6445 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
6446 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
6447 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
6448 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
6450 /***************** Bit definition for SYSCFG_RCR register *******************/
6451 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
6452 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
6453 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
6454 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
6455 #define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
6456 #define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
6457 #define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
6458 #define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
6459 #define SYSCFG_RCR_PAGE8 ((uint32_t)0x00000100) /*!< ICODE SRAM Write protection page 8 */
6460 #define SYSCFG_RCR_PAGE9 ((uint32_t)0x00000200) /*!< ICODE SRAM Write protection page 9 */
6461 #define SYSCFG_RCR_PAGE10 ((uint32_t)0x00000400) /*!< ICODE SRAM Write protection page 10 */
6462 #define SYSCFG_RCR_PAGE11 ((uint32_t)0x00000800) /*!< ICODE SRAM Write protection page 11 */
6463 #define SYSCFG_RCR_PAGE12 ((uint32_t)0x00001000) /*!< ICODE SRAM Write protection page 12 */
6464 #define SYSCFG_RCR_PAGE13 ((uint32_t)0x00002000) /*!< ICODE SRAM Write protection page 13 */
6465 #define SYSCFG_RCR_PAGE14 ((uint32_t)0x00004000) /*!< ICODE SRAM Write protection page 14 */
6466 #define SYSCFG_RCR_PAGE15 ((uint32_t)0x00008000) /*!< ICODE SRAM Write protection page 15 */
6468 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6469 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
6470 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
6471 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
6472 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
6475 * @brief EXTI0 configuration
6477 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
6478 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
6479 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
6480 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
6481 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
6482 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
6483 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
6484 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!< PH[0] pin */
6487 * @brief EXTI1 configuration
6489 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
6490 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
6491 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
6492 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
6493 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
6494 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
6495 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
6496 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!< PH[1] pin */
6499 * @brief EXTI2 configuration
6501 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
6502 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
6503 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
6504 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
6505 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
6506 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
6507 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
6510 * @brief EXTI3 configuration
6512 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
6513 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
6514 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
6515 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
6516 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
6517 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PE[3] pin */
6518 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
6520 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6521 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
6522 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
6523 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
6524 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
6527 * @brief EXTI4 configuration
6529 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
6530 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
6531 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
6532 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
6533 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
6534 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
6535 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
6536 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!< PH[4] pin */
6539 * @brief EXTI5 configuration
6541 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
6542 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
6543 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
6544 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
6545 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
6546 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
6547 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
6550 * @brief EXTI6 configuration
6552 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
6553 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
6554 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
6555 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
6556 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
6557 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
6558 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
6561 * @brief EXTI7 configuration
6563 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
6564 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
6565 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
6566 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
6567 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
6568 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
6569 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
6571 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6572 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
6573 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
6574 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
6575 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
6578 * @brief EXTI8 configuration
6580 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
6581 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
6582 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
6583 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
6584 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
6585 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
6586 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
6589 * @brief EXTI9 configuration
6591 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
6592 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
6593 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
6594 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
6595 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
6596 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
6597 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
6600 * @brief EXTI10 configuration
6602 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
6603 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
6604 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
6605 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
6606 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
6607 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
6608 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
6611 * @brief EXTI11 configuration
6613 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
6614 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
6615 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
6616 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
6617 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
6618 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
6619 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
6621 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
6622 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
6623 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
6624 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
6625 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
6628 * @brief EXTI12 configuration
6630 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
6631 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
6632 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
6633 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
6634 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
6635 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
6636 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
6639 * @brief EXTI13 configuration
6641 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
6642 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
6643 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
6644 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
6645 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
6646 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
6647 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
6650 * @brief EXTI14 configuration
6652 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
6653 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
6654 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
6655 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
6656 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
6657 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
6658 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
6661 * @brief EXTI15 configuration
6663 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
6664 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
6665 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
6666 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
6667 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
6668 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
6669 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
6671 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
6672 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
6673 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
6674 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
6675 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
6676 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
6678 /***************** Bit definition for SYSCFG_CFGR4 register *****************/
6679 #define SYSCFG_CFGR4_ADC12_EXT2_RMP ((uint32_t)0x00000001) /*!< ADC12 regular channel EXT2 remap */
6680 #define SYSCFG_CFGR4_ADC12_EXT3_RMP ((uint32_t)0x00000002) /*!< ADC12 regular channel EXT3 remap */
6681 #define SYSCFG_CFGR4_ADC12_EXT5_RMP ((uint32_t)0x00000004) /*!< ADC12 regular channel EXT5 remap */
6682 #define SYSCFG_CFGR4_ADC12_EXT13_RMP ((uint32_t)0x00000008) /*!< ADC12 regular channel EXT13 remap */
6683 #define SYSCFG_CFGR4_ADC12_EXT15_RMP ((uint32_t)0x00000010) /*!< ADC12 regular channel EXT15 remap */
6684 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP ((uint32_t)0x00000020) /*!< ADC12 injected channel JEXT3 remap */
6685 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP ((uint32_t)0x00000040) /*!< ADC12 injected channel JEXT6 remap */
6686 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP ((uint32_t)0x00000080) /*!< ADC12 injected channel JEXT13 remap */
6687 #define SYSCFG_CFGR4_ADC34_EXT5_RMP ((uint32_t)0x00000100) /*!< ADC34 regular channel EXT5 remap */
6688 #define SYSCFG_CFGR4_ADC34_EXT6_RMP ((uint32_t)0x00000200) /*!< ADC34 regular channel EXT6 remap */
6689 #define SYSCFG_CFGR4_ADC34_EXT15_RMP ((uint32_t)0x00000400) /*!< ADC34 regular channel EXT15 remap */
6690 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP ((uint32_t)0x00000800) /*!< ADC34 injected channel JEXT5 remap */
6691 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP ((uint32_t)0x00001000) /*!< ADC34 injected channel JEXT11 remap */
6692 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP ((uint32_t)0x00002000) /*!< ADC34 injected channel JEXT14 remap */
6694 /******************************************************************************/
6698 /******************************************************************************/
6699 /******************* Bit definition for TIM_CR1 register ********************/
6700 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
6701 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
6702 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
6703 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
6704 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
6706 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
6707 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
6708 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
6710 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
6712 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
6713 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6714 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6716 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
6718 /******************* Bit definition for TIM_CR2 register ********************/
6719 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
6720 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
6721 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
6723 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
6724 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6725 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6726 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
6728 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
6729 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
6730 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
6731 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
6732 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
6733 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
6734 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
6735 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
6736 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
6737 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
6739 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
6740 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
6741 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
6742 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
6743 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
6745 /******************* Bit definition for TIM_SMCR register *******************/
6746 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
6747 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6748 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6749 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6750 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
6752 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
6754 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
6755 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6756 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6757 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
6759 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
6761 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
6762 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6763 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6764 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
6765 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
6767 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
6768 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
6769 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
6771 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
6772 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
6774 /******************* Bit definition for TIM_DIER register *******************/
6775 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
6776 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
6777 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
6778 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
6779 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
6780 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
6781 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
6782 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
6783 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
6784 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
6785 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
6786 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
6787 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
6788 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
6789 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
6791 /******************** Bit definition for TIM_SR register ********************/
6792 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
6793 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
6794 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
6795 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
6796 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
6797 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
6798 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
6799 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
6800 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
6801 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
6802 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
6803 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
6804 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
6805 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
6806 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
6808 /******************* Bit definition for TIM_EGR register ********************/
6809 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
6810 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
6811 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
6812 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
6813 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
6814 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
6815 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
6816 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
6817 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
6819 /****************** Bit definition for TIM_CCMR1 register *******************/
6820 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6821 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6822 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6824 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
6825 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
6827 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6828 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6829 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6830 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
6831 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
6833 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
6835 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6836 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6837 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6839 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
6840 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
6842 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6843 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
6844 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
6845 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
6846 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
6848 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
6850 /*----------------------------------------------------------------------------*/
6852 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6853 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
6854 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
6856 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6857 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6858 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6859 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
6860 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
6862 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6863 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6864 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6866 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6867 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
6868 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
6869 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
6870 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
6872 /****************** Bit definition for TIM_CCMR2 register *******************/
6873 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6874 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6875 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6877 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
6878 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
6880 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6881 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6882 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6883 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
6884 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
6886 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
6888 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6889 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6890 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6892 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
6893 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
6895 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6896 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
6897 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
6898 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
6899 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
6901 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
6903 /*----------------------------------------------------------------------------*/
6905 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6906 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
6907 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
6909 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6910 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
6911 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
6912 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
6913 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
6915 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6916 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
6917 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
6919 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6920 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
6921 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
6922 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
6923 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
6925 /******************* Bit definition for TIM_CCER register *******************/
6926 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
6927 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
6928 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
6929 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
6930 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
6931 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
6932 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
6933 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
6934 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
6935 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
6936 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
6937 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
6938 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
6939 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
6940 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
6941 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
6942 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
6943 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
6944 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
6946 /******************* Bit definition for TIM_CNT register ********************/
6947 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
6948 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
6950 /******************* Bit definition for TIM_PSC register ********************/
6951 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
6953 /******************* Bit definition for TIM_ARR register ********************/
6954 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
6956 /******************* Bit definition for TIM_RCR register ********************/
6957 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
6959 /******************* Bit definition for TIM_CCR1 register *******************/
6960 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
6962 /******************* Bit definition for TIM_CCR2 register *******************/
6963 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
6965 /******************* Bit definition for TIM_CCR3 register *******************/
6966 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
6968 /******************* Bit definition for TIM_CCR4 register *******************/
6969 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
6971 /******************* Bit definition for TIM_CCR5 register *******************/
6972 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
6973 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
6974 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
6975 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
6977 /******************* Bit definition for TIM_CCR6 register *******************/
6978 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
6980 /******************* Bit definition for TIM_BDTR register *******************/
6981 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6982 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6983 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6984 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6985 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
6986 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
6987 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
6988 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
6989 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
6991 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
6992 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6993 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6995 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
6996 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
6997 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
6998 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
6999 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
7000 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
7002 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
7003 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
7005 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
7006 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
7008 /******************* Bit definition for TIM_DCR register ********************/
7009 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
7010 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7011 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7012 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7013 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7014 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
7016 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
7017 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
7018 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
7019 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
7020 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
7021 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
7023 /******************* Bit definition for TIM_DMAR register *******************/
7024 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
7026 /******************* Bit definition for TIM16_OR register ********************/
7027 #define TIM16_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
7028 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7029 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7031 /******************* Bit definition for TIM1_OR register ********************/
7032 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
7033 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7034 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7035 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7036 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7038 /******************* Bit definition for TIM8_OR register ********************/
7039 #define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
7040 #define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7041 #define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7042 #define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7043 #define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7045 /******************* Bit definition for TIM20_OR register *******************/
7046 #define TIM20_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
7047 #define TIM20_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7048 #define TIM20_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7049 #define TIM20_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7050 #define TIM20_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7052 /****************** Bit definition for TIM_CCMR3 register *******************/
7053 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
7054 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
7056 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
7057 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7058 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7059 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7060 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7062 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
7064 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
7065 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
7067 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
7068 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7069 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7070 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7071 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7073 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
7075 /******************************************************************************/
7077 /* Touch Sensing Controller (TSC) */
7079 /******************************************************************************/
7080 /******************* Bit definition for TSC_CR register *********************/
7081 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
7082 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
7083 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
7084 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
7085 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
7087 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
7088 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
7089 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
7090 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
7092 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
7093 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7094 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7095 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7097 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
7098 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
7100 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
7101 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
7102 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
7103 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
7104 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
7105 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
7106 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
7107 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
7109 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
7110 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
7111 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
7112 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
7113 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
7115 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
7116 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
7117 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
7118 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
7119 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
7121 /******************* Bit definition for TSC_IER register ********************/
7122 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
7123 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
7125 /******************* Bit definition for TSC_ICR register ********************/
7126 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
7127 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
7129 /******************* Bit definition for TSC_ISR register ********************/
7130 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
7131 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
7133 /******************* Bit definition for TSC_IOHCR register ******************/
7134 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
7135 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
7136 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
7137 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
7138 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
7139 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
7140 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
7141 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
7142 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
7143 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
7144 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
7145 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
7146 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
7147 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
7148 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
7149 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
7150 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
7151 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
7152 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
7153 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
7154 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
7155 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
7156 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
7157 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
7158 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
7159 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
7160 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
7161 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
7162 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
7163 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
7164 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
7165 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
7167 /******************* Bit definition for TSC_IOASCR register *****************/
7168 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
7169 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
7170 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
7171 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
7172 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
7173 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
7174 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
7175 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
7176 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
7177 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
7178 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
7179 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
7180 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
7181 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
7182 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
7183 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
7184 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
7185 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
7186 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
7187 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
7188 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
7189 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
7190 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
7191 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
7192 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
7193 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
7194 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
7195 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
7196 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
7197 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
7198 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
7199 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
7201 /******************* Bit definition for TSC_IOSCR register ******************/
7202 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
7203 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
7204 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
7205 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
7206 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
7207 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
7208 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
7209 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
7210 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
7211 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
7212 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
7213 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
7214 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
7215 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
7216 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
7217 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
7218 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
7219 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
7220 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
7221 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
7222 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
7223 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
7224 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
7225 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
7226 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
7227 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
7228 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
7229 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
7230 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
7231 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
7232 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
7233 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
7235 /******************* Bit definition for TSC_IOCCR register ******************/
7236 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
7237 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
7238 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
7239 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
7240 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
7241 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
7242 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
7243 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
7244 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
7245 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
7246 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
7247 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
7248 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
7249 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
7250 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
7251 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
7252 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
7253 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
7254 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
7255 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
7256 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
7257 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
7258 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
7259 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
7260 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
7261 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
7262 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
7263 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
7264 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
7265 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
7266 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
7267 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
7269 /******************* Bit definition for TSC_IOGCSR register *****************/
7270 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
7271 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
7272 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
7273 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
7274 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
7275 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
7276 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
7277 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
7278 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
7279 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
7280 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
7281 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
7282 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
7283 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
7284 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
7285 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
7287 /******************* Bit definition for TSC_IOGXCR register *****************/
7288 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
7290 /******************************************************************************/
7292 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
7294 /******************************************************************************/
7295 /****************** Bit definition for USART_CR1 register *******************/
7296 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
7297 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
7298 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
7299 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
7300 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
7301 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
7302 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
7303 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
7304 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
7305 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
7306 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
7307 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
7308 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
7309 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
7310 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
7311 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
7312 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
7313 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
7314 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
7315 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
7316 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
7317 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
7318 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
7319 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
7320 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
7321 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
7322 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
7323 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
7324 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
7325 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
7326 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
7327 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
7329 /****************** Bit definition for USART_CR2 register *******************/
7330 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
7331 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
7332 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
7333 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
7334 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
7335 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
7336 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
7337 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
7338 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
7339 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
7340 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
7341 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
7342 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
7343 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
7344 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
7345 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
7346 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
7347 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
7348 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
7349 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
7350 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
7351 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
7353 /****************** Bit definition for USART_CR3 register *******************/
7354 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
7355 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
7356 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
7357 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
7358 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
7359 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
7360 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
7361 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
7362 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
7363 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
7364 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
7365 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
7366 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
7367 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
7368 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
7369 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
7370 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
7371 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
7372 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
7373 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
7374 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
7375 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
7376 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
7377 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
7379 /****************** Bit definition for USART_BRR register *******************/
7380 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
7381 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
7383 /****************** Bit definition for USART_GTPR register ******************/
7384 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
7385 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
7388 /******************* Bit definition for USART_RTOR register *****************/
7389 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
7390 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
7392 /******************* Bit definition for USART_RQR register ******************/
7393 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
7394 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
7395 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
7396 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
7397 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
7399 /******************* Bit definition for USART_ISR register ******************/
7400 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
7401 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
7402 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
7403 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
7404 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
7405 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
7406 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
7407 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
7408 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
7409 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
7410 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
7411 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
7412 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
7413 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
7414 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
7415 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
7416 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
7417 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
7418 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
7419 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
7420 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
7421 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
7423 /******************* Bit definition for USART_ICR register ******************/
7424 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
7425 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
7426 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
7427 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
7428 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
7429 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
7430 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
7431 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
7432 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
7433 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
7434 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
7435 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
7437 /******************* Bit definition for USART_RDR register ******************/
7438 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
7440 /******************* Bit definition for USART_TDR register ******************/
7441 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
7443 /******************************************************************************/
7445 /* USB Device General registers */
7447 /******************************************************************************/
7448 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
7449 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
7450 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
7451 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
7452 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
7453 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
7455 /**************************** ISTR interrupt events *************************/
7456 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
7457 #define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
7458 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
7459 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
7460 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
7461 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
7462 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
7463 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
7464 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
7465 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
7466 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
7468 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
7469 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
7470 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
7471 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
7472 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
7473 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
7474 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
7475 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
7476 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
7478 /************************* CNTR control register bits definitions ***********/
7479 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
7480 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
7481 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
7482 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
7483 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
7484 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
7485 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
7486 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
7487 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
7488 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
7489 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
7490 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
7491 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
7492 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
7493 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
7495 /*************************** LPM register bits definitions ******************/
7496 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
7497 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
7498 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
7499 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
7501 /******************** FNR Frame Number Register bit definitions ************/
7502 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
7503 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
7504 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
7505 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
7506 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
7508 /******************** DADDR Device ADDRess bit definitions ****************/
7509 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
7510 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
7512 /****************************** Endpoint register *************************/
7513 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
7514 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
7515 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
7516 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
7517 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
7518 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
7519 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
7520 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
7522 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
7523 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
7524 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
7525 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
7526 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
7527 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
7528 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
7529 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
7530 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
7531 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
7533 /* EndPoint REGister MASK (no toggle fields) */
7534 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
7535 /*!< EP_TYPE[1:0] EndPoint TYPE */
7536 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
7537 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
7538 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
7539 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
7540 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
7541 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
7543 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
7544 /*!< STAT_TX[1:0] STATus for TX transfer */
7545 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
7546 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
7547 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
7548 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
7549 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
7550 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
7551 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
7552 /*!< STAT_RX[1:0] STATus for RX transfer */
7553 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
7554 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
7555 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
7556 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
7557 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
7558 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
7559 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
7561 /******************************************************************************/
7563 /* Window WATCHDOG */
7565 /******************************************************************************/
7566 /******************* Bit definition for WWDG_CR register ********************/
7567 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
7568 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
7569 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
7570 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
7571 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
7572 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
7573 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
7574 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
7576 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
7578 /******************* Bit definition for WWDG_CFR register *******************/
7579 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
7580 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
7581 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
7582 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
7583 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
7584 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
7585 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
7586 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
7588 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
7589 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
7590 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
7592 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
7594 /******************* Bit definition for WWDG_SR register ********************/
7595 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
7605 /** @addtogroup Exported_macros
7609 /****************************** ADC Instances *********************************/
7610 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7611 ((INSTANCE) == ADC2) || \
7612 ((INSTANCE) == ADC3) || \
7613 ((INSTANCE) == ADC4))
7615 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7616 ((INSTANCE) == ADC3))
7618 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON) || \
7619 ((INSTANCE) == ADC3_4_COMMON))
7621 /****************************** CAN Instances *********************************/
7622 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
7624 /****************************** COMP Instances ********************************/
7625 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
7626 ((INSTANCE) == COMP2) || \
7627 ((INSTANCE) == COMP3) || \
7628 ((INSTANCE) == COMP4) || \
7629 ((INSTANCE) == COMP5) || \
7630 ((INSTANCE) == COMP6) || \
7631 ((INSTANCE) == COMP7))
7633 /******************** COMP Instances with window mode capability **************/
7634 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
7635 ((INSTANCE) == COMP4) || \
7636 ((INSTANCE) == COMP6))
7638 /****************************** CRC Instances *********************************/
7639 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7641 /****************************** DAC Instances *********************************/
7642 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
7644 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
7645 (((INSTANCE) == DAC1) && \
7646 (((CHANNEL) == DAC_CHANNEL_1) || \
7647 ((CHANNEL) == DAC_CHANNEL_2)))
7649 /****************************** DMA Instances *********************************/
7650 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
7651 ((INSTANCE) == DMA1_Channel2) || \
7652 ((INSTANCE) == DMA1_Channel3) || \
7653 ((INSTANCE) == DMA1_Channel4) || \
7654 ((INSTANCE) == DMA1_Channel5) || \
7655 ((INSTANCE) == DMA1_Channel6) || \
7656 ((INSTANCE) == DMA1_Channel7) || \
7657 ((INSTANCE) == DMA2_Channel1) || \
7658 ((INSTANCE) == DMA2_Channel2) || \
7659 ((INSTANCE) == DMA2_Channel3) || \
7660 ((INSTANCE) == DMA2_Channel4) || \
7661 ((INSTANCE) == DMA2_Channel5))
7663 /****************************** GPIO Instances ********************************/
7664 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7665 ((INSTANCE) == GPIOB) || \
7666 ((INSTANCE) == GPIOC) || \
7667 ((INSTANCE) == GPIOD) || \
7668 ((INSTANCE) == GPIOE) || \
7669 ((INSTANCE) == GPIOF) || \
7670 ((INSTANCE) == GPIOG) || \
7671 ((INSTANCE) == GPIOH))
7673 /****************************** I2C Instances *********************************/
7674 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7675 ((INSTANCE) == I2C2) || \
7676 ((INSTANCE) == I2C3))
7678 /****************************** I2S Instances *********************************/
7679 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
7680 ((INSTANCE) == SPI3))
7682 /****************************** IWDG Instances ********************************/
7683 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
7685 /****************************** OPAMP Instances *******************************/
7686 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
7687 ((INSTANCE) == OPAMP2) || \
7688 ((INSTANCE) == OPAMP3) || \
7689 ((INSTANCE) == OPAMP4))
7691 /****************************** RTC Instances *********************************/
7692 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7694 /****************************** SMBUS Instances *******************************/
7695 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7696 ((INSTANCE) == I2C2) || \
7697 ((INSTANCE) == I2C3))
7699 /****************************** SPI Instances *********************************/
7700 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7701 ((INSTANCE) == SPI2) || \
7702 ((INSTANCE) == SPI3) || \
7703 ((INSTANCE) == SPI4))
7705 /******************* TIM Instances : All supported instances ******************/
7706 #define IS_TIM_INSTANCE(INSTANCE)\
7707 (((INSTANCE) == TIM1) || \
7708 ((INSTANCE) == TIM2) || \
7709 ((INSTANCE) == TIM3) || \
7710 ((INSTANCE) == TIM4) || \
7711 ((INSTANCE) == TIM6) || \
7712 ((INSTANCE) == TIM7) || \
7713 ((INSTANCE) == TIM8) || \
7714 ((INSTANCE) == TIM15) || \
7715 ((INSTANCE) == TIM16) || \
7716 ((INSTANCE) == TIM17) || \
7717 ((INSTANCE) == TIM20))
7719 /******************* TIM Instances : at least 1 capture/compare channel *******/
7720 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
7721 (((INSTANCE) == TIM1) || \
7722 ((INSTANCE) == TIM2) || \
7723 ((INSTANCE) == TIM3) || \
7724 ((INSTANCE) == TIM4) || \
7725 ((INSTANCE) == TIM8) || \
7726 ((INSTANCE) == TIM15) || \
7727 ((INSTANCE) == TIM16) || \
7728 ((INSTANCE) == TIM17) || \
7729 ((INSTANCE) == TIM20))
7731 /****************** TIM Instances : at least 2 capture/compare channels *******/
7732 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
7733 (((INSTANCE) == TIM1) || \
7734 ((INSTANCE) == TIM2) || \
7735 ((INSTANCE) == TIM3) || \
7736 ((INSTANCE) == TIM4) || \
7737 ((INSTANCE) == TIM8) || \
7738 ((INSTANCE) == TIM15) || \
7739 ((INSTANCE) == TIM20))
7741 /****************** TIM Instances : at least 3 capture/compare channels *******/
7742 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
7743 (((INSTANCE) == TIM1) || \
7744 ((INSTANCE) == TIM2) || \
7745 ((INSTANCE) == TIM3) || \
7746 ((INSTANCE) == TIM4) || \
7747 ((INSTANCE) == TIM8) || \
7748 ((INSTANCE) == TIM20))
7750 /****************** TIM Instances : at least 4 capture/compare channels *******/
7751 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
7752 (((INSTANCE) == TIM1) || \
7753 ((INSTANCE) == TIM2) || \
7754 ((INSTANCE) == TIM3) || \
7755 ((INSTANCE) == TIM4) || \
7756 ((INSTANCE) == TIM8) || \
7757 ((INSTANCE) == TIM20))
7759 /****************** TIM Instances : at least 5 capture/compare channels *******/
7760 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
7761 (((INSTANCE) == TIM1) || \
7762 ((INSTANCE) == TIM8) || \
7763 ((INSTANCE) == TIM20))
7765 /****************** TIM Instances : at least 6 capture/compare channels *******/
7766 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
7767 (((INSTANCE) == TIM1) || \
7768 ((INSTANCE) == TIM8) || \
7769 ((INSTANCE) == TIM20))
7771 /************************** TIM Instances : Advanced-control timers ***********/
7773 /****************** TIM Instances : supporting clock selection ****************/
7774 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
7775 (((INSTANCE) == TIM1) || \
7776 ((INSTANCE) == TIM2) || \
7777 ((INSTANCE) == TIM3) || \
7778 ((INSTANCE) == TIM4) || \
7779 ((INSTANCE) == TIM8) || \
7780 ((INSTANCE) == TIM15) || \
7781 ((INSTANCE) == TIM20))
7783 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
7784 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
7785 (((INSTANCE) == TIM1) || \
7786 ((INSTANCE) == TIM2) || \
7787 ((INSTANCE) == TIM3) || \
7788 ((INSTANCE) == TIM4) || \
7789 ((INSTANCE) == TIM8) || \
7790 ((INSTANCE) == TIM20))
7792 /****************** TIM Instances : supporting external clock mode 2 **********/
7793 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
7794 (((INSTANCE) == TIM1) || \
7795 ((INSTANCE) == TIM2) || \
7796 ((INSTANCE) == TIM3) || \
7797 ((INSTANCE) == TIM4) || \
7798 ((INSTANCE) == TIM8) || \
7799 ((INSTANCE) == TIM20))
7801 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
7802 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
7803 (((INSTANCE) == TIM1) || \
7804 ((INSTANCE) == TIM2) || \
7805 ((INSTANCE) == TIM3) || \
7806 ((INSTANCE) == TIM4) || \
7807 ((INSTANCE) == TIM8) || \
7808 ((INSTANCE) == TIM15) || \
7809 ((INSTANCE) == TIM20))
7811 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
7812 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
7813 (((INSTANCE) == TIM1) || \
7814 ((INSTANCE) == TIM2) || \
7815 ((INSTANCE) == TIM3) || \
7816 ((INSTANCE) == TIM4) || \
7817 ((INSTANCE) == TIM8) || \
7818 ((INSTANCE) == TIM15) || \
7819 ((INSTANCE) == TIM20))
7821 /****************** TIM Instances : supporting OCxREF clear *******************/
7822 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
7823 (((INSTANCE) == TIM1) || \
7824 ((INSTANCE) == TIM2) || \
7825 ((INSTANCE) == TIM3) || \
7826 ((INSTANCE) == TIM4) || \
7827 ((INSTANCE) == TIM8) || \
7828 ((INSTANCE) == TIM20))
7830 /****************** TIM Instances : supporting encoder interface **************/
7831 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
7832 (((INSTANCE) == TIM1) || \
7833 ((INSTANCE) == TIM2) || \
7834 ((INSTANCE) == TIM3) || \
7835 ((INSTANCE) == TIM4) || \
7836 ((INSTANCE) == TIM8) || \
7837 ((INSTANCE) == TIM20))
7839 /****************** TIM Instances : supporting Hall interface *****************/
7840 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
7841 (((INSTANCE) == TIM1) || \
7842 ((INSTANCE) == TIM8) || \
7843 ((INSTANCE) == TIM20))
7845 /****************** TIM Instances : supporting input XOR function *************/
7846 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
7847 (((INSTANCE) == TIM1) || \
7848 ((INSTANCE) == TIM2) || \
7849 ((INSTANCE) == TIM3) || \
7850 ((INSTANCE) == TIM4) || \
7851 ((INSTANCE) == TIM8) || \
7852 ((INSTANCE) == TIM15) || \
7853 ((INSTANCE) == TIM20))
7855 /****************** TIM Instances : supporting master mode ********************/
7856 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
7857 (((INSTANCE) == TIM1) || \
7858 ((INSTANCE) == TIM2) || \
7859 ((INSTANCE) == TIM3) || \
7860 ((INSTANCE) == TIM4) || \
7861 ((INSTANCE) == TIM6) || \
7862 ((INSTANCE) == TIM7) || \
7863 ((INSTANCE) == TIM8) || \
7864 ((INSTANCE) == TIM15) || \
7865 ((INSTANCE) == TIM20))
7867 /****************** TIM Instances : supporting slave mode *********************/
7868 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
7869 (((INSTANCE) == TIM1) || \
7870 ((INSTANCE) == TIM2) || \
7871 ((INSTANCE) == TIM3) || \
7872 ((INSTANCE) == TIM4) || \
7873 ((INSTANCE) == TIM8) || \
7874 ((INSTANCE) == TIM15) || \
7875 ((INSTANCE) == TIM20))
7877 /****************** TIM Instances : supporting synchronization ****************/
7878 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
7879 (((INSTANCE) == TIM1) || \
7880 ((INSTANCE) == TIM2) || \
7881 ((INSTANCE) == TIM3) || \
7882 ((INSTANCE) == TIM4) || \
7883 ((INSTANCE) == TIM6) || \
7884 ((INSTANCE) == TIM7) || \
7885 ((INSTANCE) == TIM8) || \
7886 ((INSTANCE) == TIM15) || \
7887 ((INSTANCE) == TIM20))
7889 /****************** TIM Instances : supporting 32 bits counter ****************/
7890 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
7891 ((INSTANCE) == TIM2)
7893 /****************** TIM Instances : supporting DMA burst **********************/
7894 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
7895 (((INSTANCE) == TIM1) || \
7896 ((INSTANCE) == TIM2) || \
7897 ((INSTANCE) == TIM3) || \
7898 ((INSTANCE) == TIM4) || \
7899 ((INSTANCE) == TIM8) || \
7900 ((INSTANCE) == TIM15) || \
7901 ((INSTANCE) == TIM16) || \
7902 ((INSTANCE) == TIM17) || \
7903 ((INSTANCE) == TIM20))
7905 /****************** TIM Instances : supporting the break function *************/
7906 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
7907 (((INSTANCE) == TIM1) || \
7908 ((INSTANCE) == TIM8) || \
7909 ((INSTANCE) == TIM15) || \
7910 ((INSTANCE) == TIM16) || \
7911 ((INSTANCE) == TIM17) || \
7912 ((INSTANCE) == TIM20))
7914 /****************** TIM Instances : supporting input/output channel(s) ********/
7915 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7916 ((((INSTANCE) == TIM1) && \
7917 (((CHANNEL) == TIM_CHANNEL_1) || \
7918 ((CHANNEL) == TIM_CHANNEL_2) || \
7919 ((CHANNEL) == TIM_CHANNEL_3) || \
7920 ((CHANNEL) == TIM_CHANNEL_4) || \
7921 ((CHANNEL) == TIM_CHANNEL_5) || \
7922 ((CHANNEL) == TIM_CHANNEL_6))) \
7924 (((INSTANCE) == TIM2) && \
7925 (((CHANNEL) == TIM_CHANNEL_1) || \
7926 ((CHANNEL) == TIM_CHANNEL_2) || \
7927 ((CHANNEL) == TIM_CHANNEL_3) || \
7928 ((CHANNEL) == TIM_CHANNEL_4))) \
7930 (((INSTANCE) == TIM3) && \
7931 (((CHANNEL) == TIM_CHANNEL_1) || \
7932 ((CHANNEL) == TIM_CHANNEL_2) || \
7933 ((CHANNEL) == TIM_CHANNEL_3) || \
7934 ((CHANNEL) == TIM_CHANNEL_4))) \
7936 (((INSTANCE) == TIM4) && \
7937 (((CHANNEL) == TIM_CHANNEL_1) || \
7938 ((CHANNEL) == TIM_CHANNEL_2) || \
7939 ((CHANNEL) == TIM_CHANNEL_3) || \
7940 ((CHANNEL) == TIM_CHANNEL_4))) \
7942 (((INSTANCE) == TIM8) && \
7943 (((CHANNEL) == TIM_CHANNEL_1) || \
7944 ((CHANNEL) == TIM_CHANNEL_2) || \
7945 ((CHANNEL) == TIM_CHANNEL_3) || \
7946 ((CHANNEL) == TIM_CHANNEL_4) || \
7947 ((CHANNEL) == TIM_CHANNEL_5) || \
7948 ((CHANNEL) == TIM_CHANNEL_6))) \
7950 (((INSTANCE) == TIM15) && \
7951 (((CHANNEL) == TIM_CHANNEL_1) || \
7952 ((CHANNEL) == TIM_CHANNEL_2))) \
7954 (((INSTANCE) == TIM16) && \
7955 (((CHANNEL) == TIM_CHANNEL_1))) \
7957 (((INSTANCE) == TIM17) && \
7958 (((CHANNEL) == TIM_CHANNEL_1))) \
7960 (((INSTANCE) == TIM20) && \
7961 (((CHANNEL) == TIM_CHANNEL_1) || \
7962 ((CHANNEL) == TIM_CHANNEL_2) || \
7963 ((CHANNEL) == TIM_CHANNEL_3) || \
7964 ((CHANNEL) == TIM_CHANNEL_4) || \
7965 ((CHANNEL) == TIM_CHANNEL_5) || \
7966 ((CHANNEL) == TIM_CHANNEL_6))))
7968 /****************** TIM Instances : supporting complementary output(s) ********/
7969 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7970 ((((INSTANCE) == TIM1) && \
7971 (((CHANNEL) == TIM_CHANNEL_1) || \
7972 ((CHANNEL) == TIM_CHANNEL_2) || \
7973 ((CHANNEL) == TIM_CHANNEL_3))) \
7975 (((INSTANCE) == TIM8) && \
7976 (((CHANNEL) == TIM_CHANNEL_1) || \
7977 ((CHANNEL) == TIM_CHANNEL_2) || \
7978 ((CHANNEL) == TIM_CHANNEL_3))) \
7980 (((INSTANCE) == TIM15) && \
7981 ((CHANNEL) == TIM_CHANNEL_1)) \
7983 (((INSTANCE) == TIM16) && \
7984 ((CHANNEL) == TIM_CHANNEL_1)) \
7986 (((INSTANCE) == TIM17) && \
7987 ((CHANNEL) == TIM_CHANNEL_1)) \
7989 (((INSTANCE) == TIM20) && \
7990 (((CHANNEL) == TIM_CHANNEL_1) || \
7991 ((CHANNEL) == TIM_CHANNEL_2) || \
7992 ((CHANNEL) == TIM_CHANNEL_3))))
7994 /****************** TIM Instances : supporting counting mode selection ********/
7995 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
7996 (((INSTANCE) == TIM1) || \
7997 ((INSTANCE) == TIM2) || \
7998 ((INSTANCE) == TIM3) || \
7999 ((INSTANCE) == TIM4) || \
8000 ((INSTANCE) == TIM8) || \
8001 ((INSTANCE) == TIM20))
8003 /****************** TIM Instances : supporting repetition counter *************/
8004 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
8005 (((INSTANCE) == TIM1) || \
8006 ((INSTANCE) == TIM8) || \
8007 ((INSTANCE) == TIM15) || \
8008 ((INSTANCE) == TIM16) || \
8009 ((INSTANCE) == TIM17) || \
8010 ((INSTANCE) == TIM20))
8012 /****************** TIM Instances : supporting clock division *****************/
8013 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
8014 (((INSTANCE) == TIM1) || \
8015 ((INSTANCE) == TIM2) || \
8016 ((INSTANCE) == TIM3) || \
8017 ((INSTANCE) == TIM4) || \
8018 ((INSTANCE) == TIM8) || \
8019 ((INSTANCE) == TIM15) || \
8020 ((INSTANCE) == TIM16) || \
8021 ((INSTANCE) == TIM17) || \
8022 ((INSTANCE) == TIM20))
8024 /****************** TIM Instances : supporting 2 break inputs *****************/
8025 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
8026 (((INSTANCE) == TIM1) || \
8027 ((INSTANCE) == TIM8) || \
8028 ((INSTANCE) == TIM20))
8030 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
8031 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
8032 (((INSTANCE) == TIM1) || \
8033 ((INSTANCE) == TIM8) || \
8034 ((INSTANCE) == TIM20))
8036 /****************** TIM Instances : supporting DMA generation on Update events*/
8037 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
8038 (((INSTANCE) == TIM1) || \
8039 ((INSTANCE) == TIM2) || \
8040 ((INSTANCE) == TIM3) || \
8041 ((INSTANCE) == TIM4) || \
8042 ((INSTANCE) == TIM6) || \
8043 ((INSTANCE) == TIM7) || \
8044 ((INSTANCE) == TIM8) || \
8045 ((INSTANCE) == TIM15) || \
8046 ((INSTANCE) == TIM16) || \
8047 ((INSTANCE) == TIM17) || \
8048 ((INSTANCE) == TIM20))
8050 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
8051 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
8052 (((INSTANCE) == TIM1) || \
8053 ((INSTANCE) == TIM2) || \
8054 ((INSTANCE) == TIM3) || \
8055 ((INSTANCE) == TIM4) || \
8056 ((INSTANCE) == TIM8) || \
8057 ((INSTANCE) == TIM15) || \
8058 ((INSTANCE) == TIM16) || \
8059 ((INSTANCE) == TIM17) || \
8060 ((INSTANCE) == TIM20))
8062 /****************** TIM Instances : supporting commutation event generation ***/
8063 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
8064 (((INSTANCE) == TIM1) || \
8065 ((INSTANCE) == TIM8) || \
8066 ((INSTANCE) == TIM15) || \
8067 ((INSTANCE) == TIM16) || \
8068 ((INSTANCE) == TIM17) || \
8069 ((INSTANCE) == TIM20))
8071 /****************** TIM Instances : supporting remapping capability ***********/
8072 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
8073 (((INSTANCE) == TIM1) || \
8074 ((INSTANCE) == TIM8) || \
8075 ((INSTANCE) == TIM16) || \
8076 ((INSTANCE) == TIM20))
8078 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
8079 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
8080 (((INSTANCE) == TIM1) || \
8081 ((INSTANCE) == TIM8) || \
8082 ((INSTANCE) == TIM20))
8084 /****************************** TSC Instances *********************************/
8085 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
8087 /******************** USART Instances : Synchronous mode **********************/
8088 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8089 ((INSTANCE) == USART2) || \
8090 ((INSTANCE) == USART3))
8092 /****************** USART Instances : Auto Baud Rate detection ****************/
8093 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8094 ((INSTANCE) == USART2) || \
8095 ((INSTANCE) == USART3))
8097 /******************** UART Instances : Asynchronous mode **********************/
8098 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8099 ((INSTANCE) == USART2) || \
8100 ((INSTANCE) == USART3) || \
8101 ((INSTANCE) == UART4) || \
8102 ((INSTANCE) == UART5))
8104 /******************** UART Instances : Half-Duplex mode **********************/
8105 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8106 ((INSTANCE) == USART2) || \
8107 ((INSTANCE) == USART3) || \
8108 ((INSTANCE) == UART4) || \
8109 ((INSTANCE) == UART5))
8111 /******************** UART Instances : LIN mode **********************/
8112 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8113 ((INSTANCE) == USART2) || \
8114 ((INSTANCE) == USART3) || \
8115 ((INSTANCE) == UART4) || \
8116 ((INSTANCE) == UART5))
8118 /******************** UART Instances : Wake-up from Stop mode **********************/
8119 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8120 ((INSTANCE) == USART2) || \
8121 ((INSTANCE) == USART3) || \
8122 ((INSTANCE) == UART4) || \
8123 ((INSTANCE) == UART5))
8125 /****************** UART Instances : Hardware Flow control ********************/
8126 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8127 ((INSTANCE) == USART2) || \
8128 ((INSTANCE) == USART3))
8130 /****************** UART Instances : Auto Baud Rate detection *****************/
8131 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8132 ((INSTANCE) == USART2) || \
8133 ((INSTANCE) == USART3))
8135 /****************** UART Instances : Driver Enable ****************************/
8136 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8137 ((INSTANCE) == USART2) || \
8138 ((INSTANCE) == USART3))
8140 /********************* UART Instances : Smard card mode ***********************/
8141 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8142 ((INSTANCE) == USART2) || \
8143 ((INSTANCE) == USART3))
8145 /*********************** UART Instances : IRDA mode ***************************/
8146 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8147 ((INSTANCE) == USART2) || \
8148 ((INSTANCE) == USART3) || \
8149 ((INSTANCE) == UART4) || \
8150 ((INSTANCE) == UART5))
8152 /****************************** USB Instances *********************************/
8153 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
8155 /****************************** WWDG Instances ********************************/
8156 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8163 /******************************************************************************/
8164 /* For a painless codes migration between the STM32F3xx device product */
8165 /* lines, the aliases defined below are put in place to overcome the */
8166 /* differences in the interrupt handlers and IRQn definitions. */
8167 /* No need to update developed interrupt code when moving across */
8168 /* product lines within the same STM32F3 Family */
8169 /******************************************************************************/
8171 /* Aliases for __IRQn */
8173 #define ADC1_IRQn ADC1_2_IRQn
8174 #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
8175 #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
8176 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
8177 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
8178 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
8179 #define COMP_IRQn COMP1_2_3_IRQn
8180 #define COMP2_IRQn COMP1_2_3_IRQn
8181 #define COMP1_2_IRQn COMP1_2_3_IRQn
8182 #define COMP4_6_IRQn COMP4_5_6_IRQn
8183 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn
8185 /* Aliases for __IRQHandler */
8186 #define ADC1_IRQHandler ADC1_2_IRQHandler
8187 #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
8188 #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
8189 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
8190 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
8191 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
8192 #define COMP_IRQHandler COMP1_2_3_IRQHandler
8193 #define COMP2_IRQHandler COMP1_2_3_IRQHandler
8194 #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
8195 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
8196 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
8200 #endif /* __cplusplus */
8202 #endif /* __STM32F303xE_H */
8212 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/