2 ******************************************************************************
3 * @file stm32f3xx_hal.h
4 * @author MCD Application Team
7 * @brief This file contains all the functions prototypes for the HAL
9 ******************************************************************************
12 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
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19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 ******************************************************************************
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef __STM32F3xx_HAL_H
41 #define __STM32F3xx_HAL_H
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f3xx_hal_conf.h"
50 /** @addtogroup STM32F3xx_HAL_Driver
58 /* Exported types ------------------------------------------------------------*/
59 /* Exported constants --------------------------------------------------------*/
60 /** @defgroup HAL_Exported_Constants HAL Exported Constants
63 /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
64 * @brief SYSCFG registers bit address in the alias region
67 /* ------------ SYSCFG registers bit address in the alias region -------------*/
68 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
69 /* --- CFGR2 Register ---*/
70 /* Alias word address of BYP_ADDR_PAR bit */
71 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
72 #define BYPADDRPAR_BitNumber 0x04
73 #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
78 #if defined(SYSCFG_CFGR1_DMA_RMP)
79 /** @defgroup HAL_DMA_Remapping DMA Remapping
80 * Elements values convention: 0xXXYYYYYY
81 * - YYYYYY : Position in the register
82 * - XX : Register index
83 * - 00: CFGR1 register in SYSCFG
84 * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
87 #define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
88 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
89 #define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap
90 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
91 #define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap
92 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
93 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
94 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
95 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
96 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
97 #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
98 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
99 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
100 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
101 #if defined(SYSCFG_CFGR3_DMA_RMP)
102 #if !defined(HAL_REMAP_CFGR3_MASK)
103 #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
106 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
107 11: Map on DMA1 channel 2 */
108 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
109 01: Map on DMA1 channel 4 */
110 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
111 10: Map on DMA1 channel 6 */
112 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
113 11: Map on DMA1 channel 3 */
114 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
115 01: Map on DMA1 channel 5 */
116 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
117 10: Map on DMA1 channel 7 */
118 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
119 11: Map on DMA1 channel 7 */
120 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
121 01: Map on DMA1 channel 3 */
122 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
123 10: Map on DMA1 channel 5 */
124 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
125 11: Map on DMA1 channel 6 */
126 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
127 01: Map on DMA1 channel 2 */
128 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
129 10: Map on DMA1 channel 4 */
130 #define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap
131 x0: No remap (ADC2 on DMA2)
132 10: Map on DMA1 channel 2 */
133 #define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap
134 11: Map on DMA1 channel 4 */
135 #endif /* SYSCFG_CFGR3_DMA_RMP */
137 #if defined(SYSCFG_CFGR3_DMA_RMP)
138 #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
139 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
140 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
141 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
142 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
143 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
144 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
145 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
146 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
147 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
148 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
149 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
150 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
151 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
152 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
153 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
154 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
155 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
156 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
157 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
158 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
160 #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
161 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
162 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
163 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
164 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
165 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
166 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
167 #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
171 #endif /* SYSCFG_CFGR1_DMA_RMP */
173 /** @defgroup HAL_Trigger_Remapping Trigger Remapping
174 * Elements values convention: 0xXXYYYYYY
175 * - YYYYYY : Position in the register
176 * - XX : Register index
177 * - 00: CFGR1 register in SYSCFG
178 * - 01: CFGR3 register in SYSCFG
181 #define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
182 0: No remap (DAC trigger is TIM8_TRGO)
183 1: Remap (DAC trigger is TIM3_TRGO) */
184 #define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap
186 1: Remap (TIM1_TRG3 = TIM17_OC) */
187 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
188 #if !defined(HAL_REMAP_CFGR3_MASK)
189 #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
191 #define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
192 0: Remap (DAC trigger is TIM15_TRGO)
193 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
194 #define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
196 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
197 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
198 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
199 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
200 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
202 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
203 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
204 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
209 #if defined (STM32F303xE) || defined (STM32F398xx)
210 /** @defgroup HAL_ADC_Trigger_Remapping ADC Trigger Remapping
213 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
214 0: No remap (TIM1_CC3)
215 1: Remap (TIM20_TRGO) */
216 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
217 0: No remap (TIM2_CC2)
218 1: Remap (TIM20_TRGO2) */
219 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
220 0: No remap (TIM4_CC4)
221 1: Remap (TIM20_CC1) */
222 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
223 0: No remap (TIM6_TRGO)
224 1: Remap (TIM20_CC2) */
225 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
226 0: No remap (TIM3_CC4)
227 1: Remap (TIM20_CC3) */
228 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
229 0: No remap (TIM2_CC1)
230 1: Remap (TIM20_TRGO) */
231 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
232 0: No remap (EXTI line 15)
233 1: Remap (TIM20_TRGO2) */
234 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
235 0: No remap (TIM3_CC1)
236 1: Remap (TIM20_CC4) */
237 #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
238 0: No remap (EXTI line 2)
239 1: Remap (TIM20_TRGO) */
240 #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
241 0: No remap (TIM4_CC1)
242 1: Remap (TIM20_TRGO2) */
243 #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
244 0: No remap (TIM2_CC1)
245 1: Remap (TIM20_CC1) */
246 #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
247 0: No remap (TIM4_CC3)
248 1: Remap (TIM20_TRGO) */
249 #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
250 0: No remap (TIM1_CC3)
251 1: Remap (TIM20_TRGO2) */
252 #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
253 0: No remap (TIM7_TRGO)
254 1: Remap (TIM20_CC2) */
256 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
257 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
258 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
259 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
260 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
261 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
262 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
263 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
264 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
265 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
266 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
267 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
268 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
269 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
273 #endif /* STM32F303xE || STM32F398xx */
275 /** @defgroup HAL_FastModePlus_I2C I2C Fast Mode Plus
278 #if defined(SYSCFG_CFGR1_I2C1_FMP)
279 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< I2C1 fast mode Plus driving capability activation
280 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
281 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
282 #endif /* SYSCFG_CFGR1_I2C1_FMP */
284 #if defined(SYSCFG_CFGR1_I2C2_FMP)
285 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< I2C2 fast mode Plus driving capability activation
286 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
287 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
288 #endif /* SYSCFG_CFGR1_I2C2_FMP */
290 #if defined(SYSCFG_CFGR1_I2C3_FMP)
291 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< I2C3 fast mode Plus driving capability activation
292 0: FM+ mode is not enabled on I2C3 pins selected through AF selection bits
293 1: FM+ mode is enabled on I2C3 pins selected through AF selection bits */
294 #endif /* SYSCFG_CFGR1_I2C3_FMP */
296 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
297 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
298 0: PB6 pin operates in standard mode
299 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
300 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
302 #if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
303 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
304 0: PB7 pin operates in standard mode
305 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
306 #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
308 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
309 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
310 0: PB8 pin operates in standard mode
311 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
312 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
314 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
315 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
316 0: PB9 pin operates in standard mode
317 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
318 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
320 #if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP)
321 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
322 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
323 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C3) == HAL_SYSCFG_FASTMODEPLUS_I2C3) || \
324 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
325 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
326 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
327 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
328 #elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP)
329 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
330 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
331 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
332 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
333 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
334 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
335 #elif defined(SYSCFG_CFGR1_I2C1_FMP)
336 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
337 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
338 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
339 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
340 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
341 #endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */
346 #if defined(SYSCFG_RCR_PAGE0)
347 /* CCM-SRAM defined */
348 /** @defgroup HAL_Page_Write_Protection CCM RAM page write protection
351 #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
352 #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
353 #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
354 #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
355 #if defined(SYSCFG_RCR_PAGE4)
356 /* More than 4KB CCM-SRAM defined */
357 #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
358 #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
359 #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
360 #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
361 #endif /* SYSCFG_RCR_PAGE4 */
362 #if defined(SYSCFG_RCR_PAGE8)
363 #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
364 #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
365 #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
366 #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
367 #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
368 #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
369 #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
370 #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
371 #endif /* SYSCFG_RCR_PAGE8 */
373 #if defined(SYSCFG_RCR_PAGE8)
374 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0xFFFF))
375 #elif defined(SYSCFG_RCR_PAGE4)
376 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x00FF))
378 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x000F))
379 #endif /* SYSCFG_RCR_PAGE8 */
383 #endif /* SYSCFG_RCR_PAGE0 */
385 /** @defgroup HAL_SYSCFG_Interrupts SYSCFG Interrupts
388 #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
389 #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
390 #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
391 #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
392 #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
393 #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
395 #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
396 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
397 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
398 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
399 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
400 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
410 /* Exported macro ------------------------------------------------------------*/
411 /** @defgroup HAL_Exported_Macros HAL Exported Macros
415 /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
418 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
419 #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
420 #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
421 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
423 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
424 #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
425 #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
426 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
428 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
429 #define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
430 #define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
431 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
433 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
434 #define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
435 #define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
436 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
438 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
439 #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
440 #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
441 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
443 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
444 #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
445 #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
446 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
448 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
449 #define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
450 #define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
451 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
453 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
454 #define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
455 #define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
456 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
458 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
459 #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
460 #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
461 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
463 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
464 #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
465 #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
466 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
468 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
469 #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
470 #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
471 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
473 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
474 #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
475 #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
476 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
478 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
479 #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
480 #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
481 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
483 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
484 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
485 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
486 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
488 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
489 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
490 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
491 #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
493 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
494 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
495 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
496 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
498 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
499 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
500 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
501 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
506 /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
509 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
510 #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
511 #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
512 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
514 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
515 #define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
516 #define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
517 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
519 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
520 #define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
521 #define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
522 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
524 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
525 #define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
526 #define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
527 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
529 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
530 #define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
531 #define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
532 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
534 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
535 #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
536 #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
537 #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
539 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
540 #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
541 #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
542 #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
547 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
550 #if defined(SYSCFG_CFGR1_MEM_MODE)
551 /** @brief Main Flash memory mapped at 0x00000000
553 #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
554 #endif /* SYSCFG_CFGR1_MEM_MODE */
556 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
557 /** @brief System Flash memory mapped at 0x00000000
559 #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
560 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
562 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
564 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
565 /** @brief Embedded SRAM mapped at 0x00000000
567 #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
568 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
570 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
572 #if defined(SYSCFG_CFGR1_MEM_MODE_2)
573 #define __HAL_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
574 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
576 #endif /* SYSCFG_CFGR1_MEM_MODE_2 */
581 /** @defgroup Encoder_Mode Encoder Mode
584 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
585 /** @brief No Encoder mode
587 #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
588 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
590 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
591 /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
593 #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
594 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
596 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
598 #if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
599 /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
601 #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
602 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
604 #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
606 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
607 /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
609 #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
610 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
612 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
617 /** @defgroup DMA_Remap_Enable DMA Remap Enable
620 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
621 /** @brief DMA remapping enable/disable macros
622 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
624 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
625 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
626 (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
627 (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
629 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
630 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
631 (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
632 (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
634 #elif defined(SYSCFG_CFGR1_DMA_RMP)
635 /** @brief DMA remapping enable/disable macros
636 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
638 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
639 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
641 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
642 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
644 #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
649 /** @defgroup I2C2_Fast_Mode_Plus_Enable I2C2 Fast Mode Plus Enable
652 /** @brief Fast mode Plus driving capability enable/disable macros
653 * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
655 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
656 SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
659 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
660 SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
666 /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
669 /** @brief SYSCFG interrupt enable/disable macros
670 * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
672 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
673 SYSCFG->CFGR1 |= (__INTERRUPT__); \
676 #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
677 SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
683 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
684 /** @defgroup USB_Interrupt_Remap USB Interrupt Remap
687 /** @brief USB interrupt remapping enable/disable macros
689 #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
690 #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
694 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
696 #if defined(SYSCFG_CFGR1_VBAT)
697 /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
700 /** @brief SYSCFG interrupt enable/disable macros
702 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
703 #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
707 #endif /* SYSCFG_CFGR1_VBAT */
709 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
710 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
713 /** @brief SYSCFG Break Lockup lock
714 * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
715 * @note The selected configuration is locked and can be unlocked by system reset
717 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
718 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
723 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
725 #if defined(SYSCFG_CFGR2_PVD_LOCK)
726 /** @defgroup PVD_Lock_Enable PVD Lock
729 /** @brief SYSCFG Break PVD lock
730 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
731 * @note The selected configuration is locked and can be unlocked by system reset
733 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
734 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
739 #endif /* SYSCFG_CFGR2_PVD_LOCK */
741 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
742 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
745 /** @brief SYSCFG Break SRAM PARITY lock
746 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
747 * @note The selected configuration is locked and can be unlocked by system reset
749 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
750 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
755 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
757 /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
760 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
761 /** @brief Trigger remapping enable/disable macros
762 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
764 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
765 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
766 (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
767 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
769 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
770 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
771 (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
772 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
775 /** @brief Trigger remapping enable/disable macros
776 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
778 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
779 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
781 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
782 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
784 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
789 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
790 /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
793 /** @brief ADC trigger remapping enable/disable macros
794 * @param __ADCTRIGGER_REMAP__: This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
796 #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
797 (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
799 #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
800 (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
805 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
807 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
808 /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
812 * @brief Parity check on RAM disable macro
813 * @note Disabling the parity check on RAM locks the configuration bit.
814 * To re-enable the parity check on RAM perform a system reset.
816 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001)
820 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
822 #if defined(SYSCFG_RCR_PAGE0)
823 /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
826 /** @brief CCM RAM page write protection enable macro
827 * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
828 * @note write protection can only be disabled by a system reset
830 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
831 SYSCFG->RCR |= (__PAGE_WP__); \
836 #endif /* SYSCFG_RCR_PAGE0 */
841 /* Exported functions --------------------------------------------------------*/
842 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
846 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
847 * @brief Initialization and de-initialization functions
850 /* Initialization and de-initialization functions ******************************/
851 HAL_StatusTypeDef HAL_Init(void);
852 HAL_StatusTypeDef HAL_DeInit(void);
853 void HAL_MspInit(void);
854 void HAL_MspDeInit(void);
855 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
860 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
861 * @brief HAL Control functions
864 /* Peripheral Control functions ************************************************/
865 void HAL_IncTick(void);
866 void HAL_Delay(__IO uint32_t Delay);
867 void HAL_SuspendTick(void);
868 void HAL_ResumeTick(void);
869 uint32_t HAL_GetTick(void);
870 uint32_t HAL_GetHalVersion(void);
871 uint32_t HAL_GetREVID(void);
872 uint32_t HAL_GetDEVID(void);
873 void HAL_EnableDBGSleepMode(void);
874 void HAL_DisableDBGSleepMode(void);
875 void HAL_EnableDBGStopMode(void);
876 void HAL_DisableDBGStopMode(void);
877 void HAL_EnableDBGStandbyMode(void);
878 void HAL_DisableDBGStandbyMode(void);
899 #endif /* __STM32F3xx_HAL_H */
901 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/