2 ******************************************************************************
3 * @file stm32f3xx_hal_rcc.h
4 * @author MCD Application Team
7 * @brief Header file of RCC HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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14 * are permitted provided that the following conditions are met:
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21 * may be used to endorse or promote products derived from this software
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_HAL_RCC_H
40 #define __STM32F3xx_HAL_RCC_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f3xx_hal_def.h"
49 /** @addtogroup STM32F3xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup RCC_Exported_Types RCC Exported Types
64 * @brief RCC System, AHB and APB busses clock configuration structure definition
68 uint32_t ClockType; /*!< The clock to be configured.
69 This parameter can be a value of @ref RCC_System_Clock_Type */
71 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
72 This parameter can be a value of @ref RCC_System_Clock_Source */
74 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
75 This parameter can be a value of @ref RCC_AHB_Clock_Source */
77 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
78 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
80 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
81 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
89 /* Exported constants --------------------------------------------------------*/
90 /** @defgroup RCC_Exported_Constants RCC Exported Constants
94 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
95 * @brief RCC registers bit address in the alias region
98 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
99 /* --- CR Register ---*/
100 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
101 /* Alias word address of HSION bit */
102 #define HSION_BitNumber 0
103 #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
104 /* Alias word address of HSEON bit */
105 #define HSEON_BitNumber 16
106 #define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4))
107 /* Alias word address of CSSON bit */
108 #define CSSON_BitNumber 19
109 #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
110 /* Alias word address of PLLON bit */
111 #define PLLON_BitNumber 24
112 #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
114 /* --- CFGR Register ---*/
115 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
116 /* Alias word address of PLLSRC bit */
117 #define PLLSRC_BitNumber 16
118 #define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4))
120 /* --- CIR Register ---*/
121 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
123 /* --- BDCR Register ---*/
124 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
125 /* Alias word address of LSEON bit */
126 #define LSEON_BitNumber 0
127 #define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4))
128 /* Alias word address of RTCEN bit */
129 #define RTCEN_BitNumber 15
130 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
131 /* Alias word address of BDRST bit */
132 #define BDRST_BitNumber 16
133 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
135 /* --- CSR Register ---*/
136 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
137 /* Alias word address of LSION bit */
138 #define LSION_BitNumber 0
139 #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
140 /* Alias word address of RMVF bit */
141 #define RMVF_BitNumber 24
142 #define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4))
144 /* CR register byte 2 (Bits[23:16]) base address */
145 #define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
147 /* CIR register byte 1 (Bits[15:8]) base address */
148 #define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
150 /* CIR register byte 2 (Bits[23:16]) base address */
151 #define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
153 /* CSR register byte 1 (Bits[15:8]) base address */
154 #define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
156 /* BDCR register byte 0 (Bits[7:0] base address */
157 #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
163 /** @defgroup RCC_Timeout RCC Timeout
166 /* LSE state change timeout */
167 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
169 /* Disable Backup domain write protection state change timeout */
170 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
175 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
178 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
179 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
180 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
181 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
182 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
184 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
185 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
186 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
187 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
188 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
193 /** @defgroup RCC_HSE_Config RCC HSE Config
196 #define RCC_HSE_OFF ((uint32_t)0x00000000)
197 #define RCC_HSE_ON ((uint32_t)0x00000001)
198 #define RCC_HSE_BYPASS ((uint32_t)0x00000005)
200 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
201 ((HSE) == RCC_HSE_BYPASS))
206 /** @defgroup RCC_LSE_Config RCC_LSE_Config
209 #define RCC_LSE_OFF ((uint32_t)0x00000000)
210 #define RCC_LSE_ON ((uint32_t)0x00000001)
211 #define RCC_LSE_BYPASS ((uint32_t)0x00000005)
213 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
214 ((LSE) == RCC_LSE_BYPASS))
219 /** @defgroup RCC_HSI_Config RCC HSI Config
222 #define RCC_HSI_OFF ((uint32_t)0x00000000)
223 #define RCC_HSI_ON ((uint32_t)0x00000001)
225 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
227 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
229 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
234 /** @defgroup RCC_LSI_Config RCC LSI Config
237 #define RCC_LSI_OFF ((uint32_t)0x00000000)
238 #define RCC_LSI_ON ((uint32_t)0x00000001)
240 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
245 /** @defgroup RCC_PLL_Config RCC PLL Config
248 #define RCC_PLL_NONE ((uint32_t)0x00000000)
249 #define RCC_PLL_OFF ((uint32_t)0x00000001)
250 #define RCC_PLL_ON ((uint32_t)0x00000002)
252 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
257 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
260 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
261 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
262 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
263 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
264 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
265 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
266 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
267 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
268 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
269 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
270 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
271 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
272 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
273 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
274 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
276 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
277 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
278 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
279 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
280 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
281 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
282 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
283 ((MUL) == RCC_PLL_MUL16))
288 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
291 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
292 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
293 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
294 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
296 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
297 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
298 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
299 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
304 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
307 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
308 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
309 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
311 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
312 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
313 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
318 /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
321 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
322 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
323 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
325 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
326 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
327 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)))
332 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
335 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
336 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
337 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
338 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
339 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
340 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
341 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
342 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
343 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
345 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
346 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
347 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
348 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
349 ((DIV) == RCC_SYSCLK_DIV512))
354 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
357 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
358 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
359 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
360 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
361 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
363 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
364 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
365 ((DIV) == RCC_HCLK_DIV16))
370 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
373 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
374 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
375 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
376 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
378 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
379 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
380 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
381 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
386 /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
389 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
390 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
391 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
392 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
394 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
395 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
396 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
397 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
402 /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
405 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
406 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
407 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
408 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
410 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
411 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
412 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
413 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
418 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
421 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
422 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
424 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
425 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
430 /** @defgroup RCC_MCOx_Index RCC MCOx Index
433 #define RCC_MCO ((uint32_t)0x00000000)
435 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
440 /** @defgroup RCC_Interrupt RCC Interrupt
443 #define RCC_IT_LSIRDY ((uint32_t)0x00000001)
444 #define RCC_IT_LSERDY ((uint32_t)0x00000002)
445 #define RCC_IT_HSIRDY ((uint32_t)0x00000004)
446 #define RCC_IT_HSERDY ((uint32_t)0x00000008)
447 #define RCC_IT_PLLRDY ((uint32_t)0x00000010)
448 #define RCC_IT_CSS ((uint32_t)0x00000080)
453 /** @defgroup RCC_Flag RCC Flag
454 * Elements values convention: 0XXYYYYYb
455 * - YYYYY : Flag position in the register
456 * - XX : Register index
458 * - 10: BDCR register
462 #define CR_REG_INDEX 1U
463 #define BDCR_REG_INDEX 2U
464 #define CSR_REG_INDEX 3U
466 /* Flags in the CR register */
467 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY))))
468 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSERDY))))
469 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY))))
471 /* Flags in the BDCR register */
472 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY))))
474 /* Flags in the CSR register */
475 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY))))
476 #define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_RMVF))))
477 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF))))
478 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF))))
479 #define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF))))
480 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF))))
481 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF))))
482 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF))))
483 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF))))
491 /* Exported macro ------------------------------------------------------------*/
493 /** @defgroup RCC_Exported_Macros RCC Exported Macros
497 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
498 * @brief Enable or disable the AHB peripheral clock.
499 * @note After reset, the peripheral clock (used for registers read/write access)
500 * is disabled and the application software has to enable this clock before
504 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
505 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
506 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
507 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
508 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
509 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
510 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
511 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
512 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
513 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
515 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
516 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
517 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
518 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
519 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
520 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
521 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
522 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
523 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
524 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
529 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
530 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
531 * @note After reset, the peripheral clock (used for registers read/write access)
532 * is disabled and the application software has to enable this clock before
536 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
537 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
538 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
539 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
540 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
541 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
542 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
543 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC1EN))
545 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
546 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
547 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
548 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
549 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
550 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
551 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
552 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
557 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
558 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
559 * @note After reset, the peripheral clock (used for registers read/write access)
560 * is disabled and the application software has to enable this clock before
564 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
565 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
566 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
567 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
568 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
570 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
571 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
572 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
573 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
574 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
579 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
580 * @brief Force or release AHB peripheral reset.
583 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
584 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
585 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
586 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
587 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
588 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
589 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
591 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
592 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
593 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
594 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
595 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
596 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
597 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
602 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
603 * @brief Force or release APB1 peripheral reset.
606 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
607 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
608 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
609 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
610 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
611 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
612 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
613 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
614 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
616 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
617 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
618 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
619 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
620 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
621 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
622 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
623 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
624 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
629 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
630 * @brief Force or release APB2 peripheral reset.
633 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
634 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
635 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
636 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
637 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
638 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
640 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
641 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
642 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
643 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
644 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
645 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
650 /** @defgroup RCC_HSI_Configuration RCC HSI Configuration
654 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
655 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
656 * It is used (enabled by hardware) as system clock source after startup
657 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
658 * of the HSE used directly or indirectly as system clock (if the Clock
659 * Security System CSS is enabled).
660 * @note HSI can not be stopped if it is used as system clock source. In this case,
661 * you have to select another source of the system clock then stop the HSI.
662 * @note After enabling the HSI, the application software should wait on HSIRDY
663 * flag to be set indicating that HSI clock is stable and can be used as
664 * system clock source.
665 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
668 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)CR_HSION_BB = ENABLE)
669 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)CR_HSION_BB = DISABLE)
672 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
673 * @note The calibration is used to compensate for the variations in voltage
674 * and temperature that influence the frequency of the internal HSI RC.
675 * @param __HSICalibrationValue__: specifies the calibration trimming value.
676 * This parameter must be a number between 0 and 0x1F.
678 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
679 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))
684 /** @defgroup RCC_LSI_Configuration RCC LSI Configuration
688 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
689 * @note After enabling the LSI, the application software should wait on
690 * LSIRDY flag to be set indicating that LSI clock is stable and can
691 * be used to clock the IWDG and/or the RTC.
692 * @note LSI can not be disabled if the IWDG is running.
693 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
696 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)CSR_LSION_BB = ENABLE)
697 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)CSR_LSION_BB = DISABLE)
702 /** @defgroup RCC_HSE_Configuration RCC HSE Configuration
707 * @brief Macro to configure the External High Speed oscillator (HSE).
708 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
709 * software should wait on HSERDY flag to be set indicating that HSE clock
710 * is stable and can be used to clock the PLL and/or system clock.
711 * @note HSE state can not be changed if it is used directly or through the
712 * PLL as system clock. In this case, you have to select another source
713 * of the system clock then change the HSE state (ex. disable it).
714 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
715 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
716 * was previously enabled you have to enable it again after calling this
718 * @param __STATE__: specifies the new state of the HSE.
719 * This parameter can be one of the following values:
720 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
721 * 6 HSE oscillator clock cycles.
722 * @arg RCC_HSE_ON: turn ON the HSE oscillator
723 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
725 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)CR_BYTE2_ADDRESS = (__STATE__))
730 /** @defgroup RCC_LSE_Configuration RCC LSE Configuration
734 * @brief Macro to configure the External Low Speed oscillator (LSE).
735 * @note As the LSE is in the Backup domain and write access is denied to
736 * this domain after reset, you have to enable write access using
737 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
738 * (to be done once after reset).
739 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
740 * software should wait on LSERDY flag to be set indicating that LSE clock
741 * is stable and can be used to clock the RTC.
742 * @param __STATE__: specifies the new state of the LSE.
743 * This parameter can be one of the following values:
744 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
745 * 6 LSE oscillator clock cycles.
746 * @arg RCC_LSE_ON: turn ON the LSE oscillator
747 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
749 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
750 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
755 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
758 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
759 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
760 * This parameter can be one of the following values:
761 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
762 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
764 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
765 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
767 /** @brief Macro to get the I2C1 clock source.
768 * @retval The clock source can be one of the following values:
769 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
770 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
772 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
777 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
781 /** @brief Macro to configure the USART1 clock (USART1CLK).
782 * @param __USART1CLKSource__: specifies the USART1 clock source.
783 * This parameter can be one of the following values:
784 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
785 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
786 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
787 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
789 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
790 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
792 /** @brief Macro to get the USART1 clock source.
793 * @retval The clock source can be one of the following values:
794 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
795 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
796 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
797 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
799 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
801 /** @brief Macro to configure the USART2 clock (USART2CLK).
802 * @param __USART2CLKSource__: specifies the USART2 clock source.
803 * This parameter can be one of the following values:
804 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
805 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
806 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
807 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
809 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
810 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
812 /** @brief Macro to get the USART2 clock source.
813 * @retval The clock source can be one of the following values:
814 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
815 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
816 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
817 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
819 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
821 /** @brief Macro to configure the USART3 clock (USART3CLK).
822 * @param __USART3CLKSource__: specifies the USART3 clock source.
823 * This parameter can be one of the following values:
824 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
825 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
826 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
827 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
829 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
830 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
832 /** @brief Macro to get the USART3 clock source.
833 * @retval The clock source can be one of the following values:
834 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
835 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
836 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
837 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
839 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
844 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
847 /** @brief Macros to enable or disable the the RTC clock.
848 * @note These macros must be used only after the RTC clock source was selected.
850 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = ENABLE)
851 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = DISABLE)
853 /** @brief Macro to configure the RTC clock (RTCCLK).
854 * @note As the RTC clock configuration bits are in the Backup domain and write
855 * access is denied to this domain after reset, you have to enable write
856 * access using the Power Backup Access macro before to configure
857 * the RTC clock source (to be done once after reset).
858 * @note Once the RTC clock is configured it can't be changed unless the
859 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
860 * a Power On Reset (POR).
861 * @param __RTCCLKSource__: specifies the RTC clock source.
862 * This parameter can be one of the following values:
863 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
864 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
865 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
866 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
868 * @note If the LSE is used as RTC clock source, the RTC continues to
869 * work in STOP and STANDBY modes, and can be used as wakeup source.
870 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
871 * the RTC cannot be used in STOP and STANDBY modes.
872 * @note The system must always be configured so as to get a PCLK frequency greater than or
873 * equal to the RTCCLK frequency for a proper operation of the RTC.
875 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
876 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
878 /** @brief Macro to get the RTC clock source.
879 * @retval The clock source can be one of the following values:
880 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
881 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
882 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
883 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
885 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
890 /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
894 /** @brief Macro to force or release the Backup domain reset.
895 * @note These macros reset the RTC peripheral (including the backup registers)
896 * and the RTC clock source selection in RCC_CSR register.
897 * @note The BKPSRAM is not affected by this reset.
899 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)BDCR_BDRST_BB = ENABLE)
900 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)BDCR_BDRST_BB = DISABLE)
905 /** @defgroup RCC_PLL_Configuration RCC PLL Configuration
909 /** @brief Macro to enable or disable the PLL.
910 * @note After enabling the PLL, the application software should wait on
911 * PLLRDY flag to be set indicating that PLL clock is stable and can
912 * be used as system clock source.
913 * @note The PLL can not be disabled if it is used as system clock source
914 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
916 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)CR_PLLON_BB = ENABLE)
917 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)CR_PLLON_BB = DISABLE)
922 /** @defgroup RCC_Get_Clock_source RCC Get Clock source
926 /** @brief Macro to get the clock source used as system clock.
927 * @retval The clock source used as system clock.
928 * The returned value can be one of the following value:
929 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
930 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
931 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
933 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
935 /** @brief Macro to get the oscillator used as PLL clock source.
936 * @retval The oscillator used as PLL clock source. The returned value can be one
938 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
939 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
941 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
946 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
947 * @brief macros to manage the specified RCC Flags and interrupts.
951 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
952 * the selected interrupts.).
953 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
954 * This parameter can be any combination of the following values:
955 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
956 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
957 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
958 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
959 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
961 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
963 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
964 * the selected interrupts.).
965 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
966 * This parameter can be any combination of the following values:
967 * @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable
968 * @arg RCC_IT_LSERDYIE: LSE ready interrupt enable
969 * @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable
970 * @arg RCC_IT_HSERDYIE: HSE ready interrupt enable
971 * @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable
973 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
975 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
976 * bits to clear the selected interrupt pending bits.
977 * @param __IT__: specifies the interrupt pending bit to clear.
978 * This parameter can be any combination of the following values:
979 * @arg RCC_IT_LSIRDYC: LSI ready interrupt clear
980 * @arg RCC_IT_LSERDYC: LSE ready interrupt clear
981 * @arg RCC_IT_HSIRDYC: HSI ready interrupt clear
982 * @arg RCC_IT_HSERDYC: HSE ready interrupt clear
983 * @arg RCC_IT_PLLRDYC: PLL ready interrupt clear
984 * @arg RCC_IT_CSSC: Clock Security System interrupt clear
986 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)CIR_BYTE2_ADDRESS = (__IT__))
988 /** @brief Check the RCC's interrupt has occurred or not.
989 * @param __IT__: specifies the RCC interrupt source to check.
990 * This parameter can be one of the following values:
991 * @arg RCC_IT_LSIRDYF: LSI ready interrupt flag
992 * @arg RCC_IT_LSERDYF: LSE ready interrupt flag
993 * @arg RCC_IT_HSIRDYF: HSI ready interrupt flag
994 * @arg RCC_IT_HSERDYF: HSE ready interrupt flag
995 * @arg RCC_IT_PLLRDYF: PLL ready interrupt flag
996 * @arg RCC_IT_CSSF: Clock Security System interrupt flag
997 * @retval The new state of __IT__ (TRUE or FALSE).
999 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
1001 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1002 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1004 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)CSR_RMVF_BB = ENABLE)
1006 /** @brief Check RCC flag is set or not.
1007 * @param __FLAG__: specifies the flag to check.
1008 * This parameter can be one of the following values:
1009 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
1010 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
1011 * @arg RCC_FLAG_PLLRDY: PLL clock ready
1012 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
1013 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
1014 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
1015 * @arg RCC_FLAG_PINRST: Pin reset
1016 * @arg RCC_FLAG_PORRST: POR/PDR reset
1017 * @arg RCC_FLAG_SFTRST: Software reset
1018 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
1019 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
1020 * @arg RCC_FLAG_LPWRRST: Low Power reset
1021 * @retval The new state of __FLAG__ (TRUE or FALSE).
1023 #define RCC_FLAG_MASK ((uint32_t)0x0000001F)
1024 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
1025 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
1026 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
1037 /* Include RCC HAL Extended module */
1038 #include "stm32f3xx_hal_rcc_ex.h"
1040 /* Exported functions --------------------------------------------------------*/
1042 /** @addtogroup RCC_Exported_Functions
1046 /** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
1050 /* Initialization and de-initialization functions ***************************/
1051 void HAL_RCC_DeInit(void);
1052 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1053 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1059 /** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
1063 /* Peripheral Control functions *********************************************/
1064 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1065 void HAL_RCC_EnableCSS(void);
1066 void HAL_RCC_DisableCSS(void);
1067 uint32_t HAL_RCC_GetSysClockFreq(void);
1068 uint32_t HAL_RCC_GetHCLKFreq(void);
1069 uint32_t HAL_RCC_GetPCLK1Freq(void);
1070 uint32_t HAL_RCC_GetPCLK2Freq(void);
1071 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1072 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1074 /* CSS NMI IRQ handler */
1075 void HAL_RCC_NMI_IRQHandler(void);
1077 /* User Callbacks in non blocking mode (IT mode) */
1078 void HAL_RCC_CCSCallback(void);
1100 #endif /* __STM32F3xx_HAL_RCC_H */
1102 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/