2 ******************************************************************************
3 * @file stm32f3xx_hal_sdadc.h
4 * @author MCD Application Team
7 * @brief This file contains all the functions prototypes for the SDADC
9 ******************************************************************************
12 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 ******************************************************************************
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef __STM32F3xx_SDADC_H
41 #define __STM32F3xx_SDADC_H
47 #if defined(STM32F373xC) || defined(STM32F378xx)
49 /* Includes ------------------------------------------------------------------*/
50 #include "stm32f3xx_hal_def.h"
52 /** @addtogroup STM32F3xx_HAL_Driver
60 /* Exported types ------------------------------------------------------------*/
61 /** @defgroup SDADC_Exported_Types SDADC Exported Types
67 * @brief HAL SDADC States definition
71 HAL_SDADC_STATE_RESET = 0x00, /*!< SDADC not initialized */
72 HAL_SDADC_STATE_READY = 0x01, /*!< SDADC initialized and ready for use */
73 HAL_SDADC_STATE_CALIB = 0x02, /*!< SDADC calibration in progress */
74 HAL_SDADC_STATE_REG = 0x03, /*!< SDADC regular conversion in progress */
75 HAL_SDADC_STATE_INJ = 0x04, /*!< SDADC injected conversion in progress */
76 HAL_SDADC_STATE_REG_INJ = 0x05, /*!< SDADC regular and injected conversions in progress */
77 HAL_SDADC_STATE_ERROR = 0xFF, /*!< SDADC state error */
78 }HAL_SDADC_StateTypeDef;
81 * @brief SDADC Init Structure definition
85 uint32_t IdleLowPowerMode; /*!< Specifies if SDADC can enter in power down or standby when idle.
86 This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
87 uint32_t FastConversionMode; /*!< Specifies if Fast conversion mode is enabled or not.
88 This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
89 uint32_t SlowClockMode; /*!< Specifies if slow clock mode is enabled or not.
90 This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
91 uint32_t ReferenceVoltage; /*!< Specifies the reference voltage.
92 This parameter can be a value of @ref SDADC_Reference_Voltage */
96 * @brief SDADC handle Structure definition
100 SDADC_TypeDef *Instance; /*!< SDADC registers base address */
101 SDADC_InitTypeDef Init; /*!< SDADC init parameters */
102 DMA_HandleTypeDef *hdma; /*!< SDADC DMA Handle parameters */
103 uint32_t RegularContMode; /*!< Regular conversion continuous mode */
104 uint32_t InjectedContMode; /*!< Injected conversion continuous mode */
105 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
106 uint32_t InjConvRemaining; /*!< Injected conversion remaining */
107 uint32_t RegularTrigger; /*!< Current trigger used for regular conversion */
108 uint32_t InjectedTrigger; /*!< Current trigger used for injected conversion */
109 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
110 uint32_t RegularMultimode; /*!< current type of regular multimode */
111 uint32_t InjectedMultimode; /*!< Current type of injected multimode */
112 HAL_SDADC_StateTypeDef State; /*!< SDADC state */
113 uint32_t ErrorCode; /*!< SDADC Error code */
114 }SDADC_HandleTypeDef;
117 * @brief SDADC Configuration Register Parameter Structure
121 uint32_t InputMode; /*!< Specifies the input mode (single ended, differential...)
122 This parameter can be any value of @ref SDADC_InputMode */
123 uint32_t Gain; /*!< Specifies the gain setting.
124 This parameter can be any value of @ref SDADC_Gain */
125 uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2).
126 This parameter can be any value of @ref SDADC_CommonMode */
127 uint32_t Offset; /*!< Specifies the 12-bit offset value.
128 This parameter can be any value lower or equal to 0x00000FFF */
129 }SDADC_ConfParamTypeDef;
135 /* Exported constants --------------------------------------------------------*/
137 /** @defgroup SDADC_Exported_Constants SDADC Exported Constants
141 /** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
144 #define SDADC_LOWPOWER_NONE ((uint32_t)0x00000000)
145 #define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
146 #define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
147 #define IS_SDADC_LOWPOWER_MODE(LOWPOWER) (((LOWPOWER) == SDADC_LOWPOWER_NONE) || \
148 ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
149 ((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
154 /** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
157 #define SDADC_FAST_CONV_DISABLE ((uint32_t)0x00000000)
158 #define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
159 #define IS_SDADC_FAST_CONV_MODE(FAST) (((FAST) == SDADC_FAST_CONV_DISABLE) || \
160 ((FAST) == SDADC_FAST_CONV_ENABLE))
165 /** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
168 #define SDADC_SLOW_CLOCK_DISABLE ((uint32_t)0x00000000)
169 #define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
170 #define IS_SDADC_SLOW_CLOCK_MODE(MODE) (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
171 ((MODE) == SDADC_SLOW_CLOCK_ENABLE))
176 /** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
179 #define SDADC_VREF_EXT ((uint32_t)0x00000000) /*!< The reference voltage is forced externally using VREF pin */
180 #define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */
181 #define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */
182 #define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */
183 #define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_EXT) || \
184 ((VREF) == SDADC_VREF_VREFINT1) || \
185 ((VREF) == SDADC_VREF_VREFINT2) || \
186 ((VREF) == SDADC_VREF_VDDA))
191 /** @defgroup SDADC_ConfIndex SDADC Configuration Index
195 #define SDADC_CONF_INDEX_0 ((uint32_t)0x00000000) /*!< Configuration 0 Register selected */
196 #define SDADC_CONF_INDEX_1 ((uint32_t)0x00000001) /*!< Configuration 1 Register selected */
197 #define SDADC_CONF_INDEX_2 ((uint32_t)0x00000002) /*!< Configuration 2 Register selected */
199 #define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0) || \
200 ((CONF) == SDADC_CONF_INDEX_1) || \
201 ((CONF) == SDADC_CONF_INDEX_2))
206 /** @defgroup SDADC_InputMode SDADC Input Mode
209 #define SDADC_INPUT_MODE_DIFF ((uint32_t)0x00000000) /*!< Conversions are executed in differential mode */
210 #define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */
211 #define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */
213 #define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF) || \
214 ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
215 ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
220 /** @defgroup SDADC_Gain SDADC Gain
223 #define SDADC_GAIN_1 ((uint32_t)0x00000000) /*!< Gain equal to 1 */
224 #define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2 */
225 #define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4 */
226 #define SDADC_GAIN_8 ((uint32_t)0x00300000) /*!< Gain equal to 8 */
227 #define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16 */
228 #define SDADC_GAIN_32 ((uint32_t)0x00500000) /*!< Gain equal to 32 */
229 #define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1/2 */
230 #define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1) || \
231 ((GAIN) == SDADC_GAIN_2) || \
232 ((GAIN) == SDADC_GAIN_4) || \
233 ((GAIN) == SDADC_GAIN_8) || \
234 ((GAIN) == SDADC_GAIN_16) || \
235 ((GAIN) == SDADC_GAIN_32) || \
236 ((GAIN) == SDADC_GAIN_1_2))
241 /** @defgroup SDADC_CommonMode SDADC Common Mode
244 #define SDADC_COMMON_MODE_VSSA ((uint32_t)0x00000000) /*!< Select SDADC VSSA as common mode */
245 #define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
246 #define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
247 #define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA) || \
248 ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
249 ((MODE) == SDADC_COMMON_MODE_VDDA))
254 /** @defgroup SDADC_Offset SDADC Offset
257 #define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFF)
262 /** @defgroup SDADC_Channel_Selection SDADC Channel Selection
266 /* SDADC Channels ------------------------------------------------------------*/
267 /* The SDADC channels are defined as follows:
268 - in 16-bit LSB the channel mask is set
269 - in 16-bit MSB the channel number is set
270 e.g. for channel 5 definition:
271 - the channel mask is 0x00000020 (bit 5 is set)
272 - the channel number 5 is 0x00050000
273 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
274 #define SDADC_CHANNEL_0 ((uint32_t)0x00000001)
275 #define SDADC_CHANNEL_1 ((uint32_t)0x00010002)
276 #define SDADC_CHANNEL_2 ((uint32_t)0x00020004)
277 #define SDADC_CHANNEL_3 ((uint32_t)0x00030008)
278 #define SDADC_CHANNEL_4 ((uint32_t)0x00040010)
279 #define SDADC_CHANNEL_5 ((uint32_t)0x00050020)
280 #define SDADC_CHANNEL_6 ((uint32_t)0x00060040)
281 #define SDADC_CHANNEL_7 ((uint32_t)0x00070080)
282 #define SDADC_CHANNEL_8 ((uint32_t)0x00080100)
284 /* Just one channel of the 9 channels can be selected for regular conversion */
285 #define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \
286 ((CHANNEL) == SDADC_CHANNEL_1) || \
287 ((CHANNEL) == SDADC_CHANNEL_2) || \
288 ((CHANNEL) == SDADC_CHANNEL_3) || \
289 ((CHANNEL) == SDADC_CHANNEL_4) || \
290 ((CHANNEL) == SDADC_CHANNEL_5) || \
291 ((CHANNEL) == SDADC_CHANNEL_6) || \
292 ((CHANNEL) == SDADC_CHANNEL_7) || \
293 ((CHANNEL) == SDADC_CHANNEL_8))
295 /* Any or all of the 9 channels can be selected for injected conversion */
296 #define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F01FF))
302 /** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
305 #define SDADC_CALIBRATION_SEQ_1 ((uint32_t)0x00000000) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
306 #define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
307 #define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
309 #define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \
310 ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2) || \
311 ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
316 /** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
319 #define SDADC_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */
320 #define SDADC_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */
322 #define IS_SDADC_CONTINUOUS_MODE(MODE) (((MODE) == SDADC_CONTINUOUS_CONV_OFF) || \
323 ((MODE) == SDADC_CONTINUOUS_CONV_ON))
328 /** @defgroup SDADC_Trigger SDADC Trigger
331 #define SDADC_SOFTWARE_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */
332 #define SDADC_SYNCHRONOUS_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
333 #define SDADC_EXTERNAL_TRIGGER ((uint32_t)0x00000002) /*!< External trigger */
335 #define IS_SDADC_REGULAR_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
336 ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
338 #define IS_SDADC_INJECTED_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
339 ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER) || \
340 ((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
345 /** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
348 #define SDADC_EXT_TRIG_TIM13_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC1 */
349 #define SDADC_EXT_TRIG_TIM14_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC1 */
350 #define SDADC_EXT_TRIG_TIM16_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC3 */
351 #define SDADC_EXT_TRIG_TIM17_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC2 */
352 #define SDADC_EXT_TRIG_TIM12_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC2 */
353 #define SDADC_EXT_TRIG_TIM12_CC2 ((uint32_t)0x00000100) /*!< Trigger source for SDADC3 */
354 #define SDADC_EXT_TRIG_TIM15_CC2 ((uint32_t)0x00000200) /*!< Trigger source for SDADC1 */
355 #define SDADC_EXT_TRIG_TIM2_CC3 ((uint32_t)0x00000200) /*!< Trigger source for SDADC2 */
356 #define SDADC_EXT_TRIG_TIM2_CC4 ((uint32_t)0x00000200) /*!< Trigger source for SDADC3 */
357 #define SDADC_EXT_TRIG_TIM3_CC1 ((uint32_t)0x00000300) /*!< Trigger source for SDADC1 */
358 #define SDADC_EXT_TRIG_TIM3_CC2 ((uint32_t)0x00000300) /*!< Trigger source for SDADC2 */
359 #define SDADC_EXT_TRIG_TIM3_CC3 ((uint32_t)0x00000300) /*!< Trigger source for SDADC3 */
360 #define SDADC_EXT_TRIG_TIM4_CC1 ((uint32_t)0x00000400) /*!< Trigger source for SDADC1 */
361 #define SDADC_EXT_TRIG_TIM4_CC2 ((uint32_t)0x00000400) /*!< Trigger source for SDADC2 */
362 #define SDADC_EXT_TRIG_TIM4_CC3 ((uint32_t)0x00000400) /*!< Trigger source for SDADC3 */
363 #define SDADC_EXT_TRIG_TIM19_CC2 ((uint32_t)0x00000500) /*!< Trigger source for SDADC1 */
364 #define SDADC_EXT_TRIG_TIM19_CC3 ((uint32_t)0x00000500) /*!< Trigger source for SDADC2 */
365 #define SDADC_EXT_TRIG_TIM19_CC4 ((uint32_t)0x00000500) /*!< Trigger source for SDADC3 */
366 #define SDADC_EXT_TRIG_EXTI11 ((uint32_t)0x00000700) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
367 #define SDADC_EXT_TRIG_EXTI15 ((uint32_t)0x00000600) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
369 #define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
370 ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
371 ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
372 ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
373 ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
374 ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2) || \
375 ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2) || \
376 ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3) || \
377 ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4) || \
378 ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1) || \
379 ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2) || \
380 ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
381 ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
382 ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
383 ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
384 ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
385 ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
386 ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
387 ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
388 ((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
393 /** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
396 #define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0 /*!< External rising edge */
397 #define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1 /*!< External falling edge */
398 #define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN /*!< External rising and falling edges */
400 #define IS_SDADC_EXT_TRIG_EDGE(TRIGGER) (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE) || \
401 ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE) || \
402 ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
407 /** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
410 #define SDADC_INJECTED_DELAY_NONE ((uint32_t)0x00000000) /*!< No delay on injected conversion */
411 #define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */
413 #define IS_SDADC_INJECTED_DELAY(DELAY) (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
414 ((DELAY) == SDADC_INJECTED_DELAY))
419 /** @defgroup SDADC_MultimodeType SDADC Multimode Type
422 #define SDADC_MULTIMODE_SDADC1_SDADC2 ((uint32_t)0x00000000) /*!< Get conversion values for SDADC1 and SDADC2 */
423 #define SDADC_MULTIMODE_SDADC1_SDADC3 ((uint32_t)0x00000001) /*!< Get conversion values for SDADC1 and SDADC3 */
425 #define IS_SDADC_MULTIMODE_TYPE(TYPE) (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
426 ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
431 /** @defgroup SDADC_ErrorCode SDADC Error Code
434 #define SDADC_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
435 #define SDADC_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */
436 #define SDADC_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */
437 #define SDADC_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */
446 /* Exported macros -----------------------------------------------------------*/
447 /** @defgroup SDADC_Exported_Macros SDADC Exported Macros
451 /** @brief Reset SDADC handle state
452 * @param __HANDLE__: SDADC handle.
455 #define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
462 /* Exported functions --------------------------------------------------------*/
463 /** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
467 /** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
471 /* Initialization and de-initialization functions *****************************/
472 HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
473 HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
474 void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
475 void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
481 /** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions
485 /* Peripheral Control functions ***********************************************/
486 HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
488 SDADC_ConfParamTypeDef* ConfParamStruct);
489 HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
492 HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
494 uint32_t ContinuousMode);
495 HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
497 uint32_t ContinuousMode);
498 HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
499 uint32_t InjectedExtTrigger,
500 uint32_t ExtTriggerEdge);
501 HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
502 uint32_t InjectedDelay);
503 HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
504 HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
505 HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
506 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
512 /** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions
516 /* IO operation functions *****************************************************/
517 HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
518 HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
520 HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
521 HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
522 HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
523 HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
524 HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
525 HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
527 HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
528 HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
529 HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
530 HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
531 HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
532 HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
534 HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
535 HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
536 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
537 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
539 uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
540 uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
541 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
542 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
544 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
546 HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
547 HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
548 HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
550 void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
551 void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
552 void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
553 void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
554 void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
555 void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
561 /** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
565 /* Peripheral State and Error functions ***************************************/
566 HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
567 uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
569 /* Private functions ---------------------------------------------------------*/
587 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
593 #endif /*__STM32F3xx_SDADC_H */
596 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/