2 ******************************************************************************
3 * @file stm32f3xx_hal_smbus.h
4 * @author MCD Application Team
7 * @brief Header file of SMBUS HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_HAL_SMBUS_H
40 #define __STM32F3xx_HAL_SMBUS_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f3xx_hal_def.h"
49 /** @addtogroup STM32F3xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
63 * @brief SMBUS Configuration Structure definition
67 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
68 This parameter calculated by referring to SMBUS initialization
69 section in Reference manual */
70 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
71 This parameter can be a a value of @ref SMBUS_Analog_Filter */
73 uint32_t OwnAddress1; /*!< Specifies the first device own address.
74 This parameter can be a 7-bit or 10-bit address. */
76 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
77 This parameter can be a value of @ref SMBUS_addressing_mode */
79 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
80 This parameter can be a value of @ref SMBUS_dual_addressing_mode */
82 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
83 This parameter can be a 7-bit address. */
85 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
86 This parameter can be a value of @ref SMBUS_own_address2_masks. */
88 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
89 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
91 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
92 This parameter can be a value of @ref SMBUS_nostretch_mode */
94 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
95 This parameter can be a value of @ref SMBUS_packet_error_check_mode */
97 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
98 This parameter can be a value of @ref SMBUS_peripheral_mode */
100 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
101 (Enable bits and different timeout values)
102 This parameter calculated by referring to SMBUS initialization
103 section in Reference manual */
107 * @brief HAL State structures definition
111 HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */
112 HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */
113 HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */
114 HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
115 HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
116 HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
117 HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
118 HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */
119 HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */
120 HAL_SMBUS_STATE_SLAVE_LISTEN = 0x08, /*!< Address Listen Mode is ongoing */
121 /* Aliases for inter STM32 series compatibility */
122 HAL_SMBUS_STATE_LISTEN = HAL_SMBUS_STATE_SLAVE_LISTEN
123 }HAL_SMBUS_StateTypeDef;
126 * @brief HAL SMBUS Error Code structure definition
130 HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */
131 HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */
132 HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */
133 HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */
134 HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */
135 HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */
136 HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */
137 HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */
138 HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */
140 }HAL_SMBUS_ErrorTypeDef;
143 * @brief SMBUS handle Structure definition
147 I2C_TypeDef *Instance; /*!< SMBUS registers base address */
149 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
151 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
153 uint16_t XferSize; /*!< SMBUS transfer size */
155 __IO uint16_t XferCount; /*!< SMBUS transfer counter */
157 __IO uint32_t XferOptions; /*!< SMBUS transfer options */
159 __IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */
161 HAL_LockTypeDef Lock; /*!< SMBUS locking object */
163 __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */
165 __IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */
167 }SMBUS_HandleTypeDef;
172 /* Exported constants --------------------------------------------------------*/
174 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
178 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
181 #define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
182 #define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
184 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \
185 ((FILTER) == SMBUS_ANALOGFILTER_DISABLED))
190 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
193 #define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
194 #define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
196 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
197 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
202 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
206 #define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
207 #define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
209 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \
210 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED))
215 /** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks
219 #define SMBUS_OA2_NOMASK ((uint8_t)0x00)
220 #define SMBUS_OA2_MASK01 ((uint8_t)0x01)
221 #define SMBUS_OA2_MASK02 ((uint8_t)0x02)
222 #define SMBUS_OA2_MASK03 ((uint8_t)0x03)
223 #define SMBUS_OA2_MASK04 ((uint8_t)0x04)
224 #define SMBUS_OA2_MASK05 ((uint8_t)0x05)
225 #define SMBUS_OA2_MASK06 ((uint8_t)0x06)
226 #define SMBUS_OA2_MASK07 ((uint8_t)0x07)
228 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
229 ((MASK) == SMBUS_OA2_MASK01) || \
230 ((MASK) == SMBUS_OA2_MASK02) || \
231 ((MASK) == SMBUS_OA2_MASK03) || \
232 ((MASK) == SMBUS_OA2_MASK04) || \
233 ((MASK) == SMBUS_OA2_MASK05) || \
234 ((MASK) == SMBUS_OA2_MASK06) || \
235 ((MASK) == SMBUS_OA2_MASK07))
241 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
244 #define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000)
245 #define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN
247 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \
248 ((CALL) == SMBUS_GENERALCALL_ENABLED))
253 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
256 #define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
257 #define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
259 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \
260 ((STRETCH) == SMBUS_NOSTRETCH_ENABLED))
265 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
268 #define SMBUS_PEC_DISABLED ((uint32_t)0x00000000)
269 #define SMBUS_PEC_ENABLED I2C_CR1_PECEN
271 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \
272 ((PEC) == SMBUS_PEC_ENABLED))
277 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
280 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
281 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
282 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
284 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
285 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
286 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
291 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
295 #define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
296 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
297 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
298 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
300 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
301 ((MODE) == SMBUS_AUTOEND_MODE) || \
302 ((MODE) == SMBUS_SOFTEND_MODE) || \
303 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
304 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
305 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
306 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
312 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
316 #define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
317 #define SMBUS_GENERATE_STOP I2C_CR2_STOP
318 #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
319 #define SMBUS_GENERATE_START_WRITE I2C_CR2_START
321 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
322 ((REQUEST) == SMBUS_GENERATE_START_READ) || \
323 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
324 ((REQUEST) == SMBUS_NO_STARTSTOP))
330 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
334 #define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
335 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
336 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
337 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
338 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
339 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
341 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
342 ((REQUEST) == SMBUS_NEXT_FRAME) || \
343 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
344 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
345 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
346 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
352 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
353 * @brief SMBUS Interrupt definition
354 * Elements values convention: 0xXXXXXXXX
355 * - XXXXXXXX : Interrupt control mask
358 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
359 #define SMBUS_IT_TCI I2C_CR1_TCIE
360 #define SMBUS_IT_STOPI I2C_CR1_STOPIE
361 #define SMBUS_IT_NACKI I2C_CR1_NACKIE
362 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
363 #define SMBUS_IT_RXI I2C_CR1_RXIE
364 #define SMBUS_IT_TXI I2C_CR1_TXIE
365 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
366 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
367 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
368 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
373 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
374 * @brief Flag definition
375 * Elements values convention: 0xXXXXYYYY
376 * - XXXXXXXX : Flag mask
380 #define SMBUS_FLAG_TXE I2C_ISR_TXE
381 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS
382 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE
383 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR
384 #define SMBUS_FLAG_AF I2C_ISR_NACKF
385 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF
386 #define SMBUS_FLAG_TC I2C_ISR_TC
387 #define SMBUS_FLAG_TCR I2C_ISR_TCR
388 #define SMBUS_FLAG_BERR I2C_ISR_BERR
389 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO
390 #define SMBUS_FLAG_OVR I2C_ISR_OVR
391 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR
392 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
393 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT
394 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY
395 #define SMBUS_FLAG_DIR I2C_ISR_DIR
404 /* Exported macros ------------------------------------------------------------*/
405 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
409 /** @brief Reset SMBUS handle state
410 * @param __HANDLE__: SMBUS handle.
413 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
415 /** @brief Enable or disable the specified SMBUS interrupts.
416 * @param __HANDLE__: specifies the SMBUS Handle.
417 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
418 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
419 * This parameter can be one of the following values:
420 * @arg SMBUS_IT_ERRI: Errors interrupt enable
421 * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
422 * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
423 * @arg SMBUS_IT_NACKI: NACK received interrupt enable
424 * @arg SMBUS_IT_ADDRI: Address match interrupt enable
425 * @arg SMBUS_IT_RXI: RX interrupt enable
426 * @arg SMBUS_IT_TXI: TX interrupt enable
431 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
432 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
434 /** @brief Checks if the specified SMBUS interrupt source is enabled or disabled.
435 * @param __HANDLE__: specifies the SMBUS Handle.
436 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
437 * @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
438 * This parameter can be one of the following values:
439 * @arg SMBUS_IT_ERRI: Errors interrupt enable
440 * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
441 * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
442 * @arg SMBUS_IT_NACKI: NACK received interrupt enable
443 * @arg SMBUS_IT_ADDRI: Address match interrupt enable
444 * @arg SMBUS_IT_RXI: RX interrupt enable
445 * @arg SMBUS_IT_TXI: TX interrupt enable
447 * @retval The new state of __IT__ (TRUE or FALSE).
449 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
451 /** @brief Checks whether the specified SMBUS flag is set or not.
452 * @param __HANDLE__: specifies the SMBUS Handle.
453 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
454 * @param __FLAG__: specifies the flag to check.
455 * This parameter can be one of the following values:
456 * @arg SMBUS_FLAG_TXE: Transmit data register empty
457 * @arg SMBUS_FLAG_TXIS: Transmit interrupt status
458 * @arg SMBUS_FLAG_RXNE: Receive data register not empty
459 * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
460 * @arg SMBUS_FLAG_AF: NACK received flag
461 * @arg SMBUS_FLAG_STOPF: STOP detection flag
462 * @arg SMBUS_FLAG_TC: Transfer complete (master mode)
463 * @arg SMBUS_FLAG_TCR: Transfer complete reload
464 * @arg SMBUS_FLAG_BERR: Bus error
465 * @arg SMBUS_FLAG_ARLO: Arbitration lost
466 * @arg SMBUS_FLAG_OVR: Overrun/Underrun
467 * @arg SMBUS_FLAG_PECERR: PEC error in reception
468 * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
469 * @arg SMBUS_FLAG_ALERT: SMBus alert
470 * @arg SMBUS_FLAG_BUSY: Bus busy
471 * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode)
473 * @retval The new state of __FLAG__ (TRUE or FALSE).
475 #define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
476 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
478 /** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit.
479 * @param __HANDLE__: specifies the SMBUS Handle.
480 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
481 * @param __FLAG__: specifies the flag to clear.
482 * This parameter can be any combination of the following values:
483 * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
484 * @arg SMBUS_FLAG_AF: NACK received flag
485 * @arg SMBUS_FLAG_STOPF: STOP detection flag
486 * @arg SMBUS_FLAG_BERR: Bus error
487 * @arg SMBUS_FLAG_ARLO: Arbitration lost
488 * @arg SMBUS_FLAG_OVR: Overrun/Underrun
489 * @arg SMBUS_FLAG_PECERR: PEC error in reception
490 * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
491 * @arg SMBUS_FLAG_ALERT: SMBus alert
495 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
498 #define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
499 #define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
501 #define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
502 #define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
504 #define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
505 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
507 #define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
508 #define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
509 #define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
510 #define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
511 #define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
512 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
514 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
515 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
520 /* Exported functions --------------------------------------------------------*/
521 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
525 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
529 /* Initialization and de-initialization functions **********************************/
530 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
531 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
532 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
533 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
539 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
543 /* IO operation functions *****************************************************/
544 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
547 /******* Blocking mode: Polling */
548 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
553 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
556 /******* Non-Blocking mode: Interrupt */
557 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
558 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
559 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
560 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
561 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
563 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
564 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
565 HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus);
566 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
567 /** @defgroup Aliases_Exported_Functions Aliases for Exported Functions
568 * @brief Aliases for new API and to insure inter STM32 series compatibility
571 /* Aliases for new API and to insure inter STM32 series compatibility */
572 #define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT
581 /** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
584 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
585 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
586 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
587 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
588 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
589 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
590 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
591 void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
592 void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
594 /** @addtogroup Aliases_Exported_Functions Aliases for Exported Functions
595 * @brief Aliases for new API and to insure inter STM32 series compatibility
598 /* Aliases for new API and to insure inter STM32 series compatibility */
599 #define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback
600 #define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback
605 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
615 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
619 /* Peripheral State and Errors functions **************************************************/
620 HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
621 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
643 #endif /* __STM32F3xx_HAL_SMBUS_H */
645 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/