2 ******************************************************************************
3 * @file stm32f3xx_hal_spi.h
4 * @author MCD Application Team
7 * @brief Header file of SPI HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_HAL_SPI_H
40 #define __STM32F3xx_HAL_SPI_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f3xx_hal_def.h"
49 /** @addtogroup STM32F3xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup SPI_Exported_Types SPI Exported Types
63 * @brief SPI Configuration Structure definition
67 uint32_t Mode; /*!< Specifies the SPI operating mode.
68 This parameter can be a value of @ref SPI_mode */
70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
71 This parameter can be a value of @ref SPI_Direction */
73 uint32_t DataSize; /*!< Specifies the SPI data size.
74 This parameter can be a value of @ref SPI_data_size */
76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
77 This parameter can be a value of @ref SPI_Clock_Polarity */
79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
80 This parameter can be a value of @ref SPI_Clock_Phase */
82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
83 hardware (NSS pin) or by software using the SSI bit.
84 This parameter can be a value of @ref SPI_Slave_Select_management */
86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
87 used to configure the transmit and receive SCK clock.
88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
89 @note The communication clock is derived from the master
90 clock. The slave clock does not need to be set. */
92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
96 This parameter can be a value of @ref SPI_TI_mode */
98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
99 This parameter can be a value of @ref SPI_CRC_Calculation */
101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
104 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
105 CRC Length is only used with Data8 and Data16, not other data size
106 This parameter must 0 or 1 or 2*/
108 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
109 This mode is activated by the NSSP bit in the SPIx_CR2 register and
110 it takes effect only if the SPI interface is configured as Motorola SPI
111 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
112 CPOL setting is ignored).. */
116 * @brief HAL State structures definition
120 HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
121 HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
122 HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
123 HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
124 HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
125 HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
126 HAL_SPI_STATE_TIMEOUT = 0x06, /*!< Timeout state */
127 HAL_SPI_STATE_ERROR = 0x07 /*!< Data Transmission and Reception process is ongoing */
129 }HAL_SPI_StateTypeDef;
132 * @brief HAL SPI Error Code structure definition
136 HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
137 HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
138 HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
139 HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
140 HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
141 HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
142 HAL_SPI_ERROR_FLAG = 0x20, /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
143 HAL_SPI_ERROR_UNKNOW = 0x40, /*!< Unknow Error error */
144 }HAL_SPI_ErrorTypeDef;
147 * @brief SPI handle Structure definition
149 typedef struct __SPI_HandleTypeDef
151 SPI_TypeDef *Instance; /* SPI registers base address */
153 SPI_InitTypeDef Init; /* SPI communication parameters */
155 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
157 uint16_t TxXferSize; /* SPI Tx Transfer size */
159 uint16_t TxXferCount; /* SPI Tx Transfer Counter */
161 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
163 uint16_t RxXferSize; /* SPI Rx Transfer size */
165 uint16_t RxXferCount; /* SPI Rx Transfer Counter */
167 uint32_t CRCSize; /* SPI CRC size used for the transfer */
169 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
171 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
173 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
175 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
177 HAL_LockTypeDef Lock; /* Locking object */
179 HAL_SPI_StateTypeDef State; /* SPI communication state */
181 HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
189 /* Exported constants --------------------------------------------------------*/
191 /** @defgroup SPI_Exported_Constants SPI Exported Constants
195 /** @defgroup SPI_mode SPI mode
199 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
200 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
201 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
202 ((MODE) == SPI_MODE_MASTER))
207 /** @defgroup SPI_Direction SPI Direction
210 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
211 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
212 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
214 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
215 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
216 ((MODE) == SPI_DIRECTION_1LINE))
218 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
220 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
221 ((MODE) == SPI_DIRECTION_1LINE))
226 /** @defgroup SPI_data_size SPI data size
230 #define SPI_DATASIZE_4BIT ((uint16_t)0x0300)
231 #define SPI_DATASIZE_5BIT ((uint16_t)0x0400)
232 #define SPI_DATASIZE_6BIT ((uint16_t)0x0500)
233 #define SPI_DATASIZE_7BIT ((uint16_t)0x0600)
234 #define SPI_DATASIZE_8BIT ((uint16_t)0x0700)
235 #define SPI_DATASIZE_9BIT ((uint16_t)0x0800)
236 #define SPI_DATASIZE_10BIT ((uint16_t)0x0900)
237 #define SPI_DATASIZE_11BIT ((uint16_t)0x0A00)
238 #define SPI_DATASIZE_12BIT ((uint16_t)0x0B00)
239 #define SPI_DATASIZE_13BIT ((uint16_t)0x0C00)
240 #define SPI_DATASIZE_14BIT ((uint16_t)0x0D00)
241 #define SPI_DATASIZE_15BIT ((uint16_t)0x0E00)
242 #define SPI_DATASIZE_16BIT ((uint16_t)0x0F00)
243 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
244 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
245 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
246 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
247 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
248 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
249 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
250 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
251 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
252 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
253 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
254 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
255 ((DATASIZE) == SPI_DATASIZE_4BIT))
261 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
265 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
266 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
267 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
268 ((CPOL) == SPI_POLARITY_HIGH))
273 /** @defgroup SPI_Clock_Phase SPI Clock Phase
277 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
278 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
279 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
280 ((CPHA) == SPI_PHASE_2EDGE))
285 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
289 #define SPI_NSS_SOFT SPI_CR1_SSM
290 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
291 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
292 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
293 ((NSS) == SPI_NSS_HARD_INPUT) || \
294 ((NSS) == SPI_NSS_HARD_OUTPUT))
301 /** @defgroup SPI_NSS SPI NSS pulse management
304 #define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
305 #define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000)
307 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \
308 ((NSSP) == SPI_NSS_PULSE_DISABLED))
315 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
319 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
320 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
321 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
322 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
323 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
324 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
325 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
326 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
327 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
328 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
329 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
330 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
331 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
332 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
333 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
334 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
339 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
343 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
344 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
345 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
346 ((BIT) == SPI_FIRSTBIT_LSB))
351 /** @defgroup SPI_TI_mode SPI TI mode
355 #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
356 #define SPI_TIMODE_ENABLED SPI_CR2_FRF
357 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
358 ((MODE) == SPI_TIMODE_ENABLED))
363 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
367 #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
368 #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
369 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
370 ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
375 /** @defgroup SPI_CRC_length SPI CRC length
377 * This parameter can be one of the following values:
378 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
379 * SPI_CRC_LENGTH_8BIT : CRC 8bit
380 * SPI_CRC_LENGTH_16BIT : CRC 16bit
382 #define SPI_CRC_LENGTH_DATASIZE 0
383 #define SPI_CRC_LENGTH_8BIT 1
384 #define SPI_CRC_LENGTH_16BIT 2
385 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
386 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
387 ((LENGTH) == SPI_CRC_LENGTH_16BIT))
392 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold
394 * This parameter can be one of the following values:
395 * SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
396 * level is greater or equal to 1/2(16-bits).
397 * SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
398 * level is greater or equal to 1/4(8 bits).
400 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
401 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
402 #define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
408 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
409 * @brief SPI Interrupt definition
410 * Elements values convention: 0xXXXXXXXX
411 * - XXXXXXXX : Interrupt control mask
414 #define SPI_IT_TXE SPI_CR2_TXEIE
415 #define SPI_IT_RXNE SPI_CR2_RXNEIE
416 #define SPI_IT_ERR SPI_CR2_ERRIE
417 #define IS_SPI_IT(IT) (((IT) == SPI_IT_TXE) || \
418 ((IT) == SPI_IT_RXNE) || \
419 ((IT) == SPI_IT_ERR))
425 /** @defgroup SPI_Flag_definition SPI Flag definition
426 * @brief Flag definition
427 * Elements values convention: 0xXXXXYYYY
428 * - XXXX : Flag register Index
432 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
433 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
434 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
435 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
436 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
437 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
438 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
439 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
440 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
441 #define IS_SPI_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXNE) || \
442 ((FLAG) == SPI_FLAG_TXE) || \
443 ((FLAG) == SPI_FLAG_BSY) || \
444 ((FLAG) == SPI_FLAG_CRCERR)|| \
445 ((FLAG) == SPI_FLAG_MODF) || \
446 ((FLAG) == SPI_FLAG_OVR) || \
447 ((FLAG) == SPI_FLAG_FTLVL) || \
448 ((FLAG) == SPI_FLAG_FRLVL) || \
449 ((FLAG) == SPI_IT_FRE))
455 /** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level
459 #define SPI_FTLVL_EMPTY ((uint16_t)0x0000)
460 #define SPI_FTLVL_QUARTER_FULL ((uint16_t)0x0800)
461 #define SPI_FTLVL_HALF_FULL ((uint16_t)0x1000)
462 #define SPI_FTLVL_FULL ((uint16_t)0x1800)
469 /** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level
472 #define SPI_FRLVL_EMPTY ((uint16_t)0x0000)
473 #define SPI_FRLVL_QUARTER_FULL ((uint16_t)0x0200)
474 #define SPI_FRLVL_HALF_FULL ((uint16_t)0x0400)
475 #define SPI_FRLVL_FULL ((uint16_t)0x0600)
486 /* Exported macros ------------------------------------------------------------*/
487 /** @defgroup SPI_Exported_Macros SPI Exported Macros
491 /** @brief Reset SPI handle state
492 * @param __HANDLE__: SPI handle.
495 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
497 /** @brief Enables or disables the specified SPI interrupts.
498 * @param __HANDLE__: specifies the SPI Handle.
499 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
500 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
501 * This parameter can be one of the following values:
502 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
503 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
504 * @arg SPI_IT_ERR: Error interrupt enable
508 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
509 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
511 /** @brief Checks if the specified SPI interrupt source is enabled or disabled.
512 * @param __HANDLE__: specifies the SPI Handle.
513 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
514 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
515 * This parameter can be one of the following values:
516 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
517 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
518 * @arg SPI_IT_ERR: Error interrupt enable
519 * @retval The new state of __IT__ (TRUE or FALSE).
521 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
523 /** @brief Checks whether the specified SPI flag is set or not.
524 * @param __HANDLE__: specifies the SPI Handle.
525 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
526 * @param __FLAG__: specifies the flag to check.
527 * This parameter can be one of the following values:
528 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
529 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
530 * @arg SPI_FLAG_CRCERR: CRC error flag
531 * @arg SPI_FLAG_MODF: Mode fault flag
532 * @arg SPI_FLAG_OVR: Overrun flag
533 * @arg SPI_FLAG_BSY: Busy flag
534 * @arg SPI_FLAG_FRE: Frame format error flag
535 * @retval The new state of __FLAG__ (TRUE or FALSE).
537 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
539 /** @brief Clears the SPI CRCERR pending flag.
540 * @param __HANDLE__: specifies the SPI Handle.
541 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
544 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
546 /** @brief Clears the SPI MODF pending flag.
547 * @param __HANDLE__: specifies the SPI Handle.
548 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
552 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
553 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
555 /** @brief Clears the SPI OVR pending flag.
556 * @param __HANDLE__: specifies the SPI Handle.
557 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
561 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
562 (__HANDLE__)->Instance->SR;}while(0)
564 /** @brief Clears the SPI FRE pending flag.
565 * @param __HANDLE__: specifies the SPI Handle.
566 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
570 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
572 /** @brief Enables the SPI.
573 * @param __HANDLE__: specifies the SPI Handle.
574 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
577 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
579 /** @brief Disables the SPI.
580 * @param __HANDLE__: specifies the SPI Handle.
581 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
584 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
586 /** @brief Sets the SPI transmit-only mode.
587 * @param __HANDLE__: specifies the SPI Handle.
588 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
591 #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
593 /** @brief Sets the SPI receive-only mode.
594 * @param __HANDLE__: specifies the SPI Handle.
595 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
598 #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
600 /** @brief Resets the CRC calculation of the SPI.
601 * @param __HANDLE__: specifies the SPI Handle.
602 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
605 #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
606 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
609 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
614 /* Exported functions --------------------------------------------------------*/
615 /** @addtogroup SPI_Exported_Functions SPI Exported Functions
619 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
623 /* Initialization and de-initialization functions ****************************/
624 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
625 HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi);
626 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
627 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
628 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
633 /** @addtogroup SPI_Exported_Functions_Group2 Input and Output operation functions
637 /* IO operation functions *****************************************************/
638 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
639 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
640 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
641 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
642 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
643 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
644 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
645 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
646 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
647 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
648 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
649 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
650 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
651 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
656 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral Control functions
660 /* Peripheral State and Error functions ***************************************/
661 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
682 #endif /* __STM32F3xx_HAL_SPI_H */
684 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/