2 ******************************************************************************
3 * @file stm32f3xx_hal_sram.c
4 * @author MCD Application Team
7 * @brief SRAM HAL module driver.
8 * This file provides a generic firmware to drive SRAM memories
9 * mounted as external device.
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
16 This driver is a generic layered driver which contains a set of APIs used to
17 control SRAM memories. It uses the FMC layer functions to interface
19 The following sequence should be followed to configure the FMC/FSMC to interface
20 with SRAM/PSRAM memories:
22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
23 SRAM_HandleTypeDef hsram; and:
25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
26 values of the structure member.
28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
29 base register instance for NOR or SRAM device
31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
32 base register instance for NOR or SRAM extended mode
34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
35 mode timings; for example:
36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
37 and fill its fields with the allowed values of the structure member.
39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
40 performs the following sequence:
42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
43 (##) Control register configuration using the FMC NORSRAM interface function
45 (##) Timing register configuration using the FMC NORSRAM interface function
46 FMC_NORSRAM_Timing_Init()
47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
48 FMC_NORSRAM_Extended_Timing_Init()
49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
51 (#) At this stage you can perform read/write accesses from/to the memory connected
52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
60 (#) You can continuously monitor the SRAM device HAL state by calling the function
64 ******************************************************************************
67 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
69 * Redistribution and use in source and binary forms, with or without modification,
70 * are permitted provided that the following conditions are met:
71 * 1. Redistributions of source code must retain the above copyright notice,
72 * this list of conditions and the following disclaimer.
73 * 2. Redistributions in binary form must reproduce the above copyright notice,
74 * this list of conditions and the following disclaimer in the documentation
75 * and/or other materials provided with the distribution.
76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
77 * may be used to endorse or promote products derived from this software
78 * without specific prior written permission.
80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
91 ******************************************************************************
94 /* Includes ------------------------------------------------------------------*/
95 #include "stm32f3xx_hal.h"
97 /** @addtogroup STM32F3xx_HAL_Driver
101 /** @defgroup SRAM SRAM HAL module driver.
102 * @brief SRAM HAL module driver.
105 #ifdef HAL_SRAM_MODULE_ENABLED
107 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
109 /* Private typedef -----------------------------------------------------------*/
110 /* Private define ------------------------------------------------------------*/
111 /* Private macro -------------------------------------------------------------*/
112 /* Private variables ---------------------------------------------------------*/
113 /* Private function prototypes -----------------------------------------------*/
114 /* Exported functions ---------------------------------------------------------*/
116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
121 * @brief Initialization and Configuration functions.
124 ==============================================================================
125 ##### SRAM Initialization and de_initialization functions #####
126 ==============================================================================
127 [..] This section provides functions allowing to initialize/de-initialize
135 * @brief Performs the SRAM device initialization sequence
136 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
137 * the configuration information for SRAM module.
138 * @param Timing: Pointer to SRAM control timing structure
139 * @param ExtTiming: Pointer to SRAM extended mode timing structure
142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
144 /* Check the SRAM handle parameter */
145 if(hsram == HAL_NULL)
150 if(hsram->State == HAL_SRAM_STATE_RESET)
152 /* Initialize the low level hardware (MSP) */
153 HAL_SRAM_MspInit(hsram);
156 /* Initialize SRAM control Interface */
157 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
159 /* Initialize SRAM timing Interface */
160 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
162 /* Initialize SRAM extended mode timing Interface */
163 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
165 /* Enable the NORSRAM device */
166 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
172 * @brief Performs the SRAM device De-initialization sequence.
173 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
174 * the configuration information for SRAM module.
177 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
179 /* De-Initialize the low level hardware (MSP) */
180 HAL_SRAM_MspDeInit(hsram);
182 /* Configure the SRAM registers with their reset values */
183 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
185 hsram->State = HAL_SRAM_STATE_RESET;
194 * @brief SRAM MSP Init.
195 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
196 * the configuration information for SRAM module.
199 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
201 /* NOTE : This function Should not be modified, when the callback is needed,
202 the HAL_SRAM_MspInit could be implemented in the user file
207 * @brief SRAM MSP DeInit.
208 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
209 * the configuration information for SRAM module.
212 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
214 /* NOTE : This function Should not be modified, when the callback is needed,
215 the HAL_SRAM_MspDeInit could be implemented in the user file
220 * @brief DMA transfer complete callback.
221 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
222 * the configuration information for SRAM module.
225 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
227 /* NOTE : This function Should not be modified, when the callback is needed,
228 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
233 * @brief DMA transfer complete error callback.
234 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
235 * the configuration information for SRAM module.
238 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
240 /* NOTE : This function Should not be modified, when the callback is needed,
241 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
249 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
250 * @brief Input Output and memory control functions
253 ==============================================================================
254 ##### SRAM Input and Output functions #####
255 ==============================================================================
257 This section provides functions allowing to use and control the SRAM memory
264 * @brief Reads 8-bit buffer from SRAM memory.
265 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
266 * the configuration information for SRAM module.
267 * @param pAddress: Pointer to read start address
268 * @param pDstBuffer: Pointer to destination buffer
269 * @param BufferSize: Size of the buffer to read from memory
272 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
274 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
279 /* Update the SRAM controller state */
280 hsram->State = HAL_SRAM_STATE_BUSY;
282 /* Read data from memory */
283 for(; BufferSize != 0; BufferSize--)
285 *pDstBuffer = *(__IO uint8_t *)psramaddress;
290 /* Update the SRAM controller state */
291 hsram->State = HAL_SRAM_STATE_READY;
293 /* Process unlocked */
300 * @brief Writes 8-bit buffer to SRAM memory.
301 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
302 * the configuration information for SRAM module.
303 * @param pAddress: Pointer to write start address
304 * @param pSrcBuffer: Pointer to source buffer to write
305 * @param BufferSize: Size of the buffer to write to memory
308 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
310 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
312 /* Check the SRAM controller state */
313 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
321 /* Update the SRAM controller state */
322 hsram->State = HAL_SRAM_STATE_BUSY;
324 /* Write data to memory */
325 for(; BufferSize != 0; BufferSize--)
327 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
332 /* Update the SRAM controller state */
333 hsram->State = HAL_SRAM_STATE_READY;
335 /* Process unlocked */
342 * @brief Reads 16-bit buffer from SRAM memory.
343 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
344 * the configuration information for SRAM module.
345 * @param pAddress: Pointer to read start address
346 * @param pDstBuffer: Pointer to destination buffer
347 * @param BufferSize: Size of the buffer to read from memory
350 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
352 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
357 /* Update the SRAM controller state */
358 hsram->State = HAL_SRAM_STATE_BUSY;
360 /* Read data from memory */
361 for(; BufferSize != 0; BufferSize--)
363 *pDstBuffer = *(__IO uint16_t *)psramaddress;
368 /* Update the SRAM controller state */
369 hsram->State = HAL_SRAM_STATE_READY;
371 /* Process unlocked */
378 * @brief Writes 16-bit buffer to SRAM memory.
379 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
380 * the configuration information for SRAM module.
381 * @param pAddress: Pointer to write start address
382 * @param pSrcBuffer: Pointer to source buffer to write
383 * @param BufferSize: Size of the buffer to write to memory
386 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
388 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
390 /* Check the SRAM controller state */
391 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
399 /* Update the SRAM controller state */
400 hsram->State = HAL_SRAM_STATE_BUSY;
402 /* Write data to memory */
403 for(; BufferSize != 0; BufferSize--)
405 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
410 /* Update the SRAM controller state */
411 hsram->State = HAL_SRAM_STATE_READY;
413 /* Process unlocked */
420 * @brief Reads 32-bit buffer from SRAM memory.
421 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
422 * the configuration information for SRAM module.
423 * @param pAddress: Pointer to read start address
424 * @param pDstBuffer: Pointer to destination buffer
425 * @param BufferSize: Size of the buffer to read from memory
428 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
433 /* Update the SRAM controller state */
434 hsram->State = HAL_SRAM_STATE_BUSY;
436 /* Read data from memory */
437 for(; BufferSize != 0; BufferSize--)
439 *pDstBuffer = *(__IO uint32_t *)pAddress;
444 /* Update the SRAM controller state */
445 hsram->State = HAL_SRAM_STATE_READY;
447 /* Process unlocked */
454 * @brief Writes 32-bit buffer to SRAM memory.
455 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
456 * the configuration information for SRAM module.
457 * @param pAddress: Pointer to write start address
458 * @param pSrcBuffer: Pointer to source buffer to write
459 * @param BufferSize: Size of the buffer to write to memory
462 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
464 /* Check the SRAM controller state */
465 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
473 /* Update the SRAM controller state */
474 hsram->State = HAL_SRAM_STATE_BUSY;
476 /* Write data to memory */
477 for(; BufferSize != 0; BufferSize--)
479 *(__IO uint32_t *)pAddress = *pSrcBuffer;
484 /* Update the SRAM controller state */
485 hsram->State = HAL_SRAM_STATE_READY;
487 /* Process unlocked */
494 * @brief Reads a Words data from the SRAM memory using DMA transfer.
495 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
496 * the configuration information for SRAM module.
497 * @param pAddress: Pointer to read start address
498 * @param pDstBuffer: Pointer to destination buffer
499 * @param BufferSize: Size of the buffer to read from memory
502 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
507 /* Update the SRAM controller state */
508 hsram->State = HAL_SRAM_STATE_BUSY;
510 /* Configure DMA user callbacks */
511 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
512 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
514 /* Enable the DMA Stream */
515 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
517 /* Update the SRAM controller state */
518 hsram->State = HAL_SRAM_STATE_READY;
520 /* Process unlocked */
527 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
528 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
529 * the configuration information for SRAM module.
530 * @param pAddress: Pointer to write start address
531 * @param pSrcBuffer: Pointer to source buffer to write
532 * @param BufferSize: Size of the buffer to write to memory
535 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
537 /* Check the SRAM controller state */
538 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
546 /* Update the SRAM controller state */
547 hsram->State = HAL_SRAM_STATE_BUSY;
549 /* Configure DMA user callbacks */
550 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
551 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
553 /* Enable the DMA Stream */
554 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
556 /* Update the SRAM controller state */
557 hsram->State = HAL_SRAM_STATE_READY;
559 /* Process unlocked */
569 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
570 * @brief Control functions
573 ==============================================================================
574 ##### SRAM Control functions #####
575 ==============================================================================
577 This subsection provides a set of functions allowing to control dynamically
585 * @brief Enables dynamically SRAM write operation.
586 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
587 * the configuration information for SRAM module.
590 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
595 /* Enable write operation */
596 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
598 /* Update the SRAM controller state */
599 hsram->State = HAL_SRAM_STATE_READY;
601 /* Process unlocked */
608 * @brief Disables dynamically SRAM write operation.
609 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
610 * the configuration information for SRAM module.
613 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
618 /* Update the SRAM controller state */
619 hsram->State = HAL_SRAM_STATE_BUSY;
621 /* Disable write operation */
622 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
624 /* Update the SRAM controller state */
625 hsram->State = HAL_SRAM_STATE_PROTECTED;
627 /* Process unlocked */
637 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
638 * @brief Peripheral State functions
641 ==============================================================================
642 ##### SRAM State functions #####
643 ==============================================================================
645 This subsection permits to get in run-time the status of the SRAM controller
653 * @brief Returns the SRAM controller state
654 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
655 * the configuration information for SRAM module.
658 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
670 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
671 #endif /* HAL_SRAM_MODULE_ENABLED */
680 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/