2 ******************************************************************************
3 * @file stm32f3xx_hal_tim_ex.c
4 * @author MCD Application Team
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer Extended peripheral:
10 * + Time Hall Sensor Interface Initialization
11 * + Time Hall Sensor Interface Start
12 * + Time Complementary signal bread and dead time configuration
13 * + Time Master and Slave synchronization configuration
14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
15 * + Time OCRef clear configuration
16 * + Timer remapping capabilities configuration
18 ==============================================================================
19 ##### TIMER Extended features #####
20 ==============================================================================
22 The Timer Extended features include:
23 (#) Complementary outputs with programmable dead-time for :
25 (++) PWM generation (Edge and Center-aligned Mode)
26 (++) One-pulse mode output
27 (#) Synchronization circuit to control the timer with external signals and to
28 interconnect several timers together.
29 (#) Break input to put the timer output signals in reset state or in a known state.
30 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
33 ##### How to use this driver #####
34 ==============================================================================
36 (#) Initialize the TIM low level resources by implementing the following functions
37 depending from feature used :
38 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
39 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
40 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
41 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
43 (#) Initialize the TIM low level resources :
44 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
45 (##) TIM pins configuration
46 (+++) Enable the clock for the TIM GPIOs using the following function:
48 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
50 (#) The external Clock can be configured, if needed (the default clock is the
51 internal clock from the APBx), using the following function:
52 HAL_TIM_ConfigClockSource, the clock configuration should be done before
55 (#) Configure the TIM in the desired functioning mode using one of the
56 initialization function of this driver:
57 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
58 Timer Hall Sensor Interface and the commutation event with the corresponding
59 Interrupt and DMA request if needed (Note that One Timer is used to interface
60 with the Hall sensor Interface and another Timer should be used to use
61 the commutation event).
63 (#) Activate the TIM peripheral using one of the start functions:
64 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
65 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
66 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
67 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
71 ******************************************************************************
74 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
76 * Redistribution and use in source and binary forms, with or without modification,
77 * are permitted provided that the following conditions are met:
78 * 1. Redistributions of source code must retain the above copyright notice,
79 * this list of conditions and the following disclaimer.
80 * 2. Redistributions in binary form must reproduce the above copyright notice,
81 * this list of conditions and the following disclaimer in the documentation
82 * and/or other materials provided with the distribution.
83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
84 * may be used to endorse or promote products derived from this software
85 * without specific prior written permission.
87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
98 ******************************************************************************
101 /* Includes ------------------------------------------------------------------*/
102 #include "stm32f3xx_hal.h"
104 /** @addtogroup STM32F3xx_HAL_Driver
108 /** @defgroup TIMEx TIM Extended HAL module driver
109 * @brief TIM Extended HAL module driver
113 #ifdef HAL_TIM_MODULE_ENABLED
115 /* Private typedef -----------------------------------------------------------*/
116 /* Private define ------------------------------------------------------------*/
117 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
118 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
119 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
120 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
122 #define BDTR_BKF_SHIFT (16)
123 #define BDTR_BK2F_SHIFT (20)
124 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
125 /* STM32F302xC || STM32F303xC || STM32F358xx || */
126 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
127 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
129 /* Private macro -------------------------------------------------------------*/
130 /* Private variables ---------------------------------------------------------*/
131 /* Private function prototypes -----------------------------------------------*/
132 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
133 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
134 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
135 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
136 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
137 TIM_OC_InitTypeDef *OC_Config);
139 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
140 TIM_OC_InitTypeDef *OC_Config);
141 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
142 /* STM32F302xC || STM32F303xC || STM32F358xx || */
143 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
144 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
146 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
148 /* Private functions ---------------------------------------------------------*/
149 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
150 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
151 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
152 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
154 * @brief Timer Ouput Compare 5 configuration
155 * @param TIMx to select the TIM peripheral
156 * @param OC_Config: The ouput configuration structure
159 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
160 TIM_OC_InitTypeDef *OC_Config)
162 uint32_t tmpccmrx = 0;
163 uint32_t tmpccer = 0;
166 /* Disable the output: Reset the CCxE Bit */
167 TIMx->CCER &= ~TIM_CCER_CC5E;
169 /* Get the TIMx CCER register value */
170 tmpccer = TIMx->CCER;
171 /* Get the TIMx CR2 register value */
173 /* Get the TIMx CCMR1 register value */
174 tmpccmrx = TIMx->CCMR3;
176 /* Reset the Output Compare Mode Bits */
177 tmpccmrx &= ~(TIM_CCMR3_OC5M);
178 /* Select the Output Compare Mode */
179 tmpccmrx |= OC_Config->OCMode;
181 /* Reset the Output Polarity level */
182 tmpccer &= ~TIM_CCER_CC5P;
183 /* Set the Output Compare Polarity */
184 tmpccer |= (OC_Config->OCPolarity << 16);
186 if(IS_TIM_BREAK_INSTANCE(TIMx))
188 /* Reset the Output Compare IDLE State */
189 tmpcr2 &= ~TIM_CR2_OIS5;
190 /* Set the Output Idle state */
191 tmpcr2 |= (OC_Config->OCIdleState << 8);
193 /* Write to TIMx CR2 */
196 /* Write to TIMx CCMR3 */
197 TIMx->CCMR3 = tmpccmrx;
199 /* Set the Capture Compare Register value */
200 TIMx->CCR5 = OC_Config->Pulse;
202 /* Write to TIMx CCER */
203 TIMx->CCER = tmpccer;
207 * @brief Timer Ouput Compare 6 configuration
208 * @param TIMx to select the TIM peripheral
209 * @param OC_Config: The ouput configuration structure
212 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
213 TIM_OC_InitTypeDef *OC_Config)
215 uint32_t tmpccmrx = 0;
216 uint32_t tmpccer = 0;
219 /* Disable the output: Reset the CCxE Bit */
220 TIMx->CCER &= ~TIM_CCER_CC6E;
222 /* Get the TIMx CCER register value */
223 tmpccer = TIMx->CCER;
224 /* Get the TIMx CR2 register value */
226 /* Get the TIMx CCMR1 register value */
227 tmpccmrx = TIMx->CCMR3;
229 /* Reset the Output Compare Mode Bits */
230 tmpccmrx &= ~(TIM_CCMR3_OC6M);
231 /* Select the Output Compare Mode */
232 tmpccmrx |= (OC_Config->OCMode << 8);
234 /* Reset the Output Polarity level */
235 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
236 /* Set the Output Compare Polarity */
237 tmpccer |= (OC_Config->OCPolarity << 20);
239 if(IS_TIM_BREAK_INSTANCE(TIMx))
241 /* Reset the Output Compare IDLE State */
242 tmpcr2 &= ~TIM_CR2_OIS6;
243 /* Set the Output Idle state */
244 tmpcr2 |= (OC_Config->OCIdleState << 10);
247 /* Write to TIMx CR2 */
250 /* Write to TIMx CCMR3 */
251 TIMx->CCMR3 = tmpccmrx;
253 /* Set the Capture Compare Register value */
254 TIMx->CCR6 = OC_Config->Pulse;
256 /* Write to TIMx CCER */
257 TIMx->CCER = tmpccer;
259 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
260 /* STM32F302xC || STM32F303xC || STM32F358xx || */
261 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
262 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
264 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
268 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
269 * @brief Timer Hall Sensor functions
272 ==============================================================================
273 ##### Timer Hall Sensor functions #####
274 ==============================================================================
276 This section provides functions allowing to:
277 (+) Initialize and configure TIM HAL Sensor.
278 (+) De-initialize TIM HAL Sensor.
279 (+) Start the Hall Sensor Interface.
280 (+) Stop the Hall Sensor Interface.
281 (+) Start the Hall Sensor Interface and enable interrupts.
282 (+) Stop the Hall Sensor Interface and disable interrupts.
283 (+) Start the Hall Sensor Interface and enable DMA transfers.
284 (+) Stop the Hall Sensor Interface and disable DMA transfers.
290 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
291 * @param htim: TIM Encoder Interface handle
292 * @param sConfig: TIM Hall Sensor configuration structure
295 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
297 TIM_OC_InitTypeDef OC_Config;
299 /* Check the TIM handle allocation */
305 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
306 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
307 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
308 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
309 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
310 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
312 /* Set the TIM state */
313 htim->State= HAL_TIM_STATE_BUSY;
315 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
316 HAL_TIMEx_HallSensor_MspInit(htim);
318 /* Configure the Time base in the Encoder Mode */
319 TIM_Base_SetConfig(htim->Instance, &htim->Init);
321 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
322 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
324 /* Reset the IC1PSC Bits */
325 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
326 /* Set the IC1PSC value */
327 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
329 /* Enable the Hall sensor interface (XOR function of the three inputs) */
330 htim->Instance->CR2 |= TIM_CR2_TI1S;
332 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
333 htim->Instance->SMCR &= ~TIM_SMCR_TS;
334 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
336 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
337 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
338 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
340 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
341 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
342 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
343 OC_Config.OCMode = TIM_OCMODE_PWM2;
344 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
345 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
346 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
347 OC_Config.Pulse = sConfig->Commutation_Delay;
349 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
351 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
353 htim->Instance->CR2 &= ~TIM_CR2_MMS;
354 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
356 /* Initialize the TIM state*/
357 htim->State= HAL_TIM_STATE_READY;
363 * @brief DeInitializes the TIM Hall Sensor interface
364 * @param htim: TIM Hall Sensor handle
367 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
369 /* Check the parameters */
370 assert_param(IS_TIM_INSTANCE(htim->Instance));
372 htim->State = HAL_TIM_STATE_BUSY;
374 /* Disable the TIM Peripheral Clock */
375 __HAL_TIM_DISABLE(htim);
377 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
378 HAL_TIMEx_HallSensor_MspDeInit(htim);
380 /* Change TIM state */
381 htim->State = HAL_TIM_STATE_RESET;
390 * @brief Initializes the TIM Hall Sensor MSP.
391 * @param htim: TIM handle
394 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
396 /* NOTE : This function Should not be modified, when the callback is needed,
397 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
402 * @brief DeInitializes TIM Hall Sensor MSP.
403 * @param htim: TIM handle
406 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
408 /* NOTE : This function Should not be modified, when the callback is needed,
409 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
414 * @brief Starts the TIM Hall Sensor Interface.
415 * @param htim : TIM Hall Sensor handle
418 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
420 /* Check the parameters */
421 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
423 /* Enable the Input Capture channels 1
424 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
425 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
427 /* Enable the Peripheral */
428 __HAL_TIM_ENABLE(htim);
430 /* Return function status */
435 * @brief Stops the TIM Hall sensor Interface.
436 * @param htim : TIM Hall Sensor handle
439 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
441 /* Check the parameters */
442 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
444 /* Disable the Input Capture channels 1, 2 and 3
445 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
446 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
448 /* Disable the Peripheral */
449 __HAL_TIM_DISABLE(htim);
451 /* Return function status */
456 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
457 * @param htim : TIM Hall Sensor handle
460 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
462 /* Check the parameters */
463 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
465 /* Enable the capture compare Interrupts 1 event */
466 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
468 /* Enable the Input Capture channels 1
469 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
470 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
472 /* Enable the Peripheral */
473 __HAL_TIM_ENABLE(htim);
475 /* Return function status */
480 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
481 * @param htim : TIM handle
484 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
486 /* Check the parameters */
487 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
489 /* Disable the Input Capture channels 1
490 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
493 /* Disable the capture compare Interrupts event */
494 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
496 /* Disable the Peripheral */
497 __HAL_TIM_DISABLE(htim);
499 /* Return function status */
504 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
505 * @param htim : TIM Hall Sensor handle
506 * @param pData: The destination Buffer address.
507 * @param Length: The length of data to be transferred from TIM peripheral to memory.
510 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
512 /* Check the parameters */
513 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
515 if((htim->State == HAL_TIM_STATE_BUSY))
519 else if((htim->State == HAL_TIM_STATE_READY))
521 if(((uint32_t)pData == 0 ) && (Length > 0))
527 htim->State = HAL_TIM_STATE_BUSY;
530 /* Enable the Input Capture channels 1
531 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
532 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
534 /* Set the DMA Input Capture 1 Callback */
535 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
536 /* Set the DMA error callback */
537 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
539 /* Enable the DMA channel for Capture 1*/
540 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
542 /* Enable the capture compare 1 Interrupt */
543 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
545 /* Enable the Peripheral */
546 __HAL_TIM_ENABLE(htim);
548 /* Return function status */
553 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
554 * @param htim : TIM handle
557 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
559 /* Check the parameters */
560 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
562 /* Disable the Input Capture channels 1
563 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
564 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
567 /* Disable the capture compare Interrupts 1 event */
568 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
570 /* Disable the Peripheral */
571 __HAL_TIM_DISABLE(htim);
573 /* Return function status */
581 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
582 * @brief Timer Complementary Output Compare functions
585 ==============================================================================
586 ##### Timer Complementary Output Compare functions #####
587 ==============================================================================
589 This section provides functions allowing to:
590 (+) Start the Complementary Output Compare/PWM.
591 (+) Stop the Complementary Output Compare/PWM.
592 (+) Start the Complementary Output Compare/PWM and enable interrupts.
593 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
594 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
595 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
602 * @brief Starts the TIM Output Compare signal generation on the complementary
604 * @param htim : TIM Output Compare handle
605 * @param Channel : TIM Channel to be enabled
606 * This parameter can be one of the following values:
607 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
608 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
609 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
610 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
613 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
615 /* Check the parameters */
616 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
618 /* Enable the Capture compare channel N */
619 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
621 /* Enable the Main Ouput */
622 __HAL_TIM_MOE_ENABLE(htim);
624 /* Enable the Peripheral */
625 __HAL_TIM_ENABLE(htim);
627 /* Return function status */
632 * @brief Stops the TIM Output Compare signal generation on the complementary
634 * @param htim : TIM handle
635 * @param Channel : TIM Channel to be disabled
636 * This parameter can be one of the following values:
637 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
638 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
639 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
640 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
643 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
645 /* Check the parameters */
646 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
648 /* Disable the Capture compare channel N */
649 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
651 /* Disable the Main Ouput */
652 __HAL_TIM_MOE_DISABLE(htim);
654 /* Disable the Peripheral */
655 __HAL_TIM_DISABLE(htim);
657 /* Return function status */
662 * @brief Starts the TIM Output Compare signal generation in interrupt mode
663 * on the complementary output.
664 * @param htim : TIM OC handle
665 * @param Channel : TIM Channel to be enabled
666 * This parameter can be one of the following values:
667 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
668 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
669 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
670 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
673 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
675 /* Check the parameters */
676 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
682 /* Enable the TIM Output Compare interrupt */
683 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
689 /* Enable the TIM Output Compare interrupt */
690 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
696 /* Enable the TIM Output Compare interrupt */
697 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
703 /* Enable the TIM Output Compare interrupt */
704 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
712 /* Enable the TIM Break interrupt */
713 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
715 /* Enable the Capture compare channel N */
716 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
718 /* Enable the Main Ouput */
719 __HAL_TIM_MOE_ENABLE(htim);
721 /* Enable the Peripheral */
722 __HAL_TIM_ENABLE(htim);
724 /* Return function status */
729 * @brief Stops the TIM Output Compare signal generation in interrupt mode
730 * on the complementary output.
731 * @param htim : TIM Output Compare handle
732 * @param Channel : TIM Channel to be disabled
733 * This parameter can be one of the following values:
734 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
735 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
736 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
737 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
740 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
742 uint32_t tmpccer = 0;
744 /* Check the parameters */
745 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
751 /* Disable the TIM Output Compare interrupt */
752 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
758 /* Disable the TIM Output Compare interrupt */
759 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
765 /* Disable the TIM Output Compare interrupt */
766 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
772 /* Disable the TIM Output Compare interrupt */
773 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
781 /* Disable the Capture compare channel N */
782 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
784 /* Disable the TIM Break interrupt (only if no more channel is active) */
785 tmpccer = htim->Instance->CCER;
786 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
788 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
791 /* Disable the Main Ouput */
792 __HAL_TIM_MOE_DISABLE(htim);
794 /* Disable the Peripheral */
795 __HAL_TIM_DISABLE(htim);
797 /* Return function status */
802 * @brief Starts the TIM Output Compare signal generation in DMA mode
803 * on the complementary output.
804 * @param htim : TIM Output Compare handle
805 * @param Channel : TIM Channel to be enabled
806 * This parameter can be one of the following values:
807 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
808 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
809 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
810 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
811 * @param pData: The source Buffer address.
812 * @param Length: The length of data to be transferred from memory to TIM peripheral
815 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
817 /* Check the parameters */
818 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
820 if((htim->State == HAL_TIM_STATE_BUSY))
824 else if((htim->State == HAL_TIM_STATE_READY))
826 if(((uint32_t)pData == 0 ) && (Length > 0))
832 htim->State = HAL_TIM_STATE_BUSY;
839 /* Set the DMA Period elapsed callback */
840 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
842 /* Set the DMA error callback */
843 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
845 /* Enable the DMA channel */
846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
848 /* Enable the TIM Output Compare DMA request */
849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
855 /* Set the DMA Period elapsed callback */
856 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
858 /* Set the DMA error callback */
859 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
861 /* Enable the DMA channel */
862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
864 /* Enable the TIM Output Compare DMA request */
865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
871 /* Set the DMA Period elapsed callback */
872 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
874 /* Set the DMA error callback */
875 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
877 /* Enable the DMA channel */
878 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
880 /* Enable the TIM Output Compare DMA request */
881 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
887 /* Set the DMA Period elapsed callback */
888 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
890 /* Set the DMA error callback */
891 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
893 /* Enable the DMA channel */
894 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
896 /* Enable the TIM Output Compare DMA request */
897 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
905 /* Enable the Capture compare channel N */
906 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
908 /* Enable the Main Ouput */
909 __HAL_TIM_MOE_ENABLE(htim);
911 /* Enable the Peripheral */
912 __HAL_TIM_ENABLE(htim);
914 /* Return function status */
919 * @brief Stops the TIM Output Compare signal generation in DMA mode
920 * on the complementary output.
921 * @param htim : TIM Output Compare handle
922 * @param Channel : TIM Channel to be disabled
923 * This parameter can be one of the following values:
924 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
925 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
926 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
927 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
930 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
932 /* Check the parameters */
933 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
939 /* Disable the TIM Output Compare DMA request */
940 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
946 /* Disable the TIM Output Compare DMA request */
947 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
953 /* Disable the TIM Output Compare DMA request */
954 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
960 /* Disable the TIM Output Compare interrupt */
961 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
969 /* Disable the Capture compare channel N */
970 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
972 /* Disable the Main Ouput */
973 __HAL_TIM_MOE_DISABLE(htim);
975 /* Disable the Peripheral */
976 __HAL_TIM_DISABLE(htim);
978 /* Change the htim state */
979 htim->State = HAL_TIM_STATE_READY;
981 /* Return function status */
989 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
990 * @brief Timer Complementary PWM functions
993 ==============================================================================
994 ##### Timer Complementary PWM functions #####
995 ==============================================================================
997 This section provides functions allowing to:
998 (+) Start the Complementary PWM.
999 (+) Stop the Complementary PWM.
1000 (+) Start the Complementary PWM and enable interrupts.
1001 (+) Stop the Complementary PWM and disable interrupts.
1002 (+) Start the Complementary PWM and enable DMA transfers.
1003 (+) Stop the Complementary PWM and disable DMA transfers.
1004 (+) Start the Complementary Input Capture measurement.
1005 (+) Stop the Complementary Input Capture.
1006 (+) Start the Complementary Input Capture and enable interrupts.
1007 (+) Stop the Complementary Input Capture and disable interrupts.
1008 (+) Start the Complementary Input Capture and enable DMA transfers.
1009 (+) Stop the Complementary Input Capture and disable DMA transfers.
1010 (+) Start the Complementary One Pulse generation.
1011 (+) Stop the Complementary One Pulse.
1012 (+) Start the Complementary One Pulse and enable interrupts.
1013 (+) Stop the Complementary One Pulse and disable interrupts.
1020 * @brief Starts the PWM signal generation on the complementary output.
1021 * @param htim : TIM handle
1022 * @param Channel : TIM Channel to be enabled
1023 * This parameter can be one of the following values:
1024 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1025 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1026 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1027 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1028 * @retval HAL status
1030 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1032 /* Check the parameters */
1033 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1035 /* Enable the complementary PWM output */
1036 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1038 /* Enable the Main Ouput */
1039 __HAL_TIM_MOE_ENABLE(htim);
1041 /* Enable the Peripheral */
1042 __HAL_TIM_ENABLE(htim);
1044 /* Return function status */
1049 * @brief Stops the PWM signal generation on the complementary output.
1050 * @param htim : TIM handle
1051 * @param Channel : TIM Channel to be disabled
1052 * This parameter can be one of the following values:
1053 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1054 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1055 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1056 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1057 * @retval HAL status
1059 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1061 /* Check the parameters */
1062 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1064 /* Disable the complementary PWM output */
1065 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1067 /* Disable the Main Ouput */
1068 __HAL_TIM_MOE_DISABLE(htim);
1070 /* Disable the Peripheral */
1071 __HAL_TIM_DISABLE(htim);
1073 /* Return function status */
1078 * @brief Starts the PWM signal generation in interrupt mode on the
1079 * complementary output.
1080 * @param htim : TIM handle
1081 * @param Channel : TIM Channel to be disabled
1082 * This parameter can be one of the following values:
1083 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1084 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1085 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1086 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1087 * @retval HAL status
1089 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1091 /* Check the parameters */
1092 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1098 /* Enable the TIM Capture/Compare 1 interrupt */
1099 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1105 /* Enable the TIM Capture/Compare 2 interrupt */
1106 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1112 /* Enable the TIM Capture/Compare 3 interrupt */
1113 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1119 /* Enable the TIM Capture/Compare 4 interrupt */
1120 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1128 /* Enable the TIM Break interrupt */
1129 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1131 /* Enable the complementary PWM output */
1132 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1134 /* Enable the Main Ouput */
1135 __HAL_TIM_MOE_ENABLE(htim);
1137 /* Enable the Peripheral */
1138 __HAL_TIM_ENABLE(htim);
1140 /* Return function status */
1145 * @brief Stops the PWM signal generation in interrupt mode on the
1146 * complementary output.
1147 * @param htim : TIM handle
1148 * @param Channel : TIM Channel to be disabled
1149 * This parameter can be one of the following values:
1150 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1151 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1152 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1153 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1154 * @retval HAL status
1156 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1158 uint32_t tmpccer = 0;
1160 /* Check the parameters */
1161 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1167 /* Disable the TIM Capture/Compare 1 interrupt */
1168 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1174 /* Disable the TIM Capture/Compare 2 interrupt */
1175 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1181 /* Disable the TIM Capture/Compare 3 interrupt */
1182 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1188 /* Disable the TIM Capture/Compare 3 interrupt */
1189 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1197 /* Disable the complementary PWM output */
1198 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1200 /* Disable the TIM Break interrupt (only if no more channel is active) */
1201 tmpccer = htim->Instance->CCER;
1202 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
1204 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1207 /* Disable the Main Ouput */
1208 __HAL_TIM_MOE_DISABLE(htim);
1210 /* Disable the Peripheral */
1211 __HAL_TIM_DISABLE(htim);
1213 /* Return function status */
1218 * @brief Starts the TIM PWM signal generation in DMA mode on the
1219 * complementary output
1220 * @param htim : TIM handle
1221 * @param Channel : TIM Channel to be enabled
1222 * This parameter can be one of the following values:
1223 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1224 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1225 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1226 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1227 * @param pData: The source Buffer address.
1228 * @param Length: The length of data to be transferred from memory to TIM peripheral
1229 * @retval HAL status
1231 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1233 /* Check the parameters */
1234 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1236 if((htim->State == HAL_TIM_STATE_BUSY))
1240 else if((htim->State == HAL_TIM_STATE_READY))
1242 if(((uint32_t)pData == 0 ) && (Length > 0))
1248 htim->State = HAL_TIM_STATE_BUSY;
1255 /* Set the DMA Period elapsed callback */
1256 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1258 /* Set the DMA error callback */
1259 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1261 /* Enable the DMA channel */
1262 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1264 /* Enable the TIM Capture/Compare 1 DMA request */
1265 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1271 /* Set the DMA Period elapsed callback */
1272 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1274 /* Set the DMA error callback */
1275 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1277 /* Enable the DMA channel */
1278 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1280 /* Enable the TIM Capture/Compare 2 DMA request */
1281 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1287 /* Set the DMA Period elapsed callback */
1288 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1290 /* Set the DMA error callback */
1291 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1293 /* Enable the DMA channel */
1294 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1296 /* Enable the TIM Capture/Compare 3 DMA request */
1297 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1303 /* Set the DMA Period elapsed callback */
1304 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1306 /* Set the DMA error callback */
1307 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1309 /* Enable the DMA channel */
1310 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1312 /* Enable the TIM Capture/Compare 4 DMA request */
1313 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1321 /* Enable the complementary PWM output */
1322 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1324 /* Enable the Main Ouput */
1325 __HAL_TIM_MOE_ENABLE(htim);
1327 /* Enable the Peripheral */
1328 __HAL_TIM_ENABLE(htim);
1330 /* Return function status */
1335 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1337 * @param htim : TIM handle
1338 * @param Channel : TIM Channel to be disabled
1339 * This parameter can be one of the following values:
1340 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1341 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1342 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1343 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1344 * @retval HAL status
1346 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1348 /* Check the parameters */
1349 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1355 /* Disable the TIM Capture/Compare 1 DMA request */
1356 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1362 /* Disable the TIM Capture/Compare 2 DMA request */
1363 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1369 /* Disable the TIM Capture/Compare 3 DMA request */
1370 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1376 /* Disable the TIM Capture/Compare 4 DMA request */
1377 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1385 /* Disable the complementary PWM output */
1386 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1388 /* Disable the Main Ouput */
1389 __HAL_TIM_MOE_DISABLE(htim);
1391 /* Disable the Peripheral */
1392 __HAL_TIM_DISABLE(htim);
1394 /* Change the htim state */
1395 htim->State = HAL_TIM_STATE_READY;
1397 /* Return function status */
1405 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1406 * @brief Timer Complementary One Pulse functions
1409 ==============================================================================
1410 ##### Timer Complementary One Pulse functions #####
1411 ==============================================================================
1413 This section provides functions allowing to:
1414 (+) Start the Complementary One Pulse generation.
1415 (+) Stop the Complementary One Pulse.
1416 (+) Start the Complementary One Pulse and enable interrupts.
1417 (+) Stop the Complementary One Pulse and disable interrupts.
1424 * @brief Starts the TIM One Pulse signal generation on the complemetary
1426 * @param htim : TIM One Pulse handle
1427 * @param OutputChannel : TIM Channel to be enabled
1428 * This parameter can be one of the following values:
1429 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1430 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1431 * @retval HAL status
1433 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1435 /* Check the parameters */
1436 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1438 /* Enable the complementary One Pulse output */
1439 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1441 /* Enable the Main Ouput */
1442 __HAL_TIM_MOE_ENABLE(htim);
1444 /* Return function status */
1449 * @brief Stops the TIM One Pulse signal generation on the complementary
1451 * @param htim : TIM One Pulse handle
1452 * @param OutputChannel : TIM Channel to be disabled
1453 * This parameter can be one of the following values:
1454 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1455 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1456 * @retval HAL status
1458 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1461 /* Check the parameters */
1462 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1464 /* Disable the complementary One Pulse output */
1465 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1467 /* Disable the Main Ouput */
1468 __HAL_TIM_MOE_DISABLE(htim);
1470 /* Disable the Peripheral */
1471 __HAL_TIM_DISABLE(htim);
1473 /* Return function status */
1478 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1479 * complementary channel.
1480 * @param htim : TIM One Pulse handle
1481 * @param OutputChannel : TIM Channel to be enabled
1482 * This parameter can be one of the following values:
1483 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1484 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1485 * @retval HAL status
1487 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1489 /* Check the parameters */
1490 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1492 /* Enable the TIM Capture/Compare 1 interrupt */
1493 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1495 /* Enable the TIM Capture/Compare 2 interrupt */
1496 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1498 /* Enable the complementary One Pulse output */
1499 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1501 /* Enable the Main Ouput */
1502 __HAL_TIM_MOE_ENABLE(htim);
1504 /* Return function status */
1509 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1510 * complementary channel.
1511 * @param htim : TIM One Pulse handle
1512 * @param OutputChannel : TIM Channel to be disabled
1513 * This parameter can be one of the following values:
1514 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1515 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1516 * @retval HAL status
1518 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1520 /* Check the parameters */
1521 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1523 /* Disable the TIM Capture/Compare 1 interrupt */
1524 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1526 /* Disable the TIM Capture/Compare 2 interrupt */
1527 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1529 /* Disable the complementary One Pulse output */
1530 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1532 /* Disable the Main Ouput */
1533 __HAL_TIM_MOE_DISABLE(htim);
1535 /* Disable the Peripheral */
1536 __HAL_TIM_DISABLE(htim);
1538 /* Return function status */
1547 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1548 * @brief Peripheral Control functions
1551 ==============================================================================
1552 ##### Peripheral Control functions #####
1553 ==============================================================================
1555 This section provides functions allowing to:
1556 (+) Configure the commutation event in case of use of the Hall sensor interface.
1557 (+) Configure Output channels for OC and PWM mode.
1559 (+) Configure Complementary channels, break features and dead time.
1560 (+) Configure Master synchronization.
1561 (+) Configure timer remapping capabilities.
1562 (+) Enable or disable channel grouping
1567 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1568 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1569 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1570 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1572 * @brief Configure the TIM commutation event sequence.
1573 * @note: this function is mandatory to use the commutation event in order to
1574 * update the configuration at each commutation detection on the TRGI input of the Timer,
1575 * the typical use of this feature is with the use of another Timer(interface Timer)
1576 * configured in Hall sensor interface, this interface Timer will generate the
1577 * commutation at its TRGO output (connected to Timer used in this function) each time
1578 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1579 * @param htim: TIM handle
1580 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1581 * This parameter can be one of the following values:
1582 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1583 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1584 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1585 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1586 * @arg TIM_TS_NONE: No trigger is needed
1587 * @param CommutationSource : the Commutation Event source
1588 * This parameter can be one of the following values:
1589 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1590 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1591 * @retval HAL status
1593 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1595 /* Check the parameters */
1596 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1597 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1601 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1602 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1604 /* Select the Input trigger */
1605 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1606 htim->Instance->SMCR |= InputTrigger;
1609 /* Select the Capture Compare preload feature */
1610 htim->Instance->CR2 |= TIM_CR2_CCPC;
1611 /* Select the Commutation event source */
1612 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1613 htim->Instance->CR2 |= CommutationSource;
1621 * @brief Configure the TIM commutation event sequence with interrupt.
1622 * @note: this function is mandatory to use the commutation event in order to
1623 * update the configuration at each commutation detection on the TRGI input of the Timer,
1624 * the typical use of this feature is with the use of another Timer(interface Timer)
1625 * configured in Hall sensor interface, this interface Timer will generate the
1626 * commutation at its TRGO output (connected to Timer used in this function) each time
1627 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1628 * @param htim: TIM handle
1629 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1630 * This parameter can be one of the following values:
1631 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1632 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1633 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1634 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1635 * @arg TIM_TS_NONE: No trigger is needed
1636 * @param CommutationSource : the Commutation Event source
1637 * This parameter can be one of the following values:
1638 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1639 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1640 * @retval HAL status
1642 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1644 /* Check the parameters */
1645 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1646 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1650 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1651 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1653 /* Select the Input trigger */
1654 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1655 htim->Instance->SMCR |= InputTrigger;
1658 /* Select the Capture Compare preload feature */
1659 htim->Instance->CR2 |= TIM_CR2_CCPC;
1660 /* Select the Commutation event source */
1661 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1662 htim->Instance->CR2 |= CommutationSource;
1664 /* Enable the Commutation Interrupt Request */
1665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
1673 * @brief Configure the TIM commutation event sequence with DMA.
1674 * @note: this function is mandatory to use the commutation event in order to
1675 * update the configuration at each commutation detection on the TRGI input of the Timer,
1676 * the typical use of this feature is with the use of another Timer(interface Timer)
1677 * configured in Hall sensor interface, this interface Timer will generate the
1678 * commutation at its TRGO output (connected to Timer used in this function) each time
1679 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1680 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
1681 * @param htim: TIM handle
1682 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1683 * This parameter can be one of the following values:
1684 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1685 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1686 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1687 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1688 * @arg TIM_TS_NONE: No trigger is needed
1689 * @param CommutationSource : the Commutation Event source
1690 * This parameter can be one of the following values:
1691 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1692 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1693 * @retval HAL status
1695 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1697 /* Check the parameters */
1698 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1699 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1703 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1704 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1706 /* Select the Input trigger */
1707 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1708 htim->Instance->SMCR |= InputTrigger;
1711 /* Select the Capture Compare preload feature */
1712 htim->Instance->CR2 |= TIM_CR2_CCPC;
1713 /* Select the Commutation event source */
1714 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1715 htim->Instance->CR2 |= CommutationSource;
1717 /* Enable the Commutation DMA Request */
1718 /* Set the DMA Commutation Callback */
1719 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
1720 /* Set the DMA error callback */
1721 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
1723 /* Enable the Commutation DMA Request */
1724 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
1732 * @brief Initializes the TIM Output Compare Channels according to the specified
1733 * parameters in the TIM_OC_InitTypeDef.
1734 * @param htim: TIM Output Compare handle
1735 * @param sConfig: TIM Output Compare configuration structure
1736 * @param Channel : TIM Channels to configure
1737 * This parameter can be one of the following values:
1738 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1739 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1740 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1741 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1742 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1743 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1744 * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
1745 * @retval HAL status
1747 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
1748 TIM_OC_InitTypeDef* sConfig,
1751 /* Check the parameters */
1752 assert_param(IS_TIM_CHANNELS(Channel));
1753 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
1754 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
1755 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
1756 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
1757 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
1759 /* Check input state */
1762 htim->State = HAL_TIM_STATE_BUSY;
1768 /* Check the parameters */
1769 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
1771 /* Configure the TIM Channel 1 in Output Compare */
1772 TIM_OC1_SetConfig(htim->Instance, sConfig);
1778 /* Check the parameters */
1779 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1781 /* Configure the TIM Channel 2 in Output Compare */
1782 TIM_OC2_SetConfig(htim->Instance, sConfig);
1788 /* Check the parameters */
1789 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
1791 /* Configure the TIM Channel 3 in Output Compare */
1792 TIM_OC3_SetConfig(htim->Instance, sConfig);
1798 /* Check the parameters */
1799 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
1801 /* Configure the TIM Channel 4 in Output Compare */
1802 TIM_OC4_SetConfig(htim->Instance, sConfig);
1808 /* Check the parameters */
1809 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
1811 /* Configure the TIM Channel 5 in Output Compare */
1812 TIM_OC5_SetConfig(htim->Instance, sConfig);
1818 /* Check the parameters */
1819 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
1821 /* Configure the TIM Channel 6 in Output Compare */
1822 TIM_OC6_SetConfig(htim->Instance, sConfig);
1830 htim->State = HAL_TIM_STATE_READY;
1838 * @brief Initializes the TIM PWM channels according to the specified
1839 * parameters in the TIM_OC_InitTypeDef.
1840 * @param htim: TIM PWM handle
1841 * @param sConfig: TIM PWM configuration structure
1842 * @param Channel : TIM Channels to be configured
1843 * This parameter can be one of the following values:
1844 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1845 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1846 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1847 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1848 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1849 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1850 * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
1851 * @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 PWM channels can
1853 * @retval HAL status
1855 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
1856 TIM_OC_InitTypeDef* sConfig,
1859 /* Check the parameters */
1860 assert_param(IS_TIM_CHANNELS(Channel));
1861 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
1862 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
1863 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
1864 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
1865 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
1866 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
1868 /* Check input state */
1871 htim->State = HAL_TIM_STATE_BUSY;
1877 /* Check the parameters */
1878 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
1880 /* Configure the Channel 1 in PWM mode */
1881 TIM_OC1_SetConfig(htim->Instance, sConfig);
1883 /* Set the Preload enable bit for channel1 */
1884 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
1886 /* Configure the Output Fast mode */
1887 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
1888 htim->Instance->CCMR1 |= sConfig->OCFastMode;
1894 /* Check the parameters */
1895 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1897 /* Configure the Channel 2 in PWM mode */
1898 TIM_OC2_SetConfig(htim->Instance, sConfig);
1900 /* Set the Preload enable bit for channel2 */
1901 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
1903 /* Configure the Output Fast mode */
1904 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
1905 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
1911 /* Check the parameters */
1912 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
1914 /* Configure the Channel 3 in PWM mode */
1915 TIM_OC3_SetConfig(htim->Instance, sConfig);
1917 /* Set the Preload enable bit for channel3 */
1918 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
1920 /* Configure the Output Fast mode */
1921 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
1922 htim->Instance->CCMR2 |= sConfig->OCFastMode;
1928 /* Check the parameters */
1929 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
1931 /* Configure the Channel 4 in PWM mode */
1932 TIM_OC4_SetConfig(htim->Instance, sConfig);
1934 /* Set the Preload enable bit for channel4 */
1935 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
1937 /* Configure the Output Fast mode */
1938 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
1939 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
1945 /* Check the parameters */
1946 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
1948 /* Configure the Channel 5 in PWM mode */
1949 TIM_OC5_SetConfig(htim->Instance, sConfig);
1951 /* Set the Preload enable bit for channel5*/
1952 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
1954 /* Configure the Output Fast mode */
1955 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
1956 htim->Instance->CCMR3 |= sConfig->OCFastMode;
1962 /* Check the parameters */
1963 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
1965 /* Configure the Channel 5 in PWM mode */
1966 TIM_OC6_SetConfig(htim->Instance, sConfig);
1968 /* Set the Preload enable bit for channel6 */
1969 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
1971 /* Configure the Output Fast mode */
1972 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
1973 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
1981 htim->State = HAL_TIM_STATE_READY;
1989 * @brief Configures the OCRef clear feature
1990 * @param htim: TIM handle
1991 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
1992 * contains the OCREF clear feature and parameters for the TIM peripheral.
1993 * @param Channel: specifies the TIM Channel
1994 * This parameter can be one of the following values:
1995 * @arg TIM_Channel_1: TIM Channel 1
1996 * @arg TIM_Channel_2: TIM Channel 2
1997 * @arg TIM_Channel_3: TIM Channel 3
1998 * @arg TIM_Channel_4: TIM Channel 4
1999 * @arg TIM_Channel_5: TIM Channel 5
2000 * @arg TIM_Channel_6: TIM Channel 6
2001 * @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 OC channels can
2005 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
2006 TIM_ClearInputConfigTypeDef *sClearInputConfig,
2009 uint32_t tmpsmcr = 0;
2011 /* Check the parameters */
2012 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
2013 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
2015 /* Check input state */
2018 switch (sClearInputConfig->ClearInputSource)
2020 case TIM_CLEARINPUTSOURCE_NONE:
2022 /* Clear the OCREF clear selection bit */
2023 tmpsmcr &= ~TIM_SMCR_OCCS;
2025 /* Clear the ETR Bits */
2026 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
2029 htim->Instance->SMCR = tmpsmcr;
2033 case TIM_CLEARINPUTSOURCE_OCREFCLR:
2035 /* Clear the OCREF clear selection bit */
2036 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
2040 case TIM_CLEARINPUTSOURCE_ETR:
2042 /* Check the parameters */
2043 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
2044 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
2045 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
2047 TIM_ETR_SetConfig(htim->Instance,
2048 sClearInputConfig->ClearInputPrescaler,
2049 sClearInputConfig->ClearInputPolarity,
2050 sClearInputConfig->ClearInputFilter);
2052 /* Set the OCREF clear selection bit */
2053 htim->Instance->SMCR |= TIM_SMCR_OCCS;
2062 if(sClearInputConfig->ClearInputState != RESET)
2064 /* Enable the Ocref clear feature for Channel 1 */
2065 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
2069 /* Disable the Ocref clear feature for Channel 1 */
2070 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
2076 if(sClearInputConfig->ClearInputState != RESET)
2078 /* Enable the Ocref clear feature for Channel 2 */
2079 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
2083 /* Disable the Ocref clear feature for Channel 2 */
2084 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
2090 if(sClearInputConfig->ClearInputState != RESET)
2092 /* Enable the Ocref clear feature for Channel 3 */
2093 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
2097 /* Disable the Ocref clear feature for Channel 3 */
2098 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
2104 if(sClearInputConfig->ClearInputState != RESET)
2106 /* Enable the Ocref clear feature for Channel 4 */
2107 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
2111 /* Disable the Ocref clear feature for Channel 4 */
2112 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
2118 if(sClearInputConfig->ClearInputState != RESET)
2120 /* Enable the Ocref clear feature for Channel 1 */
2121 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
2125 /* Disable the Ocref clear feature for Channel 1 */
2126 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
2132 if(sClearInputConfig->ClearInputState != RESET)
2134 /* Enable the Ocref clear feature for Channel 1 */
2135 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
2139 /* Disable the Ocref clear feature for Channel 1 */
2140 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
2154 * @brief Configures the TIM in master mode.
2155 * @param htim: TIM handle.
2156 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
2157 * contains the selected trigger output (TRGO) and the Master/Slave
2159 * @retval HAL status
2161 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2162 TIM_MasterConfigTypeDef * sMasterConfig)
2167 /* Check the parameters */
2168 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
2169 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2170 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2172 /* Check input state */
2175 /* Get the TIMx CR2 register value */
2176 tmpcr2 = htim->Instance->CR2;
2178 /* Get the TIMx SMCR register value */
2179 tmpsmcr = htim->Instance->SMCR;
2181 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2182 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2184 /* Check the parameters */
2185 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2187 /* Clear the MMS2 bits */
2188 tmpcr2 &= ~TIM_CR2_MMS2;
2189 /* Select the TRGO2 source*/
2190 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2193 /* Reset the MMS Bits */
2194 tmpcr2 &= ~TIM_CR2_MMS;
2195 /* Select the TRGO source */
2196 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2198 /* Reset the MSM Bit */
2199 tmpsmcr &= ~TIM_SMCR_MSM;
2200 /* Set master mode */
2201 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2203 /* Update TIMx CR2 */
2204 htim->Instance->CR2 = tmpcr2;
2206 /* Update TIMx SMCR */
2207 htim->Instance->SMCR = tmpsmcr;
2213 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2214 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2215 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2216 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2218 #if defined(STM32F373xC) || defined(STM32F378xx)
2220 * @brief Configures the TIM in master mode.
2221 * @param htim: TIM handle.
2222 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
2223 * contains the selected trigger output (TRGO) and the Master/Slave
2225 * @retval HAL status
2227 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
2229 /* Check the parameters */
2230 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2231 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2232 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2236 htim->State = HAL_TIM_STATE_BUSY;
2238 /* Reset the MMS Bits */
2239 htim->Instance->CR2 &= ~TIM_CR2_MMS;
2240 /* Select the TRGO source */
2241 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
2243 /* Reset the MSM Bit */
2244 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
2245 /* Set or Reset the MSM Bit */
2246 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
2248 htim->State = HAL_TIM_STATE_READY;
2254 #endif /* STM32F373xC || STM32F378xx */
2256 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2257 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2258 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2259 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2261 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2262 * and the AOE(automatic output enable).
2263 * @param htim: TIM handle
2264 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2265 * contains the BDTR Register configuration information for the TIM peripheral.
2266 * @note For STM32F302xC, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx and STM32F303x8 two break inputs can be configured.
2267 * @retval HAL status
2269 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2270 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
2272 uint32_t tmpbdtr = 0;
2274 /* Check the parameters */
2275 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2276 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2277 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2278 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2279 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2280 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2281 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2282 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2283 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2285 /* Check input state */
2288 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2289 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2290 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2292 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2293 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2294 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2296 /* Clear the BDTR bits */
2297 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
2298 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
2299 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
2300 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
2302 /* Set the BDTR bits */
2303 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
2304 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
2305 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
2306 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
2307 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
2308 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
2309 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
2310 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
2311 tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
2312 tmpbdtr |= sBreakDeadTimeConfig->Break2State;
2313 tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
2317 /* Clear the BDTR bits */
2318 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
2319 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
2320 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
2322 /* Set the BDTR bits */
2323 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
2324 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
2325 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
2326 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
2327 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
2328 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
2329 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
2330 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
2334 htim->Instance->BDTR = tmpbdtr;
2340 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2341 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2342 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2343 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2345 #if defined(STM32F373xC) || defined(STM32F378xx)
2347 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2348 * and the AOE(automatic output enable).
2349 * @param htim: TIM handle
2350 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2351 * contains the BDTR Register configuration information for the TIM peripheral.
2352 * @retval HAL status
2354 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2355 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2357 /* Check the parameters */
2358 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2359 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2360 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2361 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2362 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2363 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2364 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2365 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2367 /* Process Locked */
2370 htim->State = HAL_TIM_STATE_BUSY;
2372 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2373 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2374 htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
2375 sBreakDeadTimeConfig->OffStateIDLEMode |
2376 sBreakDeadTimeConfig->LockLevel |
2377 sBreakDeadTimeConfig->DeadTime |
2378 sBreakDeadTimeConfig->BreakState |
2379 sBreakDeadTimeConfig->BreakPolarity |
2380 sBreakDeadTimeConfig->AutomaticOutput;
2383 htim->State = HAL_TIM_STATE_READY;
2389 #endif /* STM32F373xC || STM32F378xx */
2391 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2392 defined(STM32F303xC) || defined(STM32F358xx)
2393 #if defined(STM32F303xE) || defined(STM32F398xx)
2395 * @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
2396 * @param htim: TIM handle.
2397 * @param Remap1: specifies the first TIM remapping source.
2398 * This parameter can be one of the following values:
2399 * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
2400 * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2401 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2402 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2403 * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
2404 * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
2405 * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
2406 * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
2407 * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
2408 * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
2409 * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
2410 * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
2411 * @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
2412 * @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
2413 * @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
2414 * @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
2415 * @param Remap2: specifies the second TIMremapping source (if any).
2416 * This parameter can be one of the following values:
2417 * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
2418 * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
2419 * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
2420 * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
2421 * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
2422 * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
2423 * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
2424 * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
2425 * @arg TIM_TIM16_NONE: Non significant value for TIM16
2426 * @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
2427 * @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
2428 * @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
2429 * @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
2430 * @retval HAL status
2432 #else /* STM32F303xC || STM32F358xx */
2434 * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
2435 * @param htim: TIM handle.
2436 * @param Remap1: specifies the first TIM remapping source.
2437 * This parameter can be one of the following values:
2438 * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
2439 * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2440 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2441 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2442 * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
2443 * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
2444 * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
2445 * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
2446 * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
2447 * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
2448 * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
2449 * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
2450 * @param Remap2: specifies the second TIMremapping source (if any).
2451 * This parameter can be one of the following values:
2452 * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
2453 * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
2454 * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
2455 * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
2456 * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
2457 * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
2458 * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
2459 * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
2460 * @retval HAL status
2462 #endif /* STM32F303xE || STM32F398xx || */
2463 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
2467 /* Check parameters */
2468 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2469 assert_param(IS_TIM_REMAP(Remap1));
2470 assert_param(IS_TIM_REMAP2(Remap2));
2472 /* Set the Timer remapping configuration */
2473 htim->Instance->OR = Remap1 | Remap2;
2475 htim->State = HAL_TIM_STATE_READY;
2481 #endif /* STM32F303xE || STM32F398xx || */
2482 /* STM32F303xC || STM32F358xx || */
2485 #if defined(STM32F302xE) || \
2486 defined(STM32F302xC) || \
2487 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2488 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
2489 defined(STM32F373xC) || defined(STM32F378xx)
2490 #if defined(STM32F302xE) || \
2491 defined(STM32F302xC) || \
2492 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2493 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2495 * @brief Configures the TIM1 and TIM16 Remapping input capabilities.
2496 * @param htim: TIM handle.
2497 * @param Remap: specifies the TIM remapping source.
2498 * This parameter can be one of the following values:
2499 * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
2500 * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2501 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2502 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2503 * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
2504 * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
2505 * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
2506 * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
2507 * @retval HAL status
2509 #else /* STM32F373xC || STM32F378xx */
2511 * @brief Configures the TIM2 and TIM14 Remapping input capabilities.
2512 * @param htim: TIM handle.
2513 * @param Remap: specifies the TIM remapping source.
2514 * This parameter can be one of the following values:
2515 * STM32F373xC, STM32F378xx:
2516 * @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
2517 * @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
2518 * @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
2519 * @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
2520 * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
2521 * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
2522 * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
2523 * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
2524 * @retval HAL status
2526 #endif /* STM32F302xE || */
2527 /* STM32F302xC || */
2528 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2529 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
2530 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2534 /* Check parameters */
2535 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2536 assert_param(IS_TIM_REMAP(Remap));
2538 /* Set the Timer remapping configuration */
2539 htim->Instance->OR = Remap;
2541 htim->State = HAL_TIM_STATE_READY;
2547 #endif /* STM32F302xE || */
2548 /* STM32F302xC || */
2549 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2550 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
2551 /* STM32F373xC || STM32F378xx */
2554 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2555 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2556 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2557 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2559 * @brief Group channel 5 and channel 1, 2 or 3
2560 * @param htim: TIM handle.
2561 * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
2562 * This parameter can be any combination of the following values:
2563 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2564 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2565 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2566 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2567 * @retval HAL status
2569 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
2571 /* Check parameters */
2572 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2573 assert_param(IS_TIM_GROUPCH5(OCRef));
2575 /* Process Locked */
2578 htim->State = HAL_TIM_STATE_BUSY;
2580 /* Clear GC5Cx bit fields */
2581 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
2583 /* Set GC5Cx bit fields */
2584 htim->Instance->CCR5 |= OCRef;
2586 htim->State = HAL_TIM_STATE_READY;
2592 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2593 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2594 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2595 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2601 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2602 * @brief Extended Callbacks functions
2605 ==============================================================================
2606 ##### Extended Callbacks functions #####
2607 ==============================================================================
2609 This section provides Extended TIM callback functions:
2610 (+) Timer Commutation callback
2611 (+) Timer Break callback
2618 * @brief Hall commutation changed callback in non blocking mode
2619 * @param htim : TIM handle
2622 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
2624 /* NOTE : This function Should not be modified, when the callback is needed,
2625 the HAL_TIMEx_CommutationCallback could be implemented in the user file
2630 * @brief Hall Break detection callback in non blocking mode
2631 * @param htim : TIM handle
2634 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
2636 /* NOTE : This function Should not be modified, when the callback is needed,
2637 the HAL_TIMEx_BreakCallback could be implemented in the user file
2645 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
2646 * @brief Extended Peripheral State functions
2649 ==============================================================================
2650 ##### Extended Peripheral State functions #####
2651 ==============================================================================
2653 This subsection permit to get in run-time the status of the peripheral
2661 * @brief Return the TIM Hall Sensor interface state
2662 * @param htim: TIM Hall Sensor handle
2665 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
2675 * @brief TIM DMA Commutation callback.
2676 * @param hdma : pointer to DMA handle.
2679 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
2681 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2683 htim->State= HAL_TIM_STATE_READY;
2685 HAL_TIMEx_CommutationCallback(htim);
2689 * @brief Enables or disables the TIM Capture Compare Channel xN.
2690 * @param TIMx to select the TIM peripheral
2691 * @param Channel: specifies the TIM Channel
2692 * This parameter can be one of the following values:
2693 * @arg TIM_Channel_1: TIM Channel 1
2694 * @arg TIM_Channel_2: TIM Channel 2
2695 * @arg TIM_Channel_3: TIM Channel 3
2696 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
2697 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
2700 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
2704 tmp = TIM_CCER_CC1NE << Channel;
2706 /* Reset the CCxNE Bit */
2709 /* Set or reset the CCxNE Bit */
2710 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
2717 #endif /* HAL_TIM_MODULE_ENABLED */
2726 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/