2 ******************************************************************************
3 * @file stm32f3xx_ll_fmc.c
4 * @author MCD Application Team
7 * @brief FMC Low Layer HAL module driver.
9 * This file provides firmware functions to manage the following
10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
11 * + Initialization/de-initialization functions
12 * + Peripheral Control functions
13 * + Peripheral State functions
16 ==============================================================================
17 ##### FMC peripheral features #####
18 ==============================================================================
19 [..] The Flexible memory controller (FMC) includes three memory controllers:
20 (+) The NOR/PSRAM memory controller
21 (+) The NAND/PC Card memory controller
23 [..] The FMC functional block makes the interface with synchronous and asynchronous static
24 memories, and 16-bit PC memory cards. Its main purposes are:
25 (+) to translate AHB transactions into the appropriate external device protocol
26 (+) to meet the access time requirements of the external memory devices
28 [..] All external memories share the addresses, data and control signals with the controller.
29 Each external device is accessed by means of a unique Chip Select. The FMC performs
30 only one access at a time to an external device.
31 The main features of the FMC controller are the following:
32 (+) Interface with static-memory mapped devices including:
33 (++) Static random access memory (SRAM)
34 (++) Read-only memory (ROM)
35 (++) NOR Flash memory/OneNAND Flash memory
36 (++) PSRAM (4 memory banks)
37 (++) 16-bit PC Card compatible devices
38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
40 (+) Independent Chip Select control for each memory bank
41 (+) Independent configuration for each memory bank
44 ******************************************************************************
47 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
49 * Redistribution and use in source and binary forms, with or without modification,
50 * are permitted provided that the following conditions are met:
51 * 1. Redistributions of source code must retain the above copyright notice,
52 * this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright notice,
54 * this list of conditions and the following disclaimer in the documentation
55 * and/or other materials provided with the distribution.
56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
57 * may be used to endorse or promote products derived from this software
58 * without specific prior written permission.
60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
71 ******************************************************************************
74 /* Includes ------------------------------------------------------------------*/
75 #include "stm32f3xx_hal.h"
77 /** @addtogroup STM32F3xx_HAL_Driver
82 * @brief FMC driver modules
86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
88 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
90 /* Private typedef -----------------------------------------------------------*/
91 /* Private define ------------------------------------------------------------*/
92 /* Private macro -------------------------------------------------------------*/
93 /* Private variables ---------------------------------------------------------*/
94 /* Private function prototypes -----------------------------------------------*/
95 /* Private functions ---------------------------------------------------------*/
97 /** @defgroup FMC_Private_Functions
101 /** @defgroup FMC_NORSRAM Controller functions
102 * @brief NORSRAM Controller functions
105 ==============================================================================
106 ##### How to use NORSRAM device driver #####
107 ==============================================================================
110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
111 to run the NORSRAM external devices.
113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
116 (+) FMC NORSRAM bank extended timing configuration using the function
117 FMC_NORSRAM_Extended_Timing_Init()
118 (+) FMC NORSRAM bank enable/disable write operation using the functions
119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
126 /** @defgroup FMC_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
127 * @brief Initialization and Configuration functions
130 ==============================================================================
131 ##### Initialization and de_initialization functions #####
132 ==============================================================================
134 This section provides functions allowing to:
135 (+) Initialize and configure the FMC NORSRAM interface
136 (+) De-initialize the FMC NORSRAM interface
137 (+) Configure the FMC clock and associated GPIOs
144 * @brief Initialize the FMC_NORSRAM device according to the specified
145 * control parameters in the FMC_NORSRAM_InitTypeDef
146 * @param Device: Pointer to NORSRAM device instance
147 * @param Init: Pointer to NORSRAM Initialization structure
150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
154 /* Check the parameters */
155 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
157 assert_param(IS_FMC_MUX(Init->DataAddressMux));
158 assert_param(IS_FMC_MEMORY(Init->MemoryType));
159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
162 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
163 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
164 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
165 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
166 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
167 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
168 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
169 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
171 /* Set NORSRAM device control parameters */
172 tmpr = (uint32_t)(Init->DataAddressMux |\
174 Init->MemoryDataWidth |\
175 Init->BurstAccessMode |\
176 Init->WaitSignalPolarity |\
178 Init->WaitSignalActive |\
179 Init->WriteOperation |\
181 Init->ExtendedMode |\
182 Init->AsynchronousWait |\
184 Init->ContinuousClock
187 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
189 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
192 Device->BTCR[Init->NSBank] = tmpr;
194 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
195 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
197 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
198 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
199 Init->ContinuousClock);
207 * @brief DeInitialize the FMC_NORSRAM peripheral
208 * @param Device: Pointer to NORSRAM device instance
209 * @param ExDevice: Pointer to NORSRAM extended mode device instance
210 * @param Bank: NORSRAM bank number
213 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
215 /* Check the parameters */
216 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
217 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
218 assert_param(IS_FMC_NORSRAM_BANK(Bank));
220 /* Disable the FMC_NORSRAM device */
221 __FMC_NORSRAM_DISABLE(Device, Bank);
223 /* De-initialize the FMC_NORSRAM device */
224 /* FMC_NORSRAM_BANK1 */
225 if(Bank == FMC_NORSRAM_BANK1)
227 Device->BTCR[Bank] = 0x000030DB;
229 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
232 Device->BTCR[Bank] = 0x000030D2;
235 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
236 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
243 * @brief Initialize the FMC_NORSRAM Timing according to the specified
244 * parameters in the FMC_NORSRAM_TimingTypeDef
245 * @param Device: Pointer to NORSRAM device instance
246 * @param Timing: Pointer to NORSRAM Timing structure
247 * @param Bank: NORSRAM bank number
250 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
254 /* Check the parameters */
255 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
256 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
257 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
258 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
259 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
260 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
261 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
262 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
263 assert_param(IS_FMC_NORSRAM_BANK(Bank));
265 /* Set FMC_NORSRAM device timing parameters */
266 tmpr = (uint32_t)(Timing->AddressSetupTime |\
267 ((Timing->AddressHoldTime) << 4) |\
268 ((Timing->DataSetupTime) << 8) |\
269 ((Timing->BusTurnAroundDuration) << 16) |\
270 (((Timing->CLKDivision)-1) << 20) |\
271 (((Timing->DataLatency)-2) << 24) |\
275 Device->BTCR[Bank + 1] = tmpr;
277 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
278 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
280 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
281 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
282 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
289 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
290 * parameters in the FMC_NORSRAM_TimingTypeDef
291 * @param Device: Pointer to NORSRAM device instance
292 * @param Timing: Pointer to NORSRAM Timing structure
293 * @param Bank: NORSRAM bank number
296 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
298 /* Check the parameters */
299 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
301 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
302 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
304 /* Check the parameters */
305 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
306 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
307 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
308 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
309 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
310 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
311 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
312 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
313 assert_param(IS_FMC_NORSRAM_BANK(Bank));
315 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
316 ((Timing->AddressHoldTime) << 4) |\
317 ((Timing->DataSetupTime) << 8) |\
318 ((Timing->BusTurnAroundDuration) << 16) |\
319 (((Timing->CLKDivision)-1) << 20) |\
320 (((Timing->DataLatency)-2) << 24) |\
321 (Timing->AccessMode));
325 Device->BWTR[Bank] = 0x0FFFFFFF;
337 /** @defgroup FMC_NORSRAM_Exported_Functions_Group3 Peripheral Control functions
338 * @brief management functions
341 ==============================================================================
342 ##### FMC_NORSRAM Control functions #####
343 ==============================================================================
345 This subsection provides a set of functions allowing to control dynamically
346 the FMC NORSRAM interface.
353 * @brief Enables dynamically FMC_NORSRAM write operation.
354 * @param Device: Pointer to NORSRAM device instance
355 * @param Bank: NORSRAM bank number
358 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
360 /* Check the parameters */
361 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
362 assert_param(IS_FMC_NORSRAM_BANK(Bank));
364 /* Enable write operation */
365 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
371 * @brief Disables dynamically FMC_NORSRAM write operation.
372 * @param Device: Pointer to NORSRAM device instance
373 * @param Bank: NORSRAM bank number
376 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
378 /* Check the parameters */
379 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
380 assert_param(IS_FMC_NORSRAM_BANK(Bank));
382 /* Disable write operation */
383 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
396 /** @defgroup FMC_NAND Controller functions
397 * @brief NAND Controller functions
400 ==============================================================================
401 ##### How to use NAND device driver #####
402 ==============================================================================
404 This driver contains a set of APIs to interface with the FMC NAND banks in order
405 to run the NAND external devices.
407 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
408 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
409 (+) FMC NAND bank common space timing configuration using the function
410 FMC_NAND_CommonSpace_Timing_Init()
411 (+) FMC NAND bank attribute space timing configuration using the function
412 FMC_NAND_AttributeSpace_Timing_Init()
413 (+) FMC NAND bank enable/disable ECC correction feature using the functions
414 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
415 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
421 /** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
422 * @brief Initialization and Configuration functions
425 ==============================================================================
426 ##### Initialization and de_initialization functions #####
427 ==============================================================================
429 This section provides functions allowing to:
430 (+) Initialize and configure the FMC NAND interface
431 (+) De-initialize the FMC NAND interface
432 (+) Configure the FMC clock and associated GPIOs
439 * @brief Initializes the FMC_NAND device according to the specified
440 * control parameters in the FMC_NAND_HandleTypeDef
441 * @param Device: Pointer to NAND device instance
442 * @param Init: Pointer to NAND Initialization structure
445 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
449 /* Check the parameters */
450 assert_param(IS_FMC_NAND_DEVICE(Device));
451 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
452 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
453 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
454 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
455 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
456 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
457 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
459 /* Set NAND device control parameters */
460 tmppcr = (uint32_t)(Init->Waitfeature |\
461 FMC_PCR_MEMORY_TYPE_NAND |\
462 Init->MemoryDataWidth |\
463 Init->EccComputation |\
465 ((Init->TCLRSetupTime) << 9) |\
466 ((Init->TARSetupTime) << 13)
469 if(Init->NandBank == FMC_NAND_BANK2)
471 /* NAND bank 2 registers configuration */
472 Device->PCR2 = tmppcr;
476 /* NAND bank 3 registers configuration */
477 Device->PCR3 = tmppcr;
485 * @brief Initializes the FMC_NAND Common space Timing according to the specified
486 * parameters in the FMC_NAND_PCC_TimingTypeDef
487 * @param Device: Pointer to NAND device instance
488 * @param Timing: Pointer to NAND timing structure
489 * @param Bank: NAND bank number
492 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
494 uint32_t tmppmem = 0;
496 /* Check the parameters */
497 assert_param(IS_FMC_NAND_DEVICE(Device));
498 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
499 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
500 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
501 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
502 assert_param(IS_FMC_NAND_BANK(Bank));
504 /* Set FMC_NAND device timing parameters */
505 tmppmem = (uint32_t)(Timing->SetupTime |\
506 ((Timing->WaitSetupTime) << 8) |\
507 ((Timing->HoldSetupTime) << 16) |\
508 ((Timing->HiZSetupTime) << 24)
511 if(Bank == FMC_NAND_BANK2)
513 /* NAND bank 2 registers configuration */
514 Device->PMEM2 = tmppmem;
518 /* NAND bank 3 registers configuration */
519 Device->PMEM3 = tmppmem;
526 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
527 * parameters in the FMC_NAND_PCC_TimingTypeDef
528 * @param Device: Pointer to NAND device instance
529 * @param Timing: Pointer to NAND timing structure
530 * @param Bank: NAND bank number
533 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
535 uint32_t tmppatt = 0;
537 /* Check the parameters */
538 assert_param(IS_FMC_NAND_DEVICE(Device));
539 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
540 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
541 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
542 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
543 assert_param(IS_FMC_NAND_BANK(Bank));
545 /* Set FMC_NAND device timing parameters */
546 tmppatt = (uint32_t)(Timing->SetupTime |\
547 ((Timing->WaitSetupTime) << 8) |\
548 ((Timing->HoldSetupTime) << 16) |\
549 ((Timing->HiZSetupTime) << 24)
552 if(Bank == FMC_NAND_BANK2)
554 /* NAND bank 2 registers configuration */
555 Device->PATT2 = tmppatt;
559 /* NAND bank 3 registers configuration */
560 Device->PATT3 = tmppatt;
568 * @brief DeInitializes the FMC_NAND device
569 * @param Device: Pointer to NAND device instance
570 * @param Bank: NAND bank number
573 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
575 /* Check the parameters */
576 assert_param(IS_FMC_NAND_DEVICE(Device));
577 assert_param(IS_FMC_NAND_BANK(Bank));
579 /* Disable the NAND Bank */
580 __FMC_NAND_DISABLE(Device, Bank);
582 /* De-initialize the NAND Bank */
583 if(Bank == FMC_NAND_BANK2)
585 /* Set the FMC_NAND_BANK2 registers to their reset values */
586 Device->PCR2 = 0x00000018;
587 Device->SR2 = 0x00000040;
588 Device->PMEM2 = 0xFCFCFCFC;
589 Device->PATT2 = 0xFCFCFCFC;
594 /* Set the FMC_NAND_BANK3 registers to their reset values */
595 Device->PCR3 = 0x00000018;
596 Device->SR3 = 0x00000040;
597 Device->PMEM3 = 0xFCFCFCFC;
598 Device->PATT3 = 0xFCFCFCFC;
609 /** @defgroup FMC_NAND_Exported_Functions_Group3 Peripheral Control functions
610 * @brief management functions
613 ==============================================================================
614 ##### FMC_NAND Control functions #####
615 ==============================================================================
617 This subsection provides a set of functions allowing to control dynamically
618 the FMC NAND interface.
626 * @brief Enables dynamically FMC_NAND ECC feature.
627 * @param Device: Pointer to NAND device instance
628 * @param Bank: NAND bank number
631 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
633 /* Check the parameters */
634 assert_param(IS_FMC_NAND_DEVICE(Device));
635 assert_param(IS_FMC_NAND_BANK(Bank));
637 /* Enable ECC feature */
638 if(Bank == FMC_NAND_BANK2)
640 Device->PCR2 |= FMC_PCR2_ECCEN;
644 Device->PCR3 |= FMC_PCR3_ECCEN;
652 * @brief Disables dynamically FMC_NAND ECC feature.
653 * @param Device: Pointer to NAND device instance
654 * @param Bank: NAND bank number
657 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
659 /* Check the parameters */
660 assert_param(IS_FMC_NAND_DEVICE(Device));
661 assert_param(IS_FMC_NAND_BANK(Bank));
663 /* Disable ECC feature */
664 if(Bank == FMC_NAND_BANK2)
666 Device->PCR2 &= ~FMC_PCR2_ECCEN;
670 Device->PCR3 &= ~FMC_PCR3_ECCEN;
677 * @brief Disables dynamically FMC_NAND ECC feature.
678 * @param Device: Pointer to NAND device instance
679 * @param ECCval: Pointer to ECC value
680 * @param Bank: NAND bank number
681 * @param Timeout: Timeout wait value
684 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
686 uint32_t timeout = 0;
688 /* Check the parameters */
689 assert_param(IS_FMC_NAND_DEVICE(Device));
690 assert_param(IS_FMC_NAND_BANK(Bank));
692 timeout = HAL_GetTick() + Timeout;
694 /* Wait untill FIFO is empty */
695 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
697 /* Check for the Timeout */
698 if(Timeout != HAL_MAX_DELAY)
700 if(HAL_GetTick() >= timeout)
707 if(Bank == FMC_NAND_BANK2)
709 /* Get the ECCR2 register value */
710 *ECCval = (uint32_t)Device->ECCR2;
714 /* Get the ECCR3 register value */
715 *ECCval = (uint32_t)Device->ECCR3;
729 /** @defgroup FMC_PCCARD Controller functions
730 * @brief PCCARD Controller functions
733 ==============================================================================
734 ##### How to use PCCARD device driver #####
735 ==============================================================================
737 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
738 to run the PCCARD/compact flash external devices.
740 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
741 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
742 (+) FMC PCCARD bank common space timing configuration using the function
743 FMC_PCCARD_CommonSpace_Timing_Init()
744 (+) FMC PCCARD bank attribute space timing configuration using the function
745 FMC_PCCARD_AttributeSpace_Timing_Init()
746 (+) FMC PCCARD bank IO space timing configuration using the function
747 FMC_PCCARD_IOSpace_Timing_Init()
754 /** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
755 * @brief Initialization and Configuration functions
758 ==============================================================================
759 ##### Initialization and de_initialization functions #####
760 ==============================================================================
762 This section provides functions allowing to:
763 (+) Initialize and configure the FMC PCCARD interface
764 (+) De-initialize the FMC PCCARD interface
765 (+) Configure the FMC clock and associated GPIOs
772 * @brief Initializes the FMC_PCCARD device according to the specified
773 * control parameters in the FMC_PCCARD_HandleTypeDef
774 * @param Device: Pointer to PCCARD device instance
775 * @param Init: Pointer to PCCARD Initialization structure
778 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
780 /* Check the parameters */
781 assert_param(IS_FMC_PCCARD_DEVICE(Device));
782 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
783 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
784 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
786 /* Set FMC_PCCARD device control parameters */
787 Device->PCR4 = (uint32_t)(Init->Waitfeature |\
788 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
789 (Init->TCLRSetupTime << 9) |\
790 (Init->TARSetupTime << 13));
797 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
798 * parameters in the FMC_NAND_PCC_TimingTypeDef
799 * @param Device: Pointer to PCCARD device instance
800 * @param Timing: Pointer to PCCARD timing structure
803 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
805 /* Check the parameters */
806 assert_param(IS_FMC_PCCARD_DEVICE(Device));
807 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
808 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
809 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
810 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
812 /* Set PCCARD timing parameters */
813 Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
814 ((Timing->WaitSetupTime) << 8) |\
815 (Timing->HoldSetupTime) << 16) |\
816 ((Timing->HiZSetupTime) << 24)
823 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
824 * parameters in the FMC_NAND_PCC_TimingTypeDef
825 * @param Device: Pointer to PCCARD device instance
826 * @param Timing: Pointer to PCCARD timing structure
829 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
831 /* Check the parameters */
832 assert_param(IS_FMC_PCCARD_DEVICE(Device));
833 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
834 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
835 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
836 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
838 /* Set PCCARD timing parameters */
839 Device->PATT4 = (uint32_t)((Timing->SetupTime |\
840 ((Timing->WaitSetupTime) << 8) |\
841 (Timing->HoldSetupTime) << 16) |\
842 ((Timing->HiZSetupTime) << 24)
849 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
850 * parameters in the FMC_NAND_PCC_TimingTypeDef
851 * @param Device: Pointer to PCCARD device instance
852 * @param Timing: Pointer to PCCARD timing structure
855 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
857 /* Check the parameters */
858 assert_param(IS_FMC_PCCARD_DEVICE(Device));
859 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
860 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
861 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
862 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
864 /* Set FMC_PCCARD device timing parameters */
865 Device->PIO4 = (uint32_t)((Timing->SetupTime |\
866 ((Timing->WaitSetupTime) << 8) |\
867 (Timing->HoldSetupTime) << 16) |\
868 ((Timing->HiZSetupTime) << 24)
875 * @brief DeInitializes the FMC_PCCARD device
876 * @param Device: Pointer to PCCARD device instance
879 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
881 /* Check the parameters */
882 assert_param(IS_FMC_PCCARD_DEVICE(Device));
884 /* Disable the FMC_PCCARD device */
885 __FMC_PCCARD_DISABLE(Device);
887 /* De-initialize the FMC_PCCARD device */
888 Device->PCR4 = 0x00000018;
889 Device->SR4 = 0x00000000;
890 Device->PMEM4 = 0xFCFCFCFC;
891 Device->PATT4 = 0xFCFCFCFC;
892 Device->PIO4 = 0xFCFCFCFC;
908 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
910 #endif /* HAL_FMC_MODULE_ENABLED */
920 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/