2 ******************************************************************************
3 * @file stm32f30x_spi.h
4 * @author MCD Application Team
6 * @date 27-February-2014
7 * @brief This file contains all the functions prototypes for the SPI
9 ******************************************************************************
12 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 ******************************************************************************
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef __STM32F30x_SPI_H
41 #define __STM32F30x_SPI_H
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f30x.h"
50 /** @addtogroup STM32F30x_StdPeriph_Driver
58 /* Exported types ------------------------------------------------------------*/
61 * @brief SPI Init structure definition
66 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
67 This parameter can be a value of @ref SPI_data_direction */
69 uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
70 This parameter can be a value of @ref SPI_mode */
72 uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
73 This parameter can be a value of @ref SPI_data_size */
75 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
76 This parameter can be a value of @ref SPI_Clock_Polarity */
78 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
79 This parameter can be a value of @ref SPI_Clock_Phase */
81 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
82 hardware (NSS pin) or by software using the SSI bit.
83 This parameter can be a value of @ref SPI_Slave_Select_management */
85 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
86 used to configure the transmit and receive SCK clock.
87 This parameter can be a value of @ref SPI_BaudRate_Prescaler.
88 @note The communication clock is derived from the master
89 clock. The slave clock does not need to be set. */
91 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
92 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
94 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
99 * @brief I2S Init structure definition
104 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
105 This parameter can be a value of @ref I2S_Mode */
107 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
108 This parameter can be a value of @ref I2S_Standard */
110 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
111 This parameter can be a value of @ref I2S_Data_Format */
113 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
114 This parameter can be a value of @ref I2S_MCLK_Output */
116 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
117 This parameter can be a value of @ref I2S_Audio_Frequency */
119 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
120 This parameter can be a value of @ref I2S_Clock_Polarity */
123 /* Exported constants --------------------------------------------------------*/
125 /** @defgroup SPI_Exported_Constants
129 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
130 ((PERIPH) == SPI2) || \
133 #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
134 ((PERIPH) == SPI2) || \
135 ((PERIPH) == SPI3) || \
136 ((PERIPH) == I2S2ext) || \
137 ((PERIPH) == I2S3ext))
139 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
142 #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
143 ((PERIPH) == SPI3) || \
144 ((PERIPH) == I2S2ext) || \
145 ((PERIPH) == I2S3ext))
147 #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
148 ((PERIPH) == I2S3ext))
150 /** @defgroup SPI_data_direction
154 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
155 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
156 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
157 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
158 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
159 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
160 ((MODE) == SPI_Direction_1Line_Rx) || \
161 ((MODE) == SPI_Direction_1Line_Tx))
166 /** @defgroup SPI_mode
170 #define SPI_Mode_Master ((uint16_t)0x0104)
171 #define SPI_Mode_Slave ((uint16_t)0x0000)
172 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
173 ((MODE) == SPI_Mode_Slave))
178 /** @defgroup SPI_data_size
182 #define SPI_DataSize_4b ((uint16_t)0x0300)
183 #define SPI_DataSize_5b ((uint16_t)0x0400)
184 #define SPI_DataSize_6b ((uint16_t)0x0500)
185 #define SPI_DataSize_7b ((uint16_t)0x0600)
186 #define SPI_DataSize_8b ((uint16_t)0x0700)
187 #define SPI_DataSize_9b ((uint16_t)0x0800)
188 #define SPI_DataSize_10b ((uint16_t)0x0900)
189 #define SPI_DataSize_11b ((uint16_t)0x0A00)
190 #define SPI_DataSize_12b ((uint16_t)0x0B00)
191 #define SPI_DataSize_13b ((uint16_t)0x0C00)
192 #define SPI_DataSize_14b ((uint16_t)0x0D00)
193 #define SPI_DataSize_15b ((uint16_t)0x0E00)
194 #define SPI_DataSize_16b ((uint16_t)0x0F00)
195 #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
196 ((SIZE) == SPI_DataSize_5b) || \
197 ((SIZE) == SPI_DataSize_6b) || \
198 ((SIZE) == SPI_DataSize_7b) || \
199 ((SIZE) == SPI_DataSize_8b) || \
200 ((SIZE) == SPI_DataSize_9b) || \
201 ((SIZE) == SPI_DataSize_10b) || \
202 ((SIZE) == SPI_DataSize_11b) || \
203 ((SIZE) == SPI_DataSize_12b) || \
204 ((SIZE) == SPI_DataSize_13b) || \
205 ((SIZE) == SPI_DataSize_14b) || \
206 ((SIZE) == SPI_DataSize_15b) || \
207 ((SIZE) == SPI_DataSize_16b))
212 /** @defgroup SPI_CRC_length
216 #define SPI_CRCLength_8b ((uint16_t)0x0000)
217 #define SPI_CRCLength_16b ((uint16_t)0x0800)
218 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
219 ((LENGTH) == SPI_CRCLength_16b))
224 /** @defgroup SPI_Clock_Polarity
228 #define SPI_CPOL_Low ((uint16_t)0x0000)
229 #define SPI_CPOL_High ((uint16_t)0x0002)
230 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
231 ((CPOL) == SPI_CPOL_High))
236 /** @defgroup SPI_Clock_Phase
240 #define SPI_CPHA_1Edge ((uint16_t)0x0000)
241 #define SPI_CPHA_2Edge ((uint16_t)0x0001)
242 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
243 ((CPHA) == SPI_CPHA_2Edge))
248 /** @defgroup SPI_Slave_Select_management
252 #define SPI_NSS_Soft ((uint16_t)0x0200)
253 #define SPI_NSS_Hard ((uint16_t)0x0000)
254 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
255 ((NSS) == SPI_NSS_Hard))
260 /** @defgroup SPI_BaudRate_Prescaler
264 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
265 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
266 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
267 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
268 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
269 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
270 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
271 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
272 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
273 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
274 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
275 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
276 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
277 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
278 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
279 ((PRESCALER) == SPI_BaudRatePrescaler_256))
284 /** @defgroup SPI_MSB_LSB_transmission
288 #define SPI_FirstBit_MSB ((uint16_t)0x0000)
289 #define SPI_FirstBit_LSB ((uint16_t)0x0080)
290 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
291 ((BIT) == SPI_FirstBit_LSB))
296 /** @defgroup I2S_Mode
300 #define I2S_Mode_SlaveTx ((uint16_t)0x0000)
301 #define I2S_Mode_SlaveRx ((uint16_t)0x0100)
302 #define I2S_Mode_MasterTx ((uint16_t)0x0200)
303 #define I2S_Mode_MasterRx ((uint16_t)0x0300)
304 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
305 ((MODE) == I2S_Mode_SlaveRx) || \
306 ((MODE) == I2S_Mode_MasterTx)|| \
307 ((MODE) == I2S_Mode_MasterRx))
312 /** @defgroup I2S_Standard
316 #define I2S_Standard_Phillips ((uint16_t)0x0000)
317 #define I2S_Standard_MSB ((uint16_t)0x0010)
318 #define I2S_Standard_LSB ((uint16_t)0x0020)
319 #define I2S_Standard_PCMShort ((uint16_t)0x0030)
320 #define I2S_Standard_PCMLong ((uint16_t)0x00B0)
321 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
322 ((STANDARD) == I2S_Standard_MSB) || \
323 ((STANDARD) == I2S_Standard_LSB) || \
324 ((STANDARD) == I2S_Standard_PCMShort) || \
325 ((STANDARD) == I2S_Standard_PCMLong))
330 /** @defgroup I2S_Data_Format
334 #define I2S_DataFormat_16b ((uint16_t)0x0000)
335 #define I2S_DataFormat_16bextended ((uint16_t)0x0001)
336 #define I2S_DataFormat_24b ((uint16_t)0x0003)
337 #define I2S_DataFormat_32b ((uint16_t)0x0005)
338 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
339 ((FORMAT) == I2S_DataFormat_16bextended) || \
340 ((FORMAT) == I2S_DataFormat_24b) || \
341 ((FORMAT) == I2S_DataFormat_32b))
346 /** @defgroup I2S_MCLK_Output
350 #define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
351 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
352 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
353 ((OUTPUT) == I2S_MCLKOutput_Disable))
358 /** @defgroup I2S_Audio_Frequency
362 #define I2S_AudioFreq_192k ((uint32_t)192000)
363 #define I2S_AudioFreq_96k ((uint32_t)96000)
364 #define I2S_AudioFreq_48k ((uint32_t)48000)
365 #define I2S_AudioFreq_44k ((uint32_t)44100)
366 #define I2S_AudioFreq_32k ((uint32_t)32000)
367 #define I2S_AudioFreq_22k ((uint32_t)22050)
368 #define I2S_AudioFreq_16k ((uint32_t)16000)
369 #define I2S_AudioFreq_11k ((uint32_t)11025)
370 #define I2S_AudioFreq_8k ((uint32_t)8000)
371 #define I2S_AudioFreq_Default ((uint32_t)2)
373 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
374 ((FREQ) <= I2S_AudioFreq_192k)) || \
375 ((FREQ) == I2S_AudioFreq_Default))
380 /** @defgroup I2S_Clock_Polarity
384 #define I2S_CPOL_Low ((uint16_t)0x0000)
385 #define I2S_CPOL_High ((uint16_t)0x0008)
386 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
387 ((CPOL) == I2S_CPOL_High))
392 /** @defgroup SPI_FIFO_reception_threshold
396 #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
397 #define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000)
398 #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
399 ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
404 /** @defgroup SPI_I2S_DMA_transfer_requests
408 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
409 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
410 #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
415 /** @defgroup SPI_last_DMA_transfers
419 #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
420 #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
421 #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
422 #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
423 #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
424 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
425 ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
426 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
430 /** @defgroup SPI_NSS_internal_software_management
434 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
435 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
436 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
437 ((INTERNAL) == SPI_NSSInternalSoft_Reset))
442 /** @defgroup SPI_CRC_Transmit_Receive
446 #define SPI_CRC_Tx ((uint8_t)0x00)
447 #define SPI_CRC_Rx ((uint8_t)0x01)
448 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
453 /** @defgroup SPI_direction_transmit_receive
457 #define SPI_Direction_Rx ((uint16_t)0xBFFF)
458 #define SPI_Direction_Tx ((uint16_t)0x4000)
459 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
460 ((DIRECTION) == SPI_Direction_Tx))
465 /** @defgroup SPI_I2S_interrupts_definition
469 #define SPI_I2S_IT_TXE ((uint8_t)0x71)
470 #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
471 #define SPI_I2S_IT_ERR ((uint8_t)0x50)
473 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
474 ((IT) == SPI_I2S_IT_RXNE) || \
475 ((IT) == SPI_I2S_IT_ERR))
477 #define I2S_IT_UDR ((uint8_t)0x53)
478 #define SPI_IT_MODF ((uint8_t)0x55)
479 #define SPI_I2S_IT_OVR ((uint8_t)0x56)
480 #define SPI_I2S_IT_FRE ((uint8_t)0x58)
482 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
483 ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
484 ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
490 /** @defgroup SPI_transmission_fifo_status_level
494 #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
495 #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
496 #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
497 #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
503 /** @defgroup SPI_reception_fifo_status_level
506 #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
507 #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
508 #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
509 #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
516 /** @defgroup SPI_I2S_flags_definition
520 #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
521 #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
522 #define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
523 #define I2S_FLAG_UDR ((uint16_t)0x0008)
524 #define SPI_FLAG_CRCERR ((uint16_t)0x0010)
525 #define SPI_FLAG_MODF ((uint16_t)0x0020)
526 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
527 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
528 #define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
532 #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
533 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
534 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
535 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
536 ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
537 ((FLAG) == I2S_FLAG_UDR))
542 /** @defgroup SPI_CRC_polynomial
546 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
555 /* Exported macro ------------------------------------------------------------*/
556 /* Exported functions ------------------------------------------------------- */
558 /* Function used to set the SPI configuration to the default reset state*******/
559 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
561 /* Initialization and Configuration functions *********************************/
562 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
563 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
564 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
565 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
566 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
567 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
568 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
569 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
570 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
571 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
572 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
573 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
574 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
575 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
577 /* Data transfers functions ***************************************************/
578 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
579 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
580 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
581 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
583 /* Hardware CRC Calculation functions *****************************************/
584 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
585 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
586 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
587 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
588 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
590 /* DMA transfers management functions *****************************************/
591 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
592 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
594 /* Interrupts and flags management functions **********************************/
595 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
596 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
597 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
598 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
599 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
600 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
606 #endif /*__STM32F30x_SPI_H */
616 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/