2 ******************************************************************************
3 * @file stm32f30x_syscfg.h
4 * @author MCD Application Team
6 * @date 27-February-2014
7 * @brief This file contains all the functions prototypes for the SYSCFG firmware
9 ******************************************************************************
12 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 ******************************************************************************
39 /*!< Define to prevent recursive inclusion -----------------------------------*/
40 #ifndef __STM32F30x_SYSCFG_H
41 #define __STM32F30x_SYSCFG_H
47 /*!< Includes ----------------------------------------------------------------*/
48 #include "stm32f30x.h"
50 /** @addtogroup STM32F30x_StdPeriph_Driver
54 /** @addtogroup SYSCFG
58 /* Exported types ------------------------------------------------------------*/
59 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup SYSCFG_Exported_Constants
65 /** @defgroup SYSCFG_EXTI_Port_Sources
68 #define EXTI_PortSourceGPIOA ((uint8_t)0x00)
69 #define EXTI_PortSourceGPIOB ((uint8_t)0x01)
70 #define EXTI_PortSourceGPIOC ((uint8_t)0x02)
71 #define EXTI_PortSourceGPIOD ((uint8_t)0x03)
72 #define EXTI_PortSourceGPIOE ((uint8_t)0x04)
73 #define EXTI_PortSourceGPIOF ((uint8_t)0x05)
75 #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
76 ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
77 ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
78 ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
79 ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
80 ((PORTSOURCE) == EXTI_PortSourceGPIOF))
85 /** @defgroup SYSCFG_EXTI_Pin_sources
88 #define EXTI_PinSource0 ((uint8_t)0x00)
89 #define EXTI_PinSource1 ((uint8_t)0x01)
90 #define EXTI_PinSource2 ((uint8_t)0x02)
91 #define EXTI_PinSource3 ((uint8_t)0x03)
92 #define EXTI_PinSource4 ((uint8_t)0x04)
93 #define EXTI_PinSource5 ((uint8_t)0x05)
94 #define EXTI_PinSource6 ((uint8_t)0x06)
95 #define EXTI_PinSource7 ((uint8_t)0x07)
96 #define EXTI_PinSource8 ((uint8_t)0x08)
97 #define EXTI_PinSource9 ((uint8_t)0x09)
98 #define EXTI_PinSource10 ((uint8_t)0x0A)
99 #define EXTI_PinSource11 ((uint8_t)0x0B)
100 #define EXTI_PinSource12 ((uint8_t)0x0C)
101 #define EXTI_PinSource13 ((uint8_t)0x0D)
102 #define EXTI_PinSource14 ((uint8_t)0x0E)
103 #define EXTI_PinSource15 ((uint8_t)0x0F)
105 #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
106 ((PINSOURCE) == EXTI_PinSource1) || \
107 ((PINSOURCE) == EXTI_PinSource2) || \
108 ((PINSOURCE) == EXTI_PinSource3) || \
109 ((PINSOURCE) == EXTI_PinSource4) || \
110 ((PINSOURCE) == EXTI_PinSource5) || \
111 ((PINSOURCE) == EXTI_PinSource6) || \
112 ((PINSOURCE) == EXTI_PinSource7) || \
113 ((PINSOURCE) == EXTI_PinSource8) || \
114 ((PINSOURCE) == EXTI_PinSource9) || \
115 ((PINSOURCE) == EXTI_PinSource10) || \
116 ((PINSOURCE) == EXTI_PinSource11) || \
117 ((PINSOURCE) == EXTI_PinSource12) || \
118 ((PINSOURCE) == EXTI_PinSource13) || \
119 ((PINSOURCE) == EXTI_PinSource14) || \
120 ((PINSOURCE) == EXTI_PinSource15))
125 /** @defgroup SYSCFG_Memory_Remap_Config
128 #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
129 #define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
130 #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
133 #define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
134 ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
135 ((REMAP) == SYSCFG_MemoryRemap_SRAM))
141 /** @defgroup SYSCFG_DMA_Remap_Config
144 #define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */
145 #define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */
146 #define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests */
148 #define SYSCFG_DMARemap_TIM6DAC1Ch1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /* Remap TIM6/DAC1 Ch1 DMA requests */
149 #define SYSCFG_DMARemap_TIM7DAC1Ch2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /* Remap TIM7/DAC1 Ch2 DMA requests */
150 #define SYSCFG_DMARemap_DAC2Ch1 SYSCFG_CFGR1_DAC2Ch1_DMA_RMP /* Remap DAC2 Ch1 DMA requests */
152 #define SYSCFG_DMARemapCh2_SPI1_RX ((uint32_t)0x80000003) /* Remap SPI1 RX DMA CH2 requests */
153 #define SYSCFG_DMARemapCh4_SPI1_RX ((uint32_t)0x80000001) /* Remap SPI1 RX DMA CH4 requests */
154 #define SYSCFG_DMARemapCh6_SPI1_RX ((uint32_t)0x80000002) /* Remap SPI1 RX DMA CH6 requests */
156 #define SYSCFG_DMARemapCh3_SPI1_TX ((uint32_t)0x8000000C) /* Remap SPI1 TX DMA CH2 requests */
157 #define SYSCFG_DMARemapCh5_SPI1_TX ((uint32_t)0x80000004) /* Remap SPI1 TX DMA CH5 requests */
158 #define SYSCFG_DMARemapCh7_SPI1_TX ((uint32_t)0x80000008) /* Remap SPI1 TX DMA CH7 requests */
160 #define SYSCFG_DMARemapCh7_I2C1_RX ((uint32_t)0x80000030) /* Remap I2C1 RX DMA CH7 requests */
161 #define SYSCFG_DMARemapCh3_I2C1_RX ((uint32_t)0x80000010) /* Remap I2C1 RX DMA CH3 requests */
162 #define SYSCFG_DMARemapCh5_I2C1_RX ((uint32_t)0x80000020) /* Remap I2C1 RX DMA CH5 requests */
164 #define SYSCFG_DMARemapCh6_I2C1_TX ((uint32_t)0x800000C0) /* Remap I2C1 TX DMA CH6 requests */
165 #define SYSCFG_DMARemapCh2_I2C1_TX ((uint32_t)0x80000040) /* Remap I2C1 TX DMA CH2 requests */
166 #define SYSCFG_DMARemapCh4_I2C1_TX ((uint32_t)0x80000080) /* Remap I2C1 TX DMA CH4 requests */
168 #define SYSCFG_DMARemapCh4_ADC2 ((uint32_t)0x80000300) /* Remap ADC2 DMA1 Ch4 requests */
169 #define SYSCFG_DMARemapCh2_ADC2 ((uint32_t)0x80000200) /* Remap ADC2 DMA1 Ch2 requests */
171 /* SYSCFG_DMA_Remap_Legacy */
172 #define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_DMARemap_TIM6DAC1Ch1 /*!< Remap TIM6/DAC1 DMA requests */
173 #define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_DMARemap_TIM7DAC1Ch2 /*!< Remap TIM7/DAC2 DMA requests */
175 #define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
176 ((REMAP) == SYSCFG_DMARemap_TIM16) || \
177 ((REMAP) == SYSCFG_DMARemap_ADC2ADC4) || \
178 ((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \
179 ((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \
180 ((REMAP) == SYSCFG_DMARemap_DAC2Ch1) || \
181 ((REMAP) == SYSCFG_DMARemapCh2_SPI1_RX) || \
182 ((REMAP) == SYSCFG_DMARemapCh4_SPI1_RX) || \
183 ((REMAP) == SYSCFG_DMARemapCh6_SPI1_RX) || \
184 ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
185 ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
186 ((REMAP) == SYSCFG_DMARemapCh7_SPI1_TX) || \
187 ((REMAP) == SYSCFG_DMARemapCh7_I2C1_RX) || \
188 ((REMAP) == SYSCFG_DMARemapCh3_I2C1_RX) || \
189 ((REMAP) == SYSCFG_DMARemapCh5_I2C1_RX) || \
190 ((REMAP) == SYSCFG_DMARemapCh6_I2C1_TX) || \
191 ((REMAP) == SYSCFG_DMARemapCh2_I2C1_TX) || \
192 ((REMAP) == SYSCFG_DMARemapCh4_I2C1_TX) || \
193 ((REMAP) == SYSCFG_DMARemapCh4_ADC2) || \
194 ((REMAP) == SYSCFG_DMARemapCh2_ADC2))
200 /** @defgroup SYSCFG_Trigger_Remap_Config
203 #define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Remap DAC trigger to TIM3 */
204 #define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */
205 #define SYSCFG_TriggerRemap_DACHRTIM1_TRIG1 ((uint32_t)0x80010000) /*!< Remap DAC trigger to HRTIM1 TRIG1 */
206 #define SYSCFG_TriggerRemap_DACHRTIM1_TRIG2 ((uint32_t)0x80020000) /*!< Remap DAC trigger to HRTIM1 TRIG2 */
208 #define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \
209 ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG1) || \
210 ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG2) || \
211 ((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
217 /** @defgroup SYSCFG_EncoderRemap_Config
220 #define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */
221 #define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
222 #define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
223 #define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
225 #define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \
226 ((REMAP) == SYSCFG_EncoderRemap_TIM2) || \
227 ((REMAP) == SYSCFG_EncoderRemap_TIM3) || \
228 ((REMAP) == SYSCFG_EncoderRemap_TIM4))
234 /** @defgroup SYSCFG_I2C_FastModePlus_Config
237 #define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
238 #define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
239 #define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
240 #define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
241 #define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
242 #define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
244 #define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
245 ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
246 ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
247 ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
248 ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
249 ((PIN) == SYSCFG_I2CFastModePlus_I2C2))
255 /** @defgroup SYSCFG_FPU_Interrupt_Config
258 #define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */
259 #define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */
260 #define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */
261 #define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */
262 #define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */
263 #define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */
265 #define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
271 /** @defgroup SYSCFG_Lock_Config
274 #define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
275 #define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
276 #define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
278 #define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
279 ((CONFIG) == SYSCFG_Break_SRAMParity) || \
280 ((CONFIG) == SYSCFG_Break_Lockup))
286 /** @defgroup SYSCFG_SRAMWRP_Config
289 #define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
290 #define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
291 #define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
292 #define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
293 #define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
294 #define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
295 #define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
296 #define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
298 #define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
304 /** @defgroup SYSCFG_flags_definition
308 #define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
310 #define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
320 /* Exported macro ------------------------------------------------------------*/
321 /* Exported functions ------------------------------------------------------- */
323 /* Function used to set the SYSCFG configuration to the default reset state **/
324 void SYSCFG_DeInit(void);
326 /* SYSCFG configuration functions *********************************************/
327 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
328 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
329 void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
330 void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
331 void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
332 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
333 void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
334 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
335 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
336 void SYSCFG_BypassParityCheckDisable(void);
337 void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
338 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
339 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
345 #endif /*__STM32F30x_SYSCFG_H */
355 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/