2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
9 * This file provides two functions and one global variable to be called from
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32f4xx.s" file.
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
23 * This file configures the system clock as follows:
24 *--------------------------------------------------------------------------------------
25 * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL
26 * | (external 8 MHz clock) | (external 8 MHz clock)
27 *--------------------------------------------------------------------------------------
28 * SYSCLK(MHz) | 168 | 180
29 *--------------------------------------------------------------------------------------
30 * AHBCLK (MHz) | 168 | 180
31 *--------------------------------------------------------------------------------------
32 * APB1CLK (MHz) | 42 | 45
33 *--------------------------------------------------------------------------------------
34 * APB2CLK (MHz) | 84 | 90
35 *--------------------------------------------------------------------------------------
36 * USB capable (48 MHz precise clock) | YES | NO
37 *--------------------------------------------------------------------------------------
38 ******************************************************************************
41 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
43 * Redistribution and use in source and binary forms, with or without modification,
44 * are permitted provided that the following conditions are met:
45 * 1. Redistributions of source code must retain the above copyright notice,
46 * this list of conditions and the following disclaimer.
47 * 2. Redistributions in binary form must reproduce the above copyright notice,
48 * this list of conditions and the following disclaimer in the documentation
49 * and/or other materials provided with the distribution.
50 * 3. Neither the name of STMicroelectronics nor the names of its contributors
51 * may be used to endorse or promote products derived from this software
52 * without specific prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
55 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
57 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
60 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
61 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 ******************************************************************************
72 /** @addtogroup stm32f4xx_system
76 /** @addtogroup STM32F4xx_System_Private_Includes
81 #include "stm32f4xx.h"
84 #if !defined (HSE_VALUE)
85 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
86 #endif /* HSE_VALUE */
88 #if !defined (HSI_VALUE)
89 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
90 #endif /* HSI_VALUE */
96 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
104 /** @addtogroup STM32F4xx_System_Private_Defines
108 /************************* Miscellaneous Configuration ************************/
109 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
110 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
111 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
112 /* #define DATA_IN_ExtSRAM */
113 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
115 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
116 /* #define DATA_IN_ExtSDRAM */
117 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
119 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
120 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
121 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
123 /*!< Uncomment the following line if you need to relocate your vector Table in
125 /* #define VECT_TAB_SRAM */
126 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
127 This value must be a multiple of 0x200. */
128 /******************************************************************************/
134 /** @addtogroup STM32F4xx_System_Private_Macros
138 /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
139 #define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
140 #define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */
146 /** @addtogroup STM32F4xx_System_Private_Variables
149 /* This variable is updated in three ways:
150 1) by calling CMSIS function SystemCoreClockUpdate()
151 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
152 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
153 Note: If you use this function to configure the system clock; then there
154 is no need to call the 2 first functions listed above, since SystemCoreClock
155 variable is updated automatically.
157 uint32_t SystemCoreClock = 168000000;
158 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
164 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
168 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
169 static void SystemInit_ExtMemCtl(void);
170 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
172 void SystemClock_Config(void);
177 /** @addtogroup STM32F4xx_System_Private_Functions
182 * @brief Setup the microcontroller system
183 * Initialize the FPU setting, vector table location and External memory
188 void SystemInit(void)
190 /* FPU settings ------------------------------------------------------------*/
191 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
192 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
194 /* Reset the RCC clock configuration to the default reset state ------------*/
196 RCC->CR |= (uint32_t)0x00000001;
198 /* Reset CFGR register */
199 RCC->CFGR = 0x00000000;
201 /* Reset HSEON, CSSON and PLLON bits */
202 RCC->CR &= (uint32_t)0xFEF6FFFF;
204 /* Reset PLLCFGR register */
205 RCC->PLLCFGR = 0x24003010;
207 /* Reset HSEBYP bit */
208 RCC->CR &= (uint32_t)0xFFFBFFFF;
210 /* Disable all interrupts */
211 RCC->CIR = 0x00000000;
213 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
214 SystemInit_ExtMemCtl();
215 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
217 /* Configure the Vector Table location add offset address ------------------*/
219 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
221 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
224 /* Configure the Cube driver */
225 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
228 /* Configure the System clock source, PLL Multiplier and Divider factors,
229 AHB/APBx prescalers and Flash settings */
230 SystemClock_Config();
231 SystemCoreClockUpdate();
233 /* Reset the timer to avoid issues after the RAM initialization */
239 * @brief Update SystemCoreClock variable according to Clock Register Values.
240 * The SystemCoreClock variable contains the core clock (HCLK), it can
241 * be used by the user application to setup the SysTick timer or configure
244 * @note Each time the core clock (HCLK) changes, this function must be called
245 * to update SystemCoreClock variable value. Otherwise, any configuration
246 * based on this variable will be incorrect.
248 * @note - The system frequency computed by this function is not the real
249 * frequency in the chip. It is calculated based on the predefined
250 * constant and the selected clock source:
252 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
254 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
256 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
257 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
259 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
260 * 16 MHz) but the real value may vary depending on the variations
261 * in voltage and temperature.
263 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
264 * depends on the application requirements), user has to ensure that HSE_VALUE
265 * is same as the real frequency of the crystal used. Otherwise, this function
266 * may have wrong result.
268 * - The result of this function could be not correct when using fractional
269 * value for HSE crystal.
274 void SystemCoreClockUpdate(void)
276 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
278 /* Get SYSCLK source -------------------------------------------------------*/
279 tmp = RCC->CFGR & RCC_CFGR_SWS;
283 case 0x00: /* HSI used as system clock source */
284 SystemCoreClock = HSI_VALUE;
286 case 0x04: /* HSE used as system clock source */
287 SystemCoreClock = HSE_VALUE;
289 case 0x08: /* PLL used as system clock source */
291 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
292 SYSCLK = PLL_VCO / PLL_P
294 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
295 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
299 /* HSE used as PLL clock source */
300 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
304 /* HSI used as PLL clock source */
305 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
308 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
309 SystemCoreClock = pllvco/pllp;
312 SystemCoreClock = HSI_VALUE;
315 /* Compute HCLK frequency --------------------------------------------------*/
316 /* Get HCLK prescaler */
317 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
319 SystemCoreClock >>= tmp;
322 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
324 * @brief Setup the external memory controller.
325 * Called in startup_stm32f4xx.s before jump to main.
326 * This function configures the external memories (SRAM/SDRAM)
327 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
331 void SystemInit_ExtMemCtl(void)
333 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
334 #if defined (DATA_IN_ExtSDRAM)
335 register uint32_t tmpreg = 0, timeout = 0xFFFF;
336 register uint32_t index;
338 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
340 RCC->AHB1ENR |= 0x000001F8;
342 /* Connect PDx pins to FMC Alternate function */
343 GPIOD->AFR[0] = 0x000000CC;
344 GPIOD->AFR[1] = 0xCC000CCC;
345 /* Configure PDx pins in Alternate function mode */
346 GPIOD->MODER = 0xA02A000A;
347 /* Configure PDx pins speed to 50 MHz */
348 GPIOD->OSPEEDR = 0xA02A000A;
349 /* Configure PDx pins Output type to push-pull */
350 GPIOD->OTYPER = 0x00000000;
351 /* No pull-up, pull-down for PDx pins */
352 GPIOD->PUPDR = 0x00000000;
354 /* Connect PEx pins to FMC Alternate function */
355 GPIOE->AFR[0] = 0xC00000CC;
356 GPIOE->AFR[1] = 0xCCCCCCCC;
357 /* Configure PEx pins in Alternate function mode */
358 GPIOE->MODER = 0xAAAA800A;
359 /* Configure PEx pins speed to 50 MHz */
360 GPIOE->OSPEEDR = 0xAAAA800A;
361 /* Configure PEx pins Output type to push-pull */
362 GPIOE->OTYPER = 0x00000000;
363 /* No pull-up, pull-down for PEx pins */
364 GPIOE->PUPDR = 0x00000000;
366 /* Connect PFx pins to FMC Alternate function */
367 GPIOF->AFR[0] = 0xCCCCCCCC;
368 GPIOF->AFR[1] = 0xCCCCCCCC;
369 /* Configure PFx pins in Alternate function mode */
370 GPIOF->MODER = 0xAA800AAA;
371 /* Configure PFx pins speed to 50 MHz */
372 GPIOF->OSPEEDR = 0xAA800AAA;
373 /* Configure PFx pins Output type to push-pull */
374 GPIOF->OTYPER = 0x00000000;
375 /* No pull-up, pull-down for PFx pins */
376 GPIOF->PUPDR = 0x00000000;
378 /* Connect PGx pins to FMC Alternate function */
379 GPIOG->AFR[0] = 0xCCCCCCCC;
380 GPIOG->AFR[1] = 0xCCCCCCCC;
381 /* Configure PGx pins in Alternate function mode */
382 GPIOG->MODER = 0xAAAAAAAA;
383 /* Configure PGx pins speed to 50 MHz */
384 GPIOG->OSPEEDR = 0xAAAAAAAA;
385 /* Configure PGx pins Output type to push-pull */
386 GPIOG->OTYPER = 0x00000000;
387 /* No pull-up, pull-down for PGx pins */
388 GPIOG->PUPDR = 0x00000000;
390 /* Connect PHx pins to FMC Alternate function */
391 GPIOH->AFR[0] = 0x00C0CC00;
392 GPIOH->AFR[1] = 0xCCCCCCCC;
393 /* Configure PHx pins in Alternate function mode */
394 GPIOH->MODER = 0xAAAA08A0;
395 /* Configure PHx pins speed to 50 MHz */
396 GPIOH->OSPEEDR = 0xAAAA08A0;
397 /* Configure PHx pins Output type to push-pull */
398 GPIOH->OTYPER = 0x00000000;
399 /* No pull-up, pull-down for PHx pins */
400 GPIOH->PUPDR = 0x00000000;
402 /* Connect PIx pins to FMC Alternate function */
403 GPIOI->AFR[0] = 0xCCCCCCCC;
404 GPIOI->AFR[1] = 0x00000CC0;
405 /* Configure PIx pins in Alternate function mode */
406 GPIOI->MODER = 0x0028AAAA;
407 /* Configure PIx pins speed to 50 MHz */
408 GPIOI->OSPEEDR = 0x0028AAAA;
409 /* Configure PIx pins Output type to push-pull */
410 GPIOI->OTYPER = 0x00000000;
411 /* No pull-up, pull-down for PIx pins */
412 GPIOI->PUPDR = 0x00000000;
414 /*-- FMC Configuration ------------------------------------------------------*/
415 /* Enable the FMC interface clock */
416 RCC->AHB3ENR |= 0x00000001;
418 /* Configure and enable SDRAM bank1 */
419 FMC_Bank5_6->SDCR[0] = 0x000019E0;
420 FMC_Bank5_6->SDTR[0] = 0x01115351;
422 /* SDRAM initialization sequence */
423 /* Clock enable command */
424 FMC_Bank5_6->SDCMR = 0x00000011;
425 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
426 while((tmpreg != 0) && (timeout-- > 0))
428 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
432 for (index = 0; index<1000; index++);
435 FMC_Bank5_6->SDCMR = 0x00000012;
437 while((tmpreg != 0) && (timeout-- > 0))
439 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
442 /* Auto refresh command */
443 FMC_Bank5_6->SDCMR = 0x00000073;
445 while((tmpreg != 0) && (timeout-- > 0))
447 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
450 /* MRD register program */
451 FMC_Bank5_6->SDCMR = 0x00046014;
453 while((tmpreg != 0) && (timeout-- > 0))
455 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
458 /* Set refresh count */
459 tmpreg = FMC_Bank5_6->SDRTR;
460 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
462 /* Disable write protection */
463 tmpreg = FMC_Bank5_6->SDCR[0];
464 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
465 #endif /* DATA_IN_ExtSDRAM */
466 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
468 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
469 #if defined(DATA_IN_ExtSRAM)
470 /*-- GPIOs Configuration -----------------------------------------------------*/
471 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
472 RCC->AHB1ENR |= 0x00000078;
474 /* Connect PDx pins to FMC Alternate function */
475 GPIOD->AFR[0] = 0x00CCC0CC;
476 GPIOD->AFR[1] = 0xCCCCCCCC;
477 /* Configure PDx pins in Alternate function mode */
478 GPIOD->MODER = 0xAAAA0A8A;
479 /* Configure PDx pins speed to 100 MHz */
480 GPIOD->OSPEEDR = 0xFFFF0FCF;
481 /* Configure PDx pins Output type to push-pull */
482 GPIOD->OTYPER = 0x00000000;
483 /* No pull-up, pull-down for PDx pins */
484 GPIOD->PUPDR = 0x00000000;
486 /* Connect PEx pins to FMC Alternate function */
487 GPIOE->AFR[0] = 0xC00CC0CC;
488 GPIOE->AFR[1] = 0xCCCCCCCC;
489 /* Configure PEx pins in Alternate function mode */
490 GPIOE->MODER = 0xAAAA828A;
491 /* Configure PEx pins speed to 100 MHz */
492 GPIOE->OSPEEDR = 0xFFFFC3CF;
493 /* Configure PEx pins Output type to push-pull */
494 GPIOE->OTYPER = 0x00000000;
495 /* No pull-up, pull-down for PEx pins */
496 GPIOE->PUPDR = 0x00000000;
498 /* Connect PFx pins to FMC Alternate function */
499 GPIOF->AFR[0] = 0x00CCCCCC;
500 GPIOF->AFR[1] = 0xCCCC0000;
501 /* Configure PFx pins in Alternate function mode */
502 GPIOF->MODER = 0xAA000AAA;
503 /* Configure PFx pins speed to 100 MHz */
504 GPIOF->OSPEEDR = 0xFF000FFF;
505 /* Configure PFx pins Output type to push-pull */
506 GPIOF->OTYPER = 0x00000000;
507 /* No pull-up, pull-down for PFx pins */
508 GPIOF->PUPDR = 0x00000000;
510 /* Connect PGx pins to FMC Alternate function */
511 GPIOG->AFR[0] = 0x00CCCCCC;
512 GPIOG->AFR[1] = 0x000000C0;
513 /* Configure PGx pins in Alternate function mode */
514 GPIOG->MODER = 0x00085AAA;
515 /* Configure PGx pins speed to 100 MHz */
516 GPIOG->OSPEEDR = 0x000CAFFF;
517 /* Configure PGx pins Output type to push-pull */
518 GPIOG->OTYPER = 0x00000000;
519 /* No pull-up, pull-down for PGx pins */
520 GPIOG->PUPDR = 0x00000000;
522 /*-- FMC/FSMC Configuration --------------------------------------------------*/
523 /* Enable the FMC/FSMC interface clock */
524 RCC->AHB3ENR |= 0x00000001;
526 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
527 /* Configure and enable Bank1_SRAM2 */
528 FMC_Bank1->BTCR[2] = 0x00001011;
529 FMC_Bank1->BTCR[3] = 0x00000201;
530 FMC_Bank1E->BWTR[2] = 0x0fffffff;
531 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
533 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
534 /* Configure and enable Bank1_SRAM2 */
535 FSMC_Bank1->BTCR[2] = 0x00001011;
536 FSMC_Bank1->BTCR[3] = 0x00000201;
537 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
538 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
540 #endif /* DATA_IN_ExtSRAM */
541 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
543 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
545 /** System Clock Configuration
547 #if USE_SYSCLOCK_168 != 0
549 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
552 void SystemClock_Config(void)
555 RCC_OscInitTypeDef RCC_OscInitStruct;
556 RCC_ClkInitTypeDef RCC_ClkInitStruct;
560 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
562 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
563 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
564 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
565 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
566 RCC_OscInitStruct.PLL.PLLM = 8;
567 RCC_OscInitStruct.PLL.PLLN = 336;
568 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
569 RCC_OscInitStruct.PLL.PLLQ = 7;
570 HAL_RCC_OscConfig(&RCC_OscInitStruct);
572 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
573 |RCC_CLOCKTYPE_PCLK2;
574 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
575 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
576 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
577 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
578 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
582 #elif USE_SYSCLOCK_180 != 0
584 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
587 void SystemClock_Config(void)
590 RCC_OscInitTypeDef RCC_OscInitStruct;
591 RCC_ClkInitTypeDef RCC_ClkInitStruct;
595 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
597 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
598 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
599 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
600 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
601 RCC_OscInitStruct.PLL.PLLM = 8;
602 RCC_OscInitStruct.PLL.PLLN = 360;
603 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
604 RCC_OscInitStruct.PLL.PLLQ = 7;
605 HAL_RCC_OscConfig(&RCC_OscInitStruct);
607 HAL_PWREx_ActivateOverDrive();
609 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
610 |RCC_CLOCKTYPE_PCLK2;
611 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
612 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
613 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
614 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
615 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
631 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/