2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
9 * This file provides two functions and one global variable to be called from
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32f4xx.s" file.
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
23 * This file configures the system clock as follows:
24 *-----------------------------------------------------------------------------
25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
26 * | (external 8 MHz clock) | (internal 16 MHz)
28 * | (external 8 MHz xtal) |
29 *-----------------------------------------------------------------------------
30 * SYSCLK(MHz) | 100 | 100
31 *-----------------------------------------------------------------------------
32 * AHBCLK (MHz) | 100 | 100
33 *-----------------------------------------------------------------------------
34 * APB1CLK (MHz) | 50 | 50
35 *-----------------------------------------------------------------------------
36 * APB2CLK (MHz) | 100 | 100
37 *-----------------------------------------------------------------------------
38 * USB capable (48 MHz precise clock) | NO | NO
39 *-----------------------------------------------------------------------------
40 ******************************************************************************
43 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
45 * Redistribution and use in source and binary forms, with or without modification,
46 * are permitted provided that the following conditions are met:
47 * 1. Redistributions of source code must retain the above copyright notice,
48 * this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright notice,
50 * this list of conditions and the following disclaimer in the documentation
51 * and/or other materials provided with the distribution.
52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
53 * may be used to endorse or promote products derived from this software
54 * without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 ******************************************************************************
74 /** @addtogroup stm32f4xx_system
78 /** @addtogroup STM32F4xx_System_Private_Includes
83 #include "stm32f4xx.h"
85 #if !defined (HSE_VALUE)
86 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
87 #endif /* HSE_VALUE */
89 #if !defined (HSI_VALUE)
90 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
91 #endif /* HSI_VALUE */
97 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
105 /** @addtogroup STM32F4xx_System_Private_Defines
109 /************************* Miscellaneous Configuration ************************/
110 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
111 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
112 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
113 /* #define DATA_IN_ExtSRAM */
114 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
116 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
117 /* #define DATA_IN_ExtSDRAM */
118 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
120 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
121 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
122 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
124 /*!< Uncomment the following line if you need to relocate your vector Table in
126 /* #define VECT_TAB_SRAM */
127 #ifndef VECT_TAB_OFFSET
128 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
129 This value must be a multiple of 0x200. */
131 /******************************************************************************/
137 /** @addtogroup STM32F4xx_System_Private_Macros
141 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
142 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
143 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
149 /** @addtogroup STM32F4xx_System_Private_Variables
152 /* This variable is updated in three ways:
153 1) by calling CMSIS function SystemCoreClockUpdate()
154 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
155 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
156 Note: If you use this function to configure the system clock; then there
157 is no need to call the 2 first functions listed above, since SystemCoreClock
158 variable is updated automatically.
160 uint32_t SystemCoreClock = 16000000;
161 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
167 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
171 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
172 static void SystemInit_ExtMemCtl(void);
173 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
175 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
176 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
179 uint8_t SetSysClock_PLL_HSI(void);
185 /** @addtogroup STM32F4xx_System_Private_Functions
190 * @brief Setup the microcontroller system
191 * Initialize the FPU setting, vector table location and External memory
196 void SystemInit(void)
198 /* FPU settings ------------------------------------------------------------*/
199 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
200 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
202 /* Reset the RCC clock configuration to the default reset state ------------*/
204 RCC->CR |= (uint32_t)0x00000001;
206 /* Reset CFGR register */
207 RCC->CFGR = 0x00000000;
209 /* Reset HSEON, CSSON and PLLON bits */
210 RCC->CR &= (uint32_t)0xFEF6FFFF;
212 /* Reset PLLCFGR register */
213 RCC->PLLCFGR = 0x24003010;
215 /* Reset HSEBYP bit */
216 RCC->CR &= (uint32_t)0xFFFBFFFF;
218 /* Disable all interrupts */
219 RCC->CIR = 0x00000000;
221 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
222 SystemInit_ExtMemCtl();
223 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
225 /* Configure the Vector Table location add offset address ------------------*/
227 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
229 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
232 /* Configure the Cube driver */
233 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
236 /* Configure the System clock source, PLL Multiplier and Divider factors,
237 AHB/APBx prescalers and Flash settings */
240 /* Reset the timer to avoid issues after the RAM initialization */
246 * @brief Update SystemCoreClock variable according to Clock Register Values.
247 * The SystemCoreClock variable contains the core clock (HCLK), it can
248 * be used by the user application to setup the SysTick timer or configure
251 * @note Each time the core clock (HCLK) changes, this function must be called
252 * to update SystemCoreClock variable value. Otherwise, any configuration
253 * based on this variable will be incorrect.
255 * @note - The system frequency computed by this function is not the real
256 * frequency in the chip. It is calculated based on the predefined
257 * constant and the selected clock source:
259 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
261 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
263 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
264 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
266 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
267 * 16 MHz) but the real value may vary depending on the variations
268 * in voltage and temperature.
270 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
271 * depends on the application requirements), user has to ensure that HSE_VALUE
272 * is same as the real frequency of the crystal used. Otherwise, this function
273 * may have wrong result.
275 * - The result of this function could be not correct when using fractional
276 * value for HSE crystal.
281 void SystemCoreClockUpdate(void)
283 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
285 /* Get SYSCLK source -------------------------------------------------------*/
286 tmp = RCC->CFGR & RCC_CFGR_SWS;
290 case 0x00: /* HSI used as system clock source */
291 SystemCoreClock = HSI_VALUE;
293 case 0x04: /* HSE used as system clock source */
294 SystemCoreClock = HSE_VALUE;
296 case 0x08: /* PLL used as system clock source */
298 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
299 SYSCLK = PLL_VCO / PLL_P
301 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
302 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
306 /* HSE used as PLL clock source */
307 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
311 /* HSI used as PLL clock source */
312 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
315 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
316 SystemCoreClock = pllvco/pllp;
319 SystemCoreClock = HSI_VALUE;
322 /* Compute HCLK frequency --------------------------------------------------*/
323 /* Get HCLK prescaler */
324 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
326 SystemCoreClock >>= tmp;
329 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
331 * @brief Setup the external memory controller.
332 * Called in startup_stm32f4xx.s before jump to main.
333 * This function configures the external memories (SRAM/SDRAM)
334 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
338 void SystemInit_ExtMemCtl(void)
340 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
341 #if defined (DATA_IN_ExtSDRAM)
342 register uint32_t tmpreg = 0, timeout = 0xFFFF;
343 register uint32_t index;
345 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
347 RCC->AHB1ENR |= 0x000001F8;
349 /* Connect PDx pins to FMC Alternate function */
350 GPIOD->AFR[0] = 0x000000CC;
351 GPIOD->AFR[1] = 0xCC000CCC;
352 /* Configure PDx pins in Alternate function mode */
353 GPIOD->MODER = 0xA02A000A;
354 /* Configure PDx pins speed to 50 MHz */
355 GPIOD->OSPEEDR = 0xA02A000A;
356 /* Configure PDx pins Output type to push-pull */
357 GPIOD->OTYPER = 0x00000000;
358 /* No pull-up, pull-down for PDx pins */
359 GPIOD->PUPDR = 0x00000000;
361 /* Connect PEx pins to FMC Alternate function */
362 GPIOE->AFR[0] = 0xC00000CC;
363 GPIOE->AFR[1] = 0xCCCCCCCC;
364 /* Configure PEx pins in Alternate function mode */
365 GPIOE->MODER = 0xAAAA800A;
366 /* Configure PEx pins speed to 50 MHz */
367 GPIOE->OSPEEDR = 0xAAAA800A;
368 /* Configure PEx pins Output type to push-pull */
369 GPIOE->OTYPER = 0x00000000;
370 /* No pull-up, pull-down for PEx pins */
371 GPIOE->PUPDR = 0x00000000;
373 /* Connect PFx pins to FMC Alternate function */
374 GPIOF->AFR[0] = 0xCCCCCCCC;
375 GPIOF->AFR[1] = 0xCCCCCCCC;
376 /* Configure PFx pins in Alternate function mode */
377 GPIOF->MODER = 0xAA800AAA;
378 /* Configure PFx pins speed to 50 MHz */
379 GPIOF->OSPEEDR = 0xAA800AAA;
380 /* Configure PFx pins Output type to push-pull */
381 GPIOF->OTYPER = 0x00000000;
382 /* No pull-up, pull-down for PFx pins */
383 GPIOF->PUPDR = 0x00000000;
385 /* Connect PGx pins to FMC Alternate function */
386 GPIOG->AFR[0] = 0xCCCCCCCC;
387 GPIOG->AFR[1] = 0xCCCCCCCC;
388 /* Configure PGx pins in Alternate function mode */
389 GPIOG->MODER = 0xAAAAAAAA;
390 /* Configure PGx pins speed to 50 MHz */
391 GPIOG->OSPEEDR = 0xAAAAAAAA;
392 /* Configure PGx pins Output type to push-pull */
393 GPIOG->OTYPER = 0x00000000;
394 /* No pull-up, pull-down for PGx pins */
395 GPIOG->PUPDR = 0x00000000;
397 /* Connect PHx pins to FMC Alternate function */
398 GPIOH->AFR[0] = 0x00C0CC00;
399 GPIOH->AFR[1] = 0xCCCCCCCC;
400 /* Configure PHx pins in Alternate function mode */
401 GPIOH->MODER = 0xAAAA08A0;
402 /* Configure PHx pins speed to 50 MHz */
403 GPIOH->OSPEEDR = 0xAAAA08A0;
404 /* Configure PHx pins Output type to push-pull */
405 GPIOH->OTYPER = 0x00000000;
406 /* No pull-up, pull-down for PHx pins */
407 GPIOH->PUPDR = 0x00000000;
409 /* Connect PIx pins to FMC Alternate function */
410 GPIOI->AFR[0] = 0xCCCCCCCC;
411 GPIOI->AFR[1] = 0x00000CC0;
412 /* Configure PIx pins in Alternate function mode */
413 GPIOI->MODER = 0x0028AAAA;
414 /* Configure PIx pins speed to 50 MHz */
415 GPIOI->OSPEEDR = 0x0028AAAA;
416 /* Configure PIx pins Output type to push-pull */
417 GPIOI->OTYPER = 0x00000000;
418 /* No pull-up, pull-down for PIx pins */
419 GPIOI->PUPDR = 0x00000000;
421 /*-- FMC Configuration ------------------------------------------------------*/
422 /* Enable the FMC interface clock */
423 RCC->AHB3ENR |= 0x00000001;
425 /* Configure and enable SDRAM bank1 */
426 FMC_Bank5_6->SDCR[0] = 0x000019E0;
427 FMC_Bank5_6->SDTR[0] = 0x01115351;
429 /* SDRAM initialization sequence */
430 /* Clock enable command */
431 FMC_Bank5_6->SDCMR = 0x00000011;
432 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
433 while((tmpreg != 0) && (timeout-- > 0))
435 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
439 for (index = 0; index<1000; index++);
442 FMC_Bank5_6->SDCMR = 0x00000012;
444 while((tmpreg != 0) && (timeout-- > 0))
446 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
449 /* Auto refresh command */
450 FMC_Bank5_6->SDCMR = 0x00000073;
452 while((tmpreg != 0) && (timeout-- > 0))
454 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
457 /* MRD register program */
458 FMC_Bank5_6->SDCMR = 0x00046014;
460 while((tmpreg != 0) && (timeout-- > 0))
462 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
465 /* Set refresh count */
466 tmpreg = FMC_Bank5_6->SDRTR;
467 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
469 /* Disable write protection */
470 tmpreg = FMC_Bank5_6->SDCR[0];
471 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
472 #endif /* DATA_IN_ExtSDRAM */
473 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
475 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
476 #if defined(DATA_IN_ExtSRAM)
477 /*-- GPIOs Configuration -----------------------------------------------------*/
478 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
479 RCC->AHB1ENR |= 0x00000078;
481 /* Connect PDx pins to FMC Alternate function */
482 GPIOD->AFR[0] = 0x00CCC0CC;
483 GPIOD->AFR[1] = 0xCCCCCCCC;
484 /* Configure PDx pins in Alternate function mode */
485 GPIOD->MODER = 0xAAAA0A8A;
486 /* Configure PDx pins speed to 100 MHz */
487 GPIOD->OSPEEDR = 0xFFFF0FCF;
488 /* Configure PDx pins Output type to push-pull */
489 GPIOD->OTYPER = 0x00000000;
490 /* No pull-up, pull-down for PDx pins */
491 GPIOD->PUPDR = 0x00000000;
493 /* Connect PEx pins to FMC Alternate function */
494 GPIOE->AFR[0] = 0xC00CC0CC;
495 GPIOE->AFR[1] = 0xCCCCCCCC;
496 /* Configure PEx pins in Alternate function mode */
497 GPIOE->MODER = 0xAAAA828A;
498 /* Configure PEx pins speed to 100 MHz */
499 GPIOE->OSPEEDR = 0xFFFFC3CF;
500 /* Configure PEx pins Output type to push-pull */
501 GPIOE->OTYPER = 0x00000000;
502 /* No pull-up, pull-down for PEx pins */
503 GPIOE->PUPDR = 0x00000000;
505 /* Connect PFx pins to FMC Alternate function */
506 GPIOF->AFR[0] = 0x00CCCCCC;
507 GPIOF->AFR[1] = 0xCCCC0000;
508 /* Configure PFx pins in Alternate function mode */
509 GPIOF->MODER = 0xAA000AAA;
510 /* Configure PFx pins speed to 100 MHz */
511 GPIOF->OSPEEDR = 0xFF000FFF;
512 /* Configure PFx pins Output type to push-pull */
513 GPIOF->OTYPER = 0x00000000;
514 /* No pull-up, pull-down for PFx pins */
515 GPIOF->PUPDR = 0x00000000;
517 /* Connect PGx pins to FMC Alternate function */
518 GPIOG->AFR[0] = 0x00CCCCCC;
519 GPIOG->AFR[1] = 0x000000C0;
520 /* Configure PGx pins in Alternate function mode */
521 GPIOG->MODER = 0x00085AAA;
522 /* Configure PGx pins speed to 100 MHz */
523 GPIOG->OSPEEDR = 0x000CAFFF;
524 /* Configure PGx pins Output type to push-pull */
525 GPIOG->OTYPER = 0x00000000;
526 /* No pull-up, pull-down for PGx pins */
527 GPIOG->PUPDR = 0x00000000;
529 /*-- FMC/FSMC Configuration --------------------------------------------------*/
530 /* Enable the FMC/FSMC interface clock */
531 RCC->AHB3ENR |= 0x00000001;
533 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
534 /* Configure and enable Bank1_SRAM2 */
535 FMC_Bank1->BTCR[2] = 0x00001011;
536 FMC_Bank1->BTCR[3] = 0x00000201;
537 FMC_Bank1E->BWTR[2] = 0x0fffffff;
538 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
540 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
541 /* Configure and enable Bank1_SRAM2 */
542 FSMC_Bank1->BTCR[2] = 0x00001011;
543 FSMC_Bank1->BTCR[3] = 0x00000201;
544 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
545 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
547 #endif /* DATA_IN_ExtSRAM */
548 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
550 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
553 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
554 * AHB/APBx prescalers and Flash settings
555 * @note This function should be called only once the RCC clock configuration
556 * is reset to the default reset state (done in SystemInit() function).
560 void SetSysClock(void)
562 /* 1- Try to start with HSE and external clock */
563 #if USE_PLL_HSE_EXTC != 0
564 if (SetSysClock_PLL_HSE(1) == 0)
567 /* 2- If fail try to start with HSE and external xtal */
568 #if USE_PLL_HSE_XTAL != 0
569 if (SetSysClock_PLL_HSE(0) == 0)
572 /* 3- If fail start with HSI clock */
573 if (SetSysClock_PLL_HSI() == 0)
577 // [TODO] Put something here to tell the user that a problem occured...
583 /* Output clock on MCO2 pin(PC9) for debugging purpose */
584 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
587 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
588 /******************************************************************************/
589 /* PLL (clocked by HSE) used as System clock source */
590 /******************************************************************************/
591 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
593 RCC_ClkInitTypeDef RCC_ClkInitStruct;
594 RCC_OscInitTypeDef RCC_OscInitStruct;
596 /* The voltage scaling allows optimizing the power consumption when the device is
597 clocked below the maximum system frequency, to update the voltage scaling value
598 regarding system frequency refer to product datasheet. */
600 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
602 /* Enable HSE oscillator and activate PLL with HSE as source */
603 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
606 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
610 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
612 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
613 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
614 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
615 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
616 RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4)
617 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200)
618 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
619 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
620 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
625 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
626 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
627 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
628 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
629 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
630 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
631 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
636 /* Output clock on MCO1 pin(PA8) for debugging purpose */
639 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
641 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
647 /******************************************************************************/
648 /* PLL (clocked by HSI) used as System clock source */
649 /******************************************************************************/
650 uint8_t SetSysClock_PLL_HSI(void)
652 RCC_ClkInitTypeDef RCC_ClkInitStruct;
653 RCC_OscInitTypeDef RCC_OscInitStruct;
655 /* The voltage scaling allows optimizing the power consumption when the device is
656 clocked below the maximum system frequency, to update the voltage scaling value
657 regarding system frequency refer to product datasheet. */
659 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
661 /* Enable HSI oscillator and activate PLL with HSI as source */
662 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
663 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
664 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
665 RCC_OscInitStruct.HSICalibrationValue = 16;
666 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
667 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
668 //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
669 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
670 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
671 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
672 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
673 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
674 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
679 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
680 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
681 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
682 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
683 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
684 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
685 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
690 /* Output clock on MCO1 pin(PA8) for debugging purpose */
691 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
707 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/