2 ******************************************************************************
3 * @file stm32f4xx_hal_iwdg.h
4 * @author MCD Application Team
7 * @brief Header file of IWDG HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_IWDG_H
40 #define __STM32F4xx_HAL_IWDG_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
49 /** @addtogroup STM32F4xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
60 * @brief IWDG HAL State Structure definition
64 HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
65 HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
66 HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
67 HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
68 HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
70 }HAL_IWDG_StateTypeDef;
73 * @brief IWDG Init structure definition
77 uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
78 This parameter can be a value of @ref IWDG_Prescaler */
80 uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
81 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
86 * @brief IWDG handle Structure definition
90 IWDG_TypeDef *Instance; /*!< Register base address */
92 IWDG_InitTypeDef Init; /*!< IWDG required parameters */
94 HAL_LockTypeDef Lock; /*!< IWDG locking object */
96 __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
100 /* Exported constants --------------------------------------------------------*/
101 /** @defgroup IWDG_Exported_Constants
105 /** @defgroup IWDG_Registers_BitMask
108 /* --- KR Register ---*/
109 /* KR register bit mask */
110 #define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG reload counter enable */
111 #define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG peripheral enable */
112 #define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR write Access enable */
113 #define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR write Access disable */
115 #define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \
116 ((__KR__) == KR_KEY_ENABLE))|| \
117 ((__KR__) == KR_KEY_EWA)) || \
118 ((__KR__) == KR_KEY_DWA))
123 /** @defgroup IWDG_Flag_definition
126 #define IWDG_FLAG_PVU ((uint32_t)0x0001) /*!< Watchdog counter prescaler value update flag */
127 #define IWDG_FLAG_RVU ((uint32_t)0x0002) /*!< Watchdog counter reload value update flag */
129 #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
130 ((FLAG) == IWDG_FLAG_RVU))
136 /** @defgroup IWDG_Prescaler
139 #define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
140 #define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
141 #define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
142 #define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
143 #define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
144 #define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
145 #define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
148 #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \
149 ((PRESCALER) == IWDG_PRESCALER_8) || \
150 ((PRESCALER) == IWDG_PRESCALER_16) || \
151 ((PRESCALER) == IWDG_PRESCALER_32) || \
152 ((PRESCALER) == IWDG_PRESCALER_64) || \
153 ((PRESCALER) == IWDG_PRESCALER_128)|| \
154 ((PRESCALER) == IWDG_PRESCALER_256))
160 /** @defgroup IWDG_Reload_Value
163 #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
173 /* Exported macro ------------------------------------------------------------*/
175 /** @brief Reset IWDG handle state
176 * @param __HANDLE__: IWDG handle
179 #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
182 * @brief Enables the IWDG peripheral.
183 * @param __HANDLE__: IWDG handle
186 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE)
189 * @brief Reloads IWDG counter with value defined in the reload register
190 * (write access to IWDG_PR and IWDG_RLR registers disabled).
191 * @param __HANDLE__: IWDG handle
194 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD)
197 * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
198 * @param __HANDLE__: IWDG handle
201 #define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA)
204 * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
205 * @param __HANDLE__: IWDG handle
208 #define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA)
211 * @brief Gets the selected IWDG's flag status.
212 * @param __HANDLE__: IWDG handle
213 * @param __FLAG__: specifies the flag to check.
214 * This parameter can be one of the following values:
215 * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
216 * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
217 * @retval The new state of __FLAG__ (TRUE or FALSE).
219 #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
221 /* Exported functions --------------------------------------------------------*/
223 /* Initialization/de-initialization functions ********************************/
224 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
225 void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
227 /* I/O operation functions ****************************************************/
228 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
229 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
231 /* Peripheral State functions ************************************************/
232 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
246 #endif /* __STM32F4xx_HAL_IWDG_H */
248 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/