2 ******************************************************************************
3 * @file stm32f4xx_hal_nor.c
4 * @author MCD Application Team
7 * @brief NOR HAL module driver.
8 * This file provides a generic firmware to drive NOR memories mounted
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
16 This driver is a generic layered driver which contains a set of APIs used to
17 control NOR flash memories. It uses the FMC/FSMC layer functions to interface
18 with NOR devices. This driver is used as follows:
20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
21 with control and timing parameters for both normal and extended mode.
23 (+) Read NOR flash memory manufacturer code and device IDs using the function
24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
25 structure declared by the function caller.
27 (+) Access NOR flash memory by read/write data unit operations using the functions
28 HAL_NOR_Read(), HAL_NOR_Program().
30 (+) Perform NOR flash erase block/chip operations using the functions
31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
35 structure declared by the function caller.
37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
40 (+) You can monitor the NOR device HAL state by calling the function
43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
44 If a NOR flash device contains different operations and/or implementations,
45 it should be implemented separately.
47 *** NOR HAL driver macros list ***
48 =============================================
50 Below the list of most used macros in NOR HAL driver.
52 (+) __NOR_WRITE : NOR memory write data to specified address
55 ******************************************************************************
58 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 ******************************************************************************
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f4xx_hal.h"
88 /** @addtogroup STM32F4xx_HAL_Driver
93 * @brief NOR driver modules
96 #ifdef HAL_NOR_MODULE_ENABLED
97 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
99 /* Private typedef -----------------------------------------------------------*/
100 /* Private define ------------------------------------------------------------*/
101 /* Private macro -------------------------------------------------------------*/
102 /* Private variables ---------------------------------------------------------*/
103 /* Private function prototypes -----------------------------------------------*/
106 /* Private functions ---------------------------------------------------------*/
108 /** @defgroup NOR_Private_Functions
112 /** @defgroup NOR_Group1 Initialization and de-initialization functions
113 * @brief Initialization and Configuration functions
116 ==============================================================================
117 ##### NOR Initialization and de_initialization functions #####
118 ==============================================================================
120 This section provides functions allowing to initialize/de-initialize
128 * @brief Perform the NOR memory Initialization sequence
129 * @param hnor: pointer to the NOR handle
130 * @param Timing: pointer to NOR control timing structure
131 * @param ExtTiming: pointer to NOR extended mode timing structure
134 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
136 /* Check the NOR handle parameter */
142 if(hnor->State == HAL_NOR_STATE_RESET)
144 /* Initialize the low level hardware (MSP) */
145 HAL_NOR_MspInit(hnor);
148 /* Initialize NOR control Interface */
149 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
151 /* Initialize NOR timing Interface */
152 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
154 /* Initialize NOR extended mode timing Interface */
155 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
157 /* Enable the NORSRAM device */
158 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
160 /* Check the NOR controller state */
161 hnor->State = HAL_NOR_STATE_READY;
167 * @brief Perform NOR memory De-Initialization sequence
168 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
169 * the configuration information for NOR module.
172 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
174 /* De-Initialize the low level hardware (MSP) */
175 HAL_NOR_MspDeInit(hnor);
177 /* Configure the NOR registers with their reset values */
178 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
180 /* Update the NOR controller state */
181 hnor->State = HAL_NOR_STATE_RESET;
190 * @brief NOR MSP Init
191 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
192 * the configuration information for NOR module.
195 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
197 /* NOTE : This function Should not be modified, when the callback is needed,
198 the HAL_NOR_MspInit could be implemented in the user file
203 * @brief NOR MSP DeInit
204 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
205 * the configuration information for NOR module.
208 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
210 /* NOTE : This function Should not be modified, when the callback is needed,
211 the HAL_NOR_MspDeInit could be implemented in the user file
216 * @brief NOR BSP Wait fro Ready/Busy signal
217 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
218 * the configuration information for NOR module.
219 * @param Timeout: Maximum timeout value
222 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
224 /* NOTE : This function Should not be modified, when the callback is needed,
225 the HAL_NOR_BspWait could be implemented in the user file
233 /** @defgroup NOR_Group2 Input and Output functions
234 * @brief Input Output and memory control functions
237 ==============================================================================
238 ##### NOR Input and Output functions #####
239 ==============================================================================
241 This section provides functions allowing to use and control the NOR memory
248 * @brief Read NOR flash IDs
249 * @param hnor: pointer to the NOR handle
250 * @param pNOR_ID : pointer to NOR ID structure
253 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
255 uint32_t deviceAddress = 0;
260 /* Check the NOR controller state */
261 if(hnor->State == HAL_NOR_STATE_BUSY)
266 /* Select the NOR device address */
267 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
269 deviceAddress = NOR_MEMORY_ADRESS1;
271 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
273 deviceAddress = NOR_MEMORY_ADRESS2;
275 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
277 deviceAddress = NOR_MEMORY_ADRESS3;
279 else /* FMC_NORSRAM_BANK4 */
281 deviceAddress = NOR_MEMORY_ADRESS4;
284 /* Update the NOR controller state */
285 hnor->State = HAL_NOR_STATE_BUSY;
287 /* Send read ID command */
288 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
289 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
290 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090);
292 /* Read the NOR IDs */
293 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS);
294 pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
295 pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
296 pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
298 /* Check the NOR controller state */
299 hnor->State = HAL_NOR_STATE_READY;
301 /* Process unlocked */
308 * @brief Returns the NOR memory to Read mode.
309 * @param hnor: pointer to the NOR handle
312 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
314 uint32_t deviceAddress = 0;
319 /* Check the NOR controller state */
320 if(hnor->State == HAL_NOR_STATE_BUSY)
325 /* Select the NOR device address */
326 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
328 deviceAddress = NOR_MEMORY_ADRESS1;
330 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
332 deviceAddress = NOR_MEMORY_ADRESS2;
334 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
336 deviceAddress = NOR_MEMORY_ADRESS3;
338 else /* FMC_NORSRAM_BANK4 */
340 deviceAddress = NOR_MEMORY_ADRESS4;
343 __NOR_WRITE(deviceAddress, 0x00F0);
345 /* Check the NOR controller state */
346 hnor->State = HAL_NOR_STATE_READY;
348 /* Process unlocked */
355 * @brief Read data from NOR memory
356 * @param hnor: pointer to the NOR handle
357 * @param pAddress: pointer to Device address
358 * @param pData : pointer to read data
361 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
363 uint32_t deviceAddress = 0;
368 /* Check the NOR controller state */
369 if(hnor->State == HAL_NOR_STATE_BUSY)
374 /* Select the NOR device address */
375 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
377 deviceAddress = NOR_MEMORY_ADRESS1;
379 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
381 deviceAddress = NOR_MEMORY_ADRESS2;
383 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
385 deviceAddress = NOR_MEMORY_ADRESS3;
387 else /* FMC_NORSRAM_BANK4 */
389 deviceAddress = NOR_MEMORY_ADRESS4;
392 /* Update the NOR controller state */
393 hnor->State = HAL_NOR_STATE_BUSY;
395 /* Send read data command */
396 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
397 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
398 __NOR_WRITE(pAddress, 0x00F0);
401 *pData = *(__IO uint32_t *)pAddress;
403 /* Check the NOR controller state */
404 hnor->State = HAL_NOR_STATE_READY;
406 /* Process unlocked */
413 * @brief Program data to NOR memory
414 * @param hnor: pointer to the NOR handle
415 * @param pAddress: Device address
416 * @param pData : pointer to the data to write
419 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
421 uint32_t deviceAddress = 0;
426 /* Check the NOR controller state */
427 if(hnor->State == HAL_NOR_STATE_BUSY)
432 /* Select the NOR device address */
433 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
435 deviceAddress = NOR_MEMORY_ADRESS1;
437 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
439 deviceAddress = NOR_MEMORY_ADRESS2;
441 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
443 deviceAddress = NOR_MEMORY_ADRESS3;
445 else /* FMC_NORSRAM_BANK4 */
447 deviceAddress = NOR_MEMORY_ADRESS4;
450 /* Update the NOR controller state */
451 hnor->State = HAL_NOR_STATE_BUSY;
453 /* Send program data command */
454 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
455 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
456 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0);
459 __NOR_WRITE(pAddress, *pData);
461 /* Check the NOR controller state */
462 hnor->State = HAL_NOR_STATE_READY;
464 /* Process unlocked */
471 * @brief Reads a half-word buffer from the NOR memory.
472 * @param hnor: pointer to the NOR handle
473 * @param uwAddress: NOR memory internal address to read from.
474 * @param pData: pointer to the buffer that receives the data read from the
476 * @param uwBufferSize : number of Half word to read.
479 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
481 uint32_t deviceAddress = 0;
486 /* Check the NOR controller state */
487 if(hnor->State == HAL_NOR_STATE_BUSY)
492 /* Select the NOR device address */
493 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
495 deviceAddress = NOR_MEMORY_ADRESS1;
497 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
499 deviceAddress = NOR_MEMORY_ADRESS2;
501 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
503 deviceAddress = NOR_MEMORY_ADRESS3;
505 else /* FMC_NORSRAM_BANK4 */
507 deviceAddress = NOR_MEMORY_ADRESS4;
510 /* Update the NOR controller state */
511 hnor->State = HAL_NOR_STATE_BUSY;
513 /* Send read data command */
514 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
515 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
516 __NOR_WRITE(uwAddress, 0x00F0);
519 while( uwBufferSize > 0)
521 *pData++ = *(__IO uint16_t *)uwAddress;
526 /* Check the NOR controller state */
527 hnor->State = HAL_NOR_STATE_READY;
529 /* Process unlocked */
536 * @brief Writes a half-word buffer to the NOR memory. This function must be used
537 only with S29GL128P NOR memory.
538 * @param hnor: pointer to the NOR handle
539 * @param uwAddress: NOR memory internal start write address
540 * @param pData: pointer to source data buffer.
541 * @param uwBufferSize: Size of the buffer to write
544 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
546 uint32_t lastloadedaddress = 0;
547 uint32_t currentaddress = 0;
548 uint32_t endaddress = 0;
549 uint32_t deviceAddress = 0;
554 /* Check the NOR controller state */
555 if(hnor->State == HAL_NOR_STATE_BUSY)
560 /* Select the NOR device address */
561 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
563 deviceAddress = NOR_MEMORY_ADRESS1;
565 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
567 deviceAddress = NOR_MEMORY_ADRESS2;
569 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
571 deviceAddress = NOR_MEMORY_ADRESS3;
573 else /* FMC_NORSRAM_BANK4 */
575 deviceAddress = NOR_MEMORY_ADRESS4;
578 /* Update the NOR controller state */
579 hnor->State = HAL_NOR_STATE_BUSY;
581 /* Initialize variables */
582 currentaddress = uwAddress;
583 endaddress = uwAddress + uwBufferSize - 1;
584 lastloadedaddress = uwAddress;
586 /* Issue unlock command sequence */
587 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
588 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
590 /* Write Buffer Load Command */
591 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
592 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
594 /* Load Data into NOR Buffer */
595 while(currentaddress <= endaddress)
597 /* Store last loaded address & data value (for polling) */
598 lastloadedaddress = currentaddress;
600 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
605 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
607 /* Check the NOR controller state */
608 hnor->State = HAL_NOR_STATE_READY;
610 /* Process unlocked */
618 * @brief Erase the specified block of the NOR memory
619 * @param hnor: pointer to the NOR handle
620 * @param BlockAddress : Block to erase address
621 * @param Address: Device address
624 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
626 uint32_t deviceAddress = 0;
631 /* Check the NOR controller state */
632 if(hnor->State == HAL_NOR_STATE_BUSY)
637 /* Select the NOR device address */
638 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
640 deviceAddress = NOR_MEMORY_ADRESS1;
642 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
644 deviceAddress = NOR_MEMORY_ADRESS2;
646 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
648 deviceAddress = NOR_MEMORY_ADRESS3;
650 else /* FMC_NORSRAM_BANK4 */
652 deviceAddress = NOR_MEMORY_ADRESS4;
655 /* Update the NOR controller state */
656 hnor->State = HAL_NOR_STATE_BUSY;
658 /* Send block erase command sequence */
659 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
660 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
661 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
662 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
663 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
664 __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
666 /* Check the NOR memory status and update the controller state */
667 hnor->State = HAL_NOR_STATE_READY;
669 /* Process unlocked */
677 * @brief Erase the entire NOR chip.
678 * @param hnor: pointer to the NOR handle
679 * @param Address : Device address
682 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
684 uint32_t deviceAddress = 0;
689 /* Check the NOR controller state */
690 if(hnor->State == HAL_NOR_STATE_BUSY)
695 /* Select the NOR device address */
696 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
698 deviceAddress = NOR_MEMORY_ADRESS1;
700 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
702 deviceAddress = NOR_MEMORY_ADRESS2;
704 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
706 deviceAddress = NOR_MEMORY_ADRESS3;
708 else /* FMC_NORSRAM_BANK4 */
710 deviceAddress = NOR_MEMORY_ADRESS4;
713 /* Update the NOR controller state */
714 hnor->State = HAL_NOR_STATE_BUSY;
716 /* Send NOR chip erase command sequence */
717 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
718 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
719 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
720 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
721 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
722 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010);
724 /* Check the NOR memory status and update the controller state */
725 hnor->State = HAL_NOR_STATE_READY;
727 /* Process unlocked */
734 * @brief Read NOR flash CFI IDs
735 * @param hnor: pointer to the NOR handle
736 * @param pNOR_CFI : pointer to NOR CFI IDs structure
739 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
741 uint32_t deviceAddress = 0;
746 /* Check the NOR controller state */
747 if(hnor->State == HAL_NOR_STATE_BUSY)
752 /* Select the NOR device address */
753 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
755 deviceAddress = NOR_MEMORY_ADRESS1;
757 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
759 deviceAddress = NOR_MEMORY_ADRESS2;
761 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
763 deviceAddress = NOR_MEMORY_ADRESS3;
765 else /* FMC_NORSRAM_BANK4 */
767 deviceAddress = NOR_MEMORY_ADRESS4;
770 /* Update the NOR controller state */
771 hnor->State = HAL_NOR_STATE_BUSY;
773 /* Send read CFI query command */
774 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098);
776 /* read the NOR CFI information */
777 pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS);
778 pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS);
779 pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS);
780 pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS);
782 /* Check the NOR controller state */
783 hnor->State = HAL_NOR_STATE_READY;
785 /* Process unlocked */
795 /** @defgroup NOR_Group3 Control functions
796 * @brief management functions
799 ==============================================================================
800 ##### NOR Control functions #####
801 ==============================================================================
803 This subsection provides a set of functions allowing to control dynamically
811 * @brief Enables dynamically NOR write operation.
812 * @param hnor: pointer to the NOR handle
815 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
820 /* Enable write operation */
821 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
823 /* Update the NOR controller state */
824 hnor->State = HAL_NOR_STATE_READY;
826 /* Process unlocked */
833 * @brief Disables dynamically NOR write operation.
834 * @param hnor: pointer to the NOR handle
837 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
842 /* Update the SRAM controller state */
843 hnor->State = HAL_NOR_STATE_BUSY;
845 /* Disable write operation */
846 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
848 /* Update the NOR controller state */
849 hnor->State = HAL_NOR_STATE_PROTECTED;
851 /* Process unlocked */
861 /** @defgroup NOR_Group4 State functions
862 * @brief Peripheral State functions
865 ==============================================================================
866 ##### NOR State functions #####
867 ==============================================================================
869 This subsection permits to get in run-time the status of the NOR controller
877 * @brief return the NOR controller state
878 * @param hnor: pointer to the NOR handle
879 * @retval NOR controller state
881 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
887 * @brief Returns the NOR operation status.
888 * @param hnor: pointer to the NOR handle
889 * @param Address: Device address
890 * @param Timeout: NOR progamming Timeout
891 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
894 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
896 NOR_StatusTypedef status = NOR_ONGOING;
897 uint16_t tmpSR1 = 0, tmpSR2 = 0;
898 uint32_t tickstart = 0;
900 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
901 HAL_NOR_MspWait(hnor, Timeout);
903 /* Get the NOR memory operation status -------------------------------------*/
904 while(status != NOR_SUCCESS)
907 tickstart = HAL_GetTick();
908 /* Check for the Timeout */
909 if(Timeout != HAL_MAX_DELAY)
911 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
913 status = NOR_TIMEOUT;
917 /* Read NOR status register (DQ6 and DQ5) */
918 tmpSR1 = *(__IO uint16_t *)Address;
919 tmpSR2 = *(__IO uint16_t *)Address;
921 /* If DQ6 did not toggle between the two reads then return NOR_Success */
922 if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
927 if((tmpSR1 & 0x0020) == 0x0020)
932 tmpSR1 = *(__IO uint16_t *)Address;
933 tmpSR2 = *(__IO uint16_t *)Address;
935 /* If DQ6 did not toggle between the two reads then return NOR_Success */
936 if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
941 if((tmpSR1 & 0x0020) == 0x0020)
947 /* Return the operation status */
958 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
959 #endif /* HAL_NOR_MODULE_ENABLED */
968 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/