2 ******************************************************************************
3 * @file stm32f4xx_hal_pwr_ex.c
4 * @author MCD Application Team
7 * @brief Extended PWR HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of PWR extension peripheral:
10 * + Peripheral Extended features functions
12 ******************************************************************************
15 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 ******************************************************************************
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32f4xx_hal.h"
45 /** @addtogroup STM32F4xx_HAL_Driver
50 * @brief PWR HAL module driver
54 #ifdef HAL_PWR_MODULE_ENABLED
56 /* Private typedef -----------------------------------------------------------*/
57 /* Private define ------------------------------------------------------------*/
58 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
59 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
60 #define PWR_BKPREG_TIMEOUT_VALUE 1000
61 /* Private macro -------------------------------------------------------------*/
62 /* Private variables ---------------------------------------------------------*/
63 /* Private function prototypes -----------------------------------------------*/
64 /* Private functions ---------------------------------------------------------*/
66 /** @defgroup PWREx_Private_Functions
70 /** @defgroup PWREx_Group1 Peripheral Extended features functions
71 * @brief Peripheral Extended features functions
75 ===============================================================================
76 ##### Peripheral extended features functions #####
77 ===============================================================================
79 *** Main and Backup Regulators configuration ***
80 ================================================
82 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
83 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
84 retained even in Standby or VBAT mode when the low power backup regulator
85 is enabled. It can be considered as an internal EEPROM when VBAT is
86 always present. You can use the HAL_PWR_EnableBkUpReg() function to
87 enable the low power backup regulator.
89 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
90 the backup SRAM is powered from VDD which replaces the VBAT power supply to
93 (+) The backup SRAM is not mass erased by a tamper event. It is read
94 protected to prevent confidential data, such as cryptographic private
95 key, from being accessed. The backup SRAM can be erased only through
96 the Flash interface when a protection level change from level 1 to
98 -@- Refer to the description of Read protection (RDP) in the Flash
101 (+) The main internal regulator can be configured to have a tradeoff between
102 performance and power consumption when the device does not operate at
103 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
104 macro which configure VOS bit in PWR_CR register
106 Refer to the product datasheets for more details.
108 *** FLASH Power Down configuration ****
109 =======================================
111 (+) By setting the FPDS bit in the PWR_CR register by using the
112 HAL_PWR_EnableFlashPowerDown() function, the Flash memory also enters power
113 down mode when the device enters Stop mode. When the Flash memory
114 is in power down mode, an additional startup delay is incurred when
115 waking up from Stop mode.
117 (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
118 is OFF and the HSI or HSE clock source is selected as system clock.
119 The new value programmed is active only when the PLL is ON.
120 When the PLL is OFF, the voltage scale 3 is automatically selected.
121 Refer to the datasheets for more details.
123 *** Over-Drive and Under-Drive configuration ****
124 =================================================
126 (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
127 2 operating modes available:
128 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
129 voltage scaling (scale 1, scale 2 or scale 3)
130 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
131 higher frequency than the normal mode for a given voltage scaling (scale 1,
132 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
133 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
134 the sequence described in Reference manual.
136 (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
137 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
138 and internal SRAM. 2 operating modes are available:
139 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
140 available when the main regulator or the low power regulator is used in Scale 3 or
142 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
143 available when the main regulator or the low power regulator is in low voltage mode.
150 * @brief Enables the Backup Regulator.
154 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
156 uint32_t tickstart = 0;
158 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
161 tickstart = HAL_GetTick();
163 /* Wait till Backup regulator ready flag is set */
164 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
166 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
175 * @brief Disables the Backup Regulator.
179 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
181 uint32_t tickstart = 0;
183 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
186 tickstart = HAL_GetTick();
188 /* Wait till Backup regulator ready flag is set */
189 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
191 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
200 * @brief Enables the Flash Power Down in Stop mode.
204 void HAL_PWREx_EnableFlashPowerDown(void)
206 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
210 * @brief Disables the Flash Power Down in Stop mode.
214 void HAL_PWREx_DisableFlashPowerDown(void)
216 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
219 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
221 * @brief Enables Main Regulator low voltage mode.
222 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
226 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
228 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
232 * @brief Disables Main Regulator low voltage mode.
233 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
237 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
239 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
243 * @brief Enables Low Power Regulator low voltage mode.
244 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
248 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
250 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
254 * @brief Disables Low Power Regulator low voltage mode.
255 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
259 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
261 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
264 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
266 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
268 * @brief Activates the Over-Drive mode.
269 * @note This function can be used only for STM32F42xx/STM32F43xx devices.
270 * This mode allows the CPU and the core logic to operate at a higher frequency
271 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
272 * @note It is recommended to enter or exit Over-drive mode when the application is not running
273 * critical tasks and when the system clock source is either HSI or HSE.
274 * During the Over-drive switch activation, no peripheral clocks should be enabled.
275 * The peripheral clocks must be enabled once the Over-drive mode is activated.
279 HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void)
281 uint32_t tickstart = 0;
285 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
286 __HAL_PWR_OVERDRIVE_ENABLE();
289 tickstart = HAL_GetTick();
291 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
293 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
299 /* Enable the Over-drive switch */
300 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
303 tickstart = HAL_GetTick();
305 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
307 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
316 * @brief Deactivates the Over-Drive mode.
317 * @note This function can be used only for STM32F42xx/STM32F43xx devices.
318 * This mode allows the CPU and the core logic to operate at a higher frequency
319 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
320 * @note It is recommended to enter or exit Over-drive mode when the application is not running
321 * critical tasks and when the system clock source is either HSI or HSE.
322 * During the Over-drive switch activation, no peripheral clocks should be enabled.
323 * The peripheral clocks must be enabled once the Over-drive mode is activated.
327 HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void)
329 uint32_t tickstart = 0;
333 /* Disable the Over-drive switch */
334 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
337 tickstart = HAL_GetTick();
339 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
341 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
347 /* Disable the Over-drive */
348 __HAL_PWR_OVERDRIVE_DISABLE();
351 tickstart = HAL_GetTick();
353 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
355 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
365 * @brief Enters in Under-Drive STOP mode.
367 * @note This mode is only available for STM32F42xxx/STM324F3xxx devices.
369 * @note This mode can be selected only when the Under-Drive is already active
371 * @note This mode is enabled only with STOP low power mode.
372 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
373 * mode is only available when the main regulator or the low power regulator
374 * is in low voltage mode
376 * @note If the Under-drive mode was enabled, it is automatically disabled after
378 * When the voltage regulator operates in Under-drive mode, an additional
379 * startup delay is induced when waking up from Stop mode.
381 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
383 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
384 * the HSI RC oscillator is selected as system clock.
386 * @note When the voltage regulator operates in low power mode, an additional
387 * startup delay is incurred when waking up from Stop mode.
388 * By keeping the internal regulator ON during Stop mode, the consumption
389 * is higher although the startup time is reduced.
391 * @param Regulator: specifies the regulator state in STOP mode.
392 * This parameter can be one of the following values:
393 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
394 * and Flash memory in power-down when the device is in Stop under-drive mode
395 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
396 * and Flash memory in power-down when the device is in Stop under-drive mode
397 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
398 * This parameter can be one of the following values:
399 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
400 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
403 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
406 uint32_t tickstart = 0;
408 /* Check the parameters */
409 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
410 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
412 /* Enable Power ctrl clock */
414 /* Enable the Under-drive Mode ---------------------------------------------*/
415 /* Clear Under-drive flag */
416 __HAL_PWR_CLEAR_ODRUDR_FLAG();
418 /* Enable the Under-drive */
419 __HAL_PWR_UNDERDRIVE_ENABLE();
422 tickstart = HAL_GetTick();
424 /* Wait for UnderDrive mode is ready */
425 while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
427 if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
433 /* Select the regulator state in STOP mode ---------------------------------*/
435 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
436 tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
438 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
441 /* Store the new value */
444 /* Set SLEEPDEEP bit of Cortex System Control Register */
445 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
447 /* Select STOP mode entry --------------------------------------------------*/
448 if(STOPEntry == PWR_SLEEPENTRY_WFI)
450 /* Request Wait For Interrupt */
455 /* Request Wait For Event */
458 /* Reset SLEEPDEEP bit of Cortex System Control Register */
459 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
464 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
473 #endif /* HAL_PWR_MODULE_ENABLED */
482 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/