2 ******************************************************************************
3 * @file stm32f4xx_hal_sram.c
4 * @author MCD Application Team
7 * @brief SRAM HAL module driver.
8 * This file provides a generic firmware to drive SRAM memories
9 * mounted as external device.
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
16 This driver is a generic layered driver which contains a set of APIs used to
17 control SRAM memories. It uses the FMC layer functions to interface
19 The following sequence should be followed to configure the FMC/FSMC to interface
20 with SRAM/PSRAM memories:
22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
23 SRAM_HandleTypeDef hsram; and:
25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
26 values of the structure member.
28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
29 base register instance for NOR or SRAM device
31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
32 base register instance for NOR or SRAM extended mode
34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
35 mode timings; for example:
36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
37 and fill its fields with the allowed values of the structure member.
39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
40 performs the following sequence:
42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
43 (##) Control register configuration using the FMC NORSRAM interface function
45 (##) Timing register configuration using the FMC NORSRAM interface function
46 FMC_NORSRAM_Timing_Init()
47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
48 FMC_NORSRAM_Extended_Timing_Init()
49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
51 (#) At this stage you can perform read/write accesses from/to the memory connected
52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
60 (#) You can continuously monitor the SRAM device HAL state by calling the function
64 ******************************************************************************
67 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
69 * Redistribution and use in source and binary forms, with or without modification,
70 * are permitted provided that the following conditions are met:
71 * 1. Redistributions of source code must retain the above copyright notice,
72 * this list of conditions and the following disclaimer.
73 * 2. Redistributions in binary form must reproduce the above copyright notice,
74 * this list of conditions and the following disclaimer in the documentation
75 * and/or other materials provided with the distribution.
76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
77 * may be used to endorse or promote products derived from this software
78 * without specific prior written permission.
80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
91 ******************************************************************************
94 /* Includes ------------------------------------------------------------------*/
95 #include "stm32f4xx_hal.h"
97 /** @addtogroup STM32F4xx_HAL_Driver
102 * @brief SRAM driver modules
105 #ifdef HAL_SRAM_MODULE_ENABLED
107 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
109 /* Private typedef -----------------------------------------------------------*/
110 /* Private define ------------------------------------------------------------*/
111 /* Private macro -------------------------------------------------------------*/
112 /* Private variables ---------------------------------------------------------*/
113 /* Private function prototypes -----------------------------------------------*/
115 /* Private functions ---------------------------------------------------------*/
117 /** @defgroup SRAM_Private_Functions
121 /** @defgroup SRAM_Group1 Initialization and de-initialization functions
122 * @brief Initialization and Configuration functions
125 ==============================================================================
126 ##### SRAM Initialization and de_initialization functions #####
127 ==============================================================================
128 [..] This section provides functions allowing to initialize/de-initialize
136 * @brief Performs the SRAM device initialization sequence
137 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
138 * the configuration information for SRAM module.
139 * @param Timing: Pointer to SRAM control timing structure
140 * @param ExtTiming: Pointer to SRAM extended mode timing structure
143 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
145 /* Check the SRAM handle parameter */
146 if(hsram == HAL_NULL)
151 if(hsram->State == HAL_SRAM_STATE_RESET)
153 /* Initialize the low level hardware (MSP) */
154 HAL_SRAM_MspInit(hsram);
157 /* Initialize SRAM control Interface */
158 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
160 /* Initialize SRAM timing Interface */
161 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
163 /* Initialize SRAM extended mode timing Interface */
164 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
166 /* Enable the NORSRAM device */
167 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
173 * @brief Performs the SRAM device De-initialization sequence.
174 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
175 * the configuration information for SRAM module.
178 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
180 /* De-Initialize the low level hardware (MSP) */
181 HAL_SRAM_MspDeInit(hsram);
183 /* Configure the SRAM registers with their reset values */
184 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
186 hsram->State = HAL_SRAM_STATE_RESET;
195 * @brief SRAM MSP Init.
196 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
197 * the configuration information for SRAM module.
200 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
202 /* NOTE : This function Should not be modified, when the callback is needed,
203 the HAL_SRAM_MspInit could be implemented in the user file
208 * @brief SRAM MSP DeInit.
209 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
210 * the configuration information for SRAM module.
213 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
215 /* NOTE : This function Should not be modified, when the callback is needed,
216 the HAL_SRAM_MspDeInit could be implemented in the user file
221 * @brief DMA transfer complete callback.
222 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
223 * the configuration information for SRAM module.
226 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
228 /* NOTE : This function Should not be modified, when the callback is needed,
229 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
234 * @brief DMA transfer complete error callback.
235 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
236 * the configuration information for SRAM module.
239 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
241 /* NOTE : This function Should not be modified, when the callback is needed,
242 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
250 /** @defgroup SRAM_Group2 Input and Output functions
251 * @brief Input Output and memory control functions
254 ==============================================================================
255 ##### SRAM Input and Output functions #####
256 ==============================================================================
258 This section provides functions allowing to use and control the SRAM memory
265 * @brief Reads 8-bit buffer from SRAM memory.
266 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
267 * the configuration information for SRAM module.
268 * @param pAddress: Pointer to read start address
269 * @param pDstBuffer: Pointer to destination buffer
270 * @param BufferSize: Size of the buffer to read from memory
273 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
275 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
280 /* Update the SRAM controller state */
281 hsram->State = HAL_SRAM_STATE_BUSY;
283 /* Read data from memory */
284 for(; BufferSize != 0; BufferSize--)
286 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
291 /* Update the SRAM controller state */
292 hsram->State = HAL_SRAM_STATE_READY;
294 /* Process unlocked */
301 * @brief Writes 8-bit buffer to SRAM memory.
302 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
303 * the configuration information for SRAM module.
304 * @param pAddress: Pointer to write start address
305 * @param pSrcBuffer: Pointer to source buffer to write
306 * @param BufferSize: Size of the buffer to write to memory
309 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
311 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
313 /* Check the SRAM controller state */
314 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
322 /* Update the SRAM controller state */
323 hsram->State = HAL_SRAM_STATE_BUSY;
325 /* Write data to memory */
326 for(; BufferSize != 0; BufferSize--)
328 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
333 /* Update the SRAM controller state */
334 hsram->State = HAL_SRAM_STATE_READY;
336 /* Process unlocked */
343 * @brief Reads 16-bit buffer from SRAM memory.
344 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
345 * the configuration information for SRAM module.
346 * @param pAddress: Pointer to read start address
347 * @param pDstBuffer: Pointer to destination buffer
348 * @param BufferSize: Size of the buffer to read from memory
351 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
353 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
358 /* Update the SRAM controller state */
359 hsram->State = HAL_SRAM_STATE_BUSY;
361 /* Read data from memory */
362 for(; BufferSize != 0; BufferSize--)
364 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
369 /* Update the SRAM controller state */
370 hsram->State = HAL_SRAM_STATE_READY;
372 /* Process unlocked */
379 * @brief Writes 16-bit buffer to SRAM memory.
380 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
381 * the configuration information for SRAM module.
382 * @param pAddress: Pointer to write start address
383 * @param pSrcBuffer: Pointer to source buffer to write
384 * @param BufferSize: Size of the buffer to write to memory
387 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
389 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
391 /* Check the SRAM controller state */
392 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
400 /* Update the SRAM controller state */
401 hsram->State = HAL_SRAM_STATE_BUSY;
403 /* Write data to memory */
404 for(; BufferSize != 0; BufferSize--)
406 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
411 /* Update the SRAM controller state */
412 hsram->State = HAL_SRAM_STATE_READY;
414 /* Process unlocked */
421 * @brief Reads 32-bit buffer from SRAM memory.
422 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
423 * the configuration information for SRAM module.
424 * @param pAddress: Pointer to read start address
425 * @param pDstBuffer: Pointer to destination buffer
426 * @param BufferSize: Size of the buffer to read from memory
429 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
434 /* Update the SRAM controller state */
435 hsram->State = HAL_SRAM_STATE_BUSY;
437 /* Read data from memory */
438 for(; BufferSize != 0; BufferSize--)
440 *pDstBuffer = *(__IO uint32_t *)pAddress;
445 /* Update the SRAM controller state */
446 hsram->State = HAL_SRAM_STATE_READY;
448 /* Process unlocked */
455 * @brief Writes 32-bit buffer to SRAM memory.
456 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
457 * the configuration information for SRAM module.
458 * @param pAddress: Pointer to write start address
459 * @param pSrcBuffer: Pointer to source buffer to write
460 * @param BufferSize: Size of the buffer to write to memory
463 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
465 /* Check the SRAM controller state */
466 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
474 /* Update the SRAM controller state */
475 hsram->State = HAL_SRAM_STATE_BUSY;
477 /* Write data to memory */
478 for(; BufferSize != 0; BufferSize--)
480 *(__IO uint32_t *)pAddress = *pSrcBuffer;
485 /* Update the SRAM controller state */
486 hsram->State = HAL_SRAM_STATE_READY;
488 /* Process unlocked */
495 * @brief Reads a Words data from the SRAM memory using DMA transfer.
496 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
497 * the configuration information for SRAM module.
498 * @param pAddress: Pointer to read start address
499 * @param pDstBuffer: Pointer to destination buffer
500 * @param BufferSize: Size of the buffer to read from memory
503 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
508 /* Update the SRAM controller state */
509 hsram->State = HAL_SRAM_STATE_BUSY;
511 /* Configure DMA user callbacks */
512 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
513 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
515 /* Enable the DMA Stream */
516 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
518 /* Update the SRAM controller state */
519 hsram->State = HAL_SRAM_STATE_READY;
521 /* Process unlocked */
528 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
529 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
530 * the configuration information for SRAM module.
531 * @param pAddress: Pointer to write start address
532 * @param pSrcBuffer: Pointer to source buffer to write
533 * @param BufferSize: Size of the buffer to write to memory
536 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
538 /* Check the SRAM controller state */
539 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
547 /* Update the SRAM controller state */
548 hsram->State = HAL_SRAM_STATE_BUSY;
550 /* Configure DMA user callbacks */
551 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
552 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
554 /* Enable the DMA Stream */
555 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
557 /* Update the SRAM controller state */
558 hsram->State = HAL_SRAM_STATE_READY;
560 /* Process unlocked */
570 /** @defgroup SRAM_Group3 Control functions
571 * @brief management functions
574 ==============================================================================
575 ##### SRAM Control functions #####
576 ==============================================================================
578 This subsection provides a set of functions allowing to control dynamically
586 * @brief Enables dynamically SRAM write operation.
587 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
588 * the configuration information for SRAM module.
591 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
596 /* Enable write operation */
597 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
599 /* Update the SRAM controller state */
600 hsram->State = HAL_SRAM_STATE_READY;
602 /* Process unlocked */
609 * @brief Disables dynamically SRAM write operation.
610 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
611 * the configuration information for SRAM module.
614 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
619 /* Update the SRAM controller state */
620 hsram->State = HAL_SRAM_STATE_BUSY;
622 /* Disable write operation */
623 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
625 /* Update the SRAM controller state */
626 hsram->State = HAL_SRAM_STATE_PROTECTED;
628 /* Process unlocked */
638 /** @defgroup SRAM_Group4 State functions
639 * @brief Peripheral State functions
642 ==============================================================================
643 ##### SRAM State functions #####
644 ==============================================================================
646 This subsection permits to get in run-time the status of the SRAM controller
654 * @brief Returns the SRAM controller state
655 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
656 * the configuration information for SRAM module.
659 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
671 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
672 #endif /* HAL_SRAM_MODULE_ENABLED */
681 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/