2 ******************************************************************************
3 * @file stm32f4xx_hal_tim.h
4 * @author MCD Application Team
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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14 * are permitted provided that the following conditions are met:
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22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_TIM_H
40 #define __STM32F4xx_HAL_TIM_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
49 /** @addtogroup STM32F4xx_HAL
57 /* Exported types ------------------------------------------------------------*/
60 * @brief TIM Time base Configuration Structure definition
64 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
65 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
67 uint32_t CounterMode; /*!< Specifies the counter mode.
68 This parameter can be a value of @ref TIM_Counter_Mode */
70 uint32_t Period; /*!< Specifies the period value to be loaded into the active
71 Auto-Reload Register at the next update event.
72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
74 uint32_t ClockDivision; /*!< Specifies the clock division.
75 This parameter can be a value of @ref TIM_ClockDivision */
77 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
78 reaches zero, an update event is generated and counting restarts
79 from the RCR value (N).
80 This means in PWM mode that (N+1) corresponds to:
81 - the number of PWM periods in edge-aligned mode
82 - the number of half PWM period in center-aligned mode
83 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
84 @note This parameter is valid only for TIM1 and TIM8. */
85 } TIM_Base_InitTypeDef;
88 * @brief TIM Output Compare Configuration Structure definition
93 uint32_t OCMode; /*!< Specifies the TIM mode.
94 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
96 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
97 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
99 uint32_t OCPolarity; /*!< Specifies the output polarity.
100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
102 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
104 @note This parameter is valid only for TIM1 and TIM8. */
106 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
107 This parameter can be a value of @ref TIM_Output_Fast_State
108 @note This parameter is valid only in PWM1 and PWM2 mode. */
111 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
112 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
113 @note This parameter is valid only for TIM1 and TIM8. */
115 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
116 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
117 @note This parameter is valid only for TIM1 and TIM8. */
118 } TIM_OC_InitTypeDef;
121 * @brief TIM One Pulse Mode Configuration Structure definition
125 uint32_t OCMode; /*!< Specifies the TIM mode.
126 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
128 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
129 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
131 uint32_t OCPolarity; /*!< Specifies the output polarity.
132 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
134 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
135 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
136 @note This parameter is valid only for TIM1 and TIM8. */
138 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
139 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
140 @note This parameter is valid only for TIM1 and TIM8. */
142 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
143 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
144 @note This parameter is valid only for TIM1 and TIM8. */
146 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
147 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
149 uint32_t ICSelection; /*!< Specifies the input.
150 This parameter can be a value of @ref TIM_Input_Capture_Selection */
152 uint32_t ICFilter; /*!< Specifies the input capture filter.
153 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
154 } TIM_OnePulse_InitTypeDef;
158 * @brief TIM Input Capture Configuration Structure definition
163 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
164 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
166 uint32_t ICSelection; /*!< Specifies the input.
167 This parameter can be a value of @ref TIM_Input_Capture_Selection */
169 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
170 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
172 uint32_t ICFilter; /*!< Specifies the input capture filter.
173 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
174 } TIM_IC_InitTypeDef;
177 * @brief TIM Encoder Configuration Structure definition
182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
183 This parameter can be a value of @ref TIM_Encoder_Mode */
185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
188 uint32_t IC1Selection; /*!< Specifies the input.
189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
200 uint32_t IC2Selection; /*!< Specifies the input.
201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
208 } TIM_Encoder_InitTypeDef;
211 * @brief Clock Configuration Handle Structure definition
215 uint32_t ClockSource; /*!< TIM clock sources.
216 This parameter can be a value of @ref TIM_Clock_Source */
217 uint32_t ClockPolarity; /*!< TIM clock polarity.
218 This parameter can be a value of @ref TIM_Clock_Polarity */
219 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
220 This parameter can be a value of @ref TIM_Clock_Prescaler */
221 uint32_t ClockFilter; /*!< TIM clock filter.
222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
223 }TIM_ClockConfigTypeDef;
226 * @brief Clear Input Configuration Handle Structure definition
230 uint32_t ClearInputState; /*!< TIM clear Input state.
231 This parameter can be ENABLE or DISABLE */
232 uint32_t ClearInputSource; /*!< TIM clear Input sources.
233 This parameter can be a value of @ref TIM_ClearInput_Source */
234 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
235 This parameter can be a value of @ref TIM_ClearInput_Polarity */
236 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
237 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
238 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
239 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
240 }TIM_ClearInputConfigTypeDef;
243 * @brief TIM Slave configuration Structure definition
246 uint32_t SlaveMode; /*!< Slave mode selection
247 This parameter can be a value of @ref TIM_Slave_Mode */
248 uint32_t InputTrigger; /*!< Input Trigger source
249 This parameter can be a value of @ref TIM_Trigger_Selection */
250 uint32_t TriggerPolarity; /*!< Input Trigger polarity
251 This parameter can be a value of @ref TIM_Trigger_Polarity */
252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
253 This parameter can be a value of @ref TIM_Trigger_Prescaler */
254 uint32_t TriggerFilter; /*!< Input trigger filter
255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
257 }TIM_SlaveConfigTypeDef;
260 * @brief HAL State structures definition
264 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
265 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
266 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
267 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
268 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
269 }HAL_TIM_StateTypeDef;
272 * @brief HAL Active channel structures definition
276 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
277 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
278 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
279 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
280 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
281 }HAL_TIM_ActiveChannel;
284 * @brief TIM Time Base Handle Structure definition
288 TIM_TypeDef *Instance; /*!< Register base address */
289 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
290 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
291 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
292 This array is accessed by a @ref DMA_Handle_index */
293 HAL_LockTypeDef Lock; /*!< Locking object */
294 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
297 /* Exported constants --------------------------------------------------------*/
298 /** @defgroup TIM_Exported_Constants
302 /** @defgroup TIM_Input_Channel_Polarity
305 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
306 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
307 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
312 /** @defgroup TIM_ETR_Polarity
315 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
316 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
321 /** @defgroup TIM_ETR_Prescaler
324 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
325 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
326 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
327 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
332 /** @defgroup TIM_Counter_Mode
335 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
336 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
337 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
338 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
339 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
341 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
342 ((MODE) == TIM_COUNTERMODE_DOWN) || \
343 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
344 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
345 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
350 /** @defgroup TIM_ClockDivision
353 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
357 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
358 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
359 ((DIV) == TIM_CLOCKDIVISION_DIV4))
364 /** @defgroup TIM_Output_Compare_and_PWM_modes
367 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
368 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
369 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
370 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
371 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
372 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
373 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
374 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
376 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
377 ((MODE) == TIM_OCMODE_PWM2))
379 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
380 ((MODE) == TIM_OCMODE_ACTIVE) || \
381 ((MODE) == TIM_OCMODE_INACTIVE) || \
382 ((MODE) == TIM_OCMODE_TOGGLE) || \
383 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
384 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
389 /** @defgroup TIM_Output_Compare_State
392 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
393 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
395 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
396 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
401 /** @defgroup TIM_Output_Fast_State
404 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
405 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
407 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
408 ((STATE) == TIM_OCFAST_ENABLE))
413 /** @defgroup TIM_Output_Compare_N_State
416 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
417 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
419 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
420 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
425 /** @defgroup TIM_Output_Compare_Polarity
428 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
429 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
431 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
432 ((POLARITY) == TIM_OCPOLARITY_LOW))
437 /** @defgroup TIM_Output_Compare_N_Polarity
440 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
441 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
443 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
444 ((POLARITY) == TIM_OCNPOLARITY_LOW))
449 /** @defgroup TIM_Output_Compare_Idle_State
452 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
453 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
454 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
455 ((STATE) == TIM_OCIDLESTATE_RESET))
460 /** @defgroup TIM_Output_Compare_N_Idle_State
463 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
464 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
465 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
466 ((STATE) == TIM_OCNIDLESTATE_RESET))
471 /** @defgroup TIM_Channel
474 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
475 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
476 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
477 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
478 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
480 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
481 ((CHANNEL) == TIM_CHANNEL_2) || \
482 ((CHANNEL) == TIM_CHANNEL_3) || \
483 ((CHANNEL) == TIM_CHANNEL_4) || \
484 ((CHANNEL) == TIM_CHANNEL_ALL))
486 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
487 ((CHANNEL) == TIM_CHANNEL_2))
489 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
490 ((CHANNEL) == TIM_CHANNEL_2))
492 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
493 ((CHANNEL) == TIM_CHANNEL_2) || \
494 ((CHANNEL) == TIM_CHANNEL_3))
499 /** @defgroup TIM_Input_Capture_Polarity
502 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
503 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
504 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
506 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
507 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
508 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
513 /** @defgroup TIM_Input_Capture_Selection
516 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
517 connected to IC1, IC2, IC3 or IC4, respectively */
518 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
519 connected to IC2, IC1, IC4 or IC3, respectively */
520 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
522 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
523 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
524 ((SELECTION) == TIM_ICSELECTION_TRC))
529 /** @defgroup TIM_Input_Capture_Prescaler
532 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
533 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
534 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
535 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
537 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
538 ((PRESCALER) == TIM_ICPSC_DIV2) || \
539 ((PRESCALER) == TIM_ICPSC_DIV4) || \
540 ((PRESCALER) == TIM_ICPSC_DIV8))
545 /** @defgroup TIM_One_Pulse_Mode
548 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
549 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
550 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
551 ((MODE) == TIM_OPMODE_REPETITIVE))
556 /** @defgroup TIM_Encoder_Mode
559 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
560 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
561 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
562 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
563 ((MODE) == TIM_ENCODERMODE_TI2) || \
564 ((MODE) == TIM_ENCODERMODE_TI12))
569 /** @defgroup TIM_Interrupt_definition
572 #define TIM_IT_UPDATE (TIM_DIER_UIE)
573 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
574 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
575 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
576 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
577 #define TIM_IT_COM (TIM_DIER_COMIE)
578 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
579 #define TIM_IT_BREAK (TIM_DIER_BIE)
581 #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
583 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
584 ((IT) == TIM_IT_CC1) || \
585 ((IT) == TIM_IT_CC2) || \
586 ((IT) == TIM_IT_CC3) || \
587 ((IT) == TIM_IT_CC4) || \
588 ((IT) == TIM_IT_COM) || \
589 ((IT) == TIM_IT_TRIGGER) || \
590 ((IT) == TIM_IT_BREAK))
594 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
595 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
597 /** @defgroup TIM_DMA_sources
600 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
601 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
602 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
603 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
604 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
605 #define TIM_DMA_COM (TIM_DIER_COMDE)
606 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
607 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
612 /** @defgroup TIM_Event_Source
615 #define TIM_EventSource_Update TIM_EGR_UG
616 #define TIM_EventSource_CC1 TIM_EGR_CC1G
617 #define TIM_EventSource_CC2 TIM_EGR_CC2G
618 #define TIM_EventSource_CC3 TIM_EGR_CC3G
619 #define TIM_EventSource_CC4 TIM_EGR_CC4G
620 #define TIM_EventSource_COM TIM_EGR_COMG
621 #define TIM_EventSource_Trigger TIM_EGR_TG
622 #define TIM_EventSource_Break TIM_EGR_BG
623 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
628 /** @defgroup TIM_Flag_definition
631 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
632 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
633 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
634 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
635 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
636 #define TIM_FLAG_COM (TIM_SR_COMIF)
637 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
638 #define TIM_FLAG_BREAK (TIM_SR_BIF)
639 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
640 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
641 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
642 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
644 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
645 ((FLAG) == TIM_FLAG_CC1) || \
646 ((FLAG) == TIM_FLAG_CC2) || \
647 ((FLAG) == TIM_FLAG_CC3) || \
648 ((FLAG) == TIM_FLAG_CC4) || \
649 ((FLAG) == TIM_FLAG_COM) || \
650 ((FLAG) == TIM_FLAG_TRIGGER) || \
651 ((FLAG) == TIM_FLAG_BREAK) || \
652 ((FLAG) == TIM_FLAG_CC1OF) || \
653 ((FLAG) == TIM_FLAG_CC2OF) || \
654 ((FLAG) == TIM_FLAG_CC3OF) || \
655 ((FLAG) == TIM_FLAG_CC4OF))
660 /** @defgroup TIM_Clock_Source
663 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
664 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
665 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
666 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
667 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
668 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
669 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
670 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
671 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
672 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
674 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
675 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
676 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
677 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
678 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
679 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
680 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
681 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
682 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
683 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
688 /** @defgroup TIM_Clock_Polarity
691 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
692 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
693 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
694 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
695 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
697 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
698 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
699 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
700 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
701 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
706 /** @defgroup TIM_Clock_Prescaler
709 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
710 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
711 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
712 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
714 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
715 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
716 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
717 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
722 /** @defgroup TIM_Clock_Filter
725 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
730 /** @defgroup TIM_ClearInput_Source
733 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
734 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
736 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
737 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
742 /** @defgroup TIM_ClearInput_Polarity
745 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
746 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
747 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
748 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
753 /** @defgroup TIM_ClearInput_Prescaler
756 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
757 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
758 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
759 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
760 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
761 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
762 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
763 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
768 /** @defgroup TIM_ClearInput_Filter
771 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
776 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
779 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
780 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
782 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
783 ((STATE) == TIM_OSSR_DISABLE))
788 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
791 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
792 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
794 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
795 ((STATE) == TIM_OSSI_DISABLE))
799 /** @defgroup TIM_Lock_level
802 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
803 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
804 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
805 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
807 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
808 ((LEVEL) == TIM_LOCKLEVEL_1) || \
809 ((LEVEL) == TIM_LOCKLEVEL_2) || \
810 ((LEVEL) == TIM_LOCKLEVEL_3))
814 /** @defgroup TIM_Break_Input_enable_disable
817 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
818 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
820 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
821 ((STATE) == TIM_BREAK_DISABLE))
825 /** @defgroup TIM_Break_Polarity
828 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
829 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
831 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
832 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
836 /** @defgroup TIM_AOE_Bit_Set_Reset
839 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
840 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
842 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
843 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
848 /** @defgroup TIM_Master_Mode_Selection
851 #define TIM_TRGO_RESET ((uint32_t)0x0000)
852 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
853 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
854 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
855 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
856 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
857 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
858 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
860 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
861 ((SOURCE) == TIM_TRGO_ENABLE) || \
862 ((SOURCE) == TIM_TRGO_UPDATE) || \
863 ((SOURCE) == TIM_TRGO_OC1) || \
864 ((SOURCE) == TIM_TRGO_OC1REF) || \
865 ((SOURCE) == TIM_TRGO_OC2REF) || \
866 ((SOURCE) == TIM_TRGO_OC3REF) || \
867 ((SOURCE) == TIM_TRGO_OC4REF))
873 /** @defgroup TIM_Slave_Mode
876 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
877 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
878 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
879 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
880 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
882 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
883 ((MODE) == TIM_SLAVEMODE_GATED) || \
884 ((MODE) == TIM_SLAVEMODE_RESET) || \
885 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
886 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
891 /** @defgroup TIM_Master_Slave_Mode
895 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
896 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
897 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
898 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
902 /** @defgroup TIM_Trigger_Selection
905 #define TIM_TS_ITR0 ((uint32_t)0x0000)
906 #define TIM_TS_ITR1 ((uint32_t)0x0010)
907 #define TIM_TS_ITR2 ((uint32_t)0x0020)
908 #define TIM_TS_ITR3 ((uint32_t)0x0030)
909 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
910 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
911 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
912 #define TIM_TS_ETRF ((uint32_t)0x0070)
913 #define TIM_TS_NONE ((uint32_t)0xFFFF)
914 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
915 ((SELECTION) == TIM_TS_ITR1) || \
916 ((SELECTION) == TIM_TS_ITR2) || \
917 ((SELECTION) == TIM_TS_ITR3) || \
918 ((SELECTION) == TIM_TS_TI1F_ED) || \
919 ((SELECTION) == TIM_TS_TI1FP1) || \
920 ((SELECTION) == TIM_TS_TI2FP2) || \
921 ((SELECTION) == TIM_TS_ETRF))
922 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
923 ((SELECTION) == TIM_TS_ITR1) || \
924 ((SELECTION) == TIM_TS_ITR2) || \
925 ((SELECTION) == TIM_TS_ITR3))
926 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
927 ((SELECTION) == TIM_TS_ITR1) || \
928 ((SELECTION) == TIM_TS_ITR2) || \
929 ((SELECTION) == TIM_TS_ITR3) || \
930 ((SELECTION) == TIM_TS_NONE))
935 /** @defgroup TIM_Trigger_Polarity
938 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
939 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
940 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
941 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
942 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
944 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
945 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
946 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
947 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
948 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
953 /** @defgroup TIM_Trigger_Prescaler
956 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
957 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
958 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
959 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
961 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
962 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
963 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
964 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
969 /** @defgroup TIM_Trigger_Filter
972 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
977 /** @defgroup TIM_TI1_Selection
980 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
981 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
983 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
984 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
989 /** @defgroup TIM_DMA_Base_address
992 #define TIM_DMABase_CR1 (0x00000000)
993 #define TIM_DMABase_CR2 (0x00000001)
994 #define TIM_DMABase_SMCR (0x00000002)
995 #define TIM_DMABase_DIER (0x00000003)
996 #define TIM_DMABase_SR (0x00000004)
997 #define TIM_DMABase_EGR (0x00000005)
998 #define TIM_DMABase_CCMR1 (0x00000006)
999 #define TIM_DMABase_CCMR2 (0x00000007)
1000 #define TIM_DMABase_CCER (0x00000008)
1001 #define TIM_DMABase_CNT (0x00000009)
1002 #define TIM_DMABase_PSC (0x0000000A)
1003 #define TIM_DMABase_ARR (0x0000000B)
1004 #define TIM_DMABase_RCR (0x0000000C)
1005 #define TIM_DMABase_CCR1 (0x0000000D)
1006 #define TIM_DMABase_CCR2 (0x0000000E)
1007 #define TIM_DMABase_CCR3 (0x0000000F)
1008 #define TIM_DMABase_CCR4 (0x00000010)
1009 #define TIM_DMABase_BDTR (0x00000011)
1010 #define TIM_DMABase_DCR (0x00000012)
1011 #define TIM_DMABase_OR (0x00000013)
1012 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
1013 ((BASE) == TIM_DMABase_CR2) || \
1014 ((BASE) == TIM_DMABase_SMCR) || \
1015 ((BASE) == TIM_DMABase_DIER) || \
1016 ((BASE) == TIM_DMABase_SR) || \
1017 ((BASE) == TIM_DMABase_EGR) || \
1018 ((BASE) == TIM_DMABase_CCMR1) || \
1019 ((BASE) == TIM_DMABase_CCMR2) || \
1020 ((BASE) == TIM_DMABase_CCER) || \
1021 ((BASE) == TIM_DMABase_CNT) || \
1022 ((BASE) == TIM_DMABase_PSC) || \
1023 ((BASE) == TIM_DMABase_ARR) || \
1024 ((BASE) == TIM_DMABase_RCR) || \
1025 ((BASE) == TIM_DMABase_CCR1) || \
1026 ((BASE) == TIM_DMABase_CCR2) || \
1027 ((BASE) == TIM_DMABase_CCR3) || \
1028 ((BASE) == TIM_DMABase_CCR4) || \
1029 ((BASE) == TIM_DMABase_BDTR) || \
1030 ((BASE) == TIM_DMABase_DCR) || \
1031 ((BASE) == TIM_DMABase_OR))
1036 /** @defgroup TIM_DMA_Burst_Length
1039 #define TIM_DMABurstLength_1Transfer (0x00000000)
1040 #define TIM_DMABurstLength_2Transfers (0x00000100)
1041 #define TIM_DMABurstLength_3Transfers (0x00000200)
1042 #define TIM_DMABurstLength_4Transfers (0x00000300)
1043 #define TIM_DMABurstLength_5Transfers (0x00000400)
1044 #define TIM_DMABurstLength_6Transfers (0x00000500)
1045 #define TIM_DMABurstLength_7Transfers (0x00000600)
1046 #define TIM_DMABurstLength_8Transfers (0x00000700)
1047 #define TIM_DMABurstLength_9Transfers (0x00000800)
1048 #define TIM_DMABurstLength_10Transfers (0x00000900)
1049 #define TIM_DMABurstLength_11Transfers (0x00000A00)
1050 #define TIM_DMABurstLength_12Transfers (0x00000B00)
1051 #define TIM_DMABurstLength_13Transfers (0x00000C00)
1052 #define TIM_DMABurstLength_14Transfers (0x00000D00)
1053 #define TIM_DMABurstLength_15Transfers (0x00000E00)
1054 #define TIM_DMABurstLength_16Transfers (0x00000F00)
1055 #define TIM_DMABurstLength_17Transfers (0x00001000)
1056 #define TIM_DMABurstLength_18Transfers (0x00001100)
1057 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
1058 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
1059 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
1060 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
1061 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
1062 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
1063 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
1064 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
1065 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
1066 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
1067 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
1068 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
1069 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
1070 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
1071 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
1072 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
1073 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
1074 ((LENGTH) == TIM_DMABurstLength_18Transfers))
1079 /** @defgroup TIM_Input_Capture_Filer_Value
1082 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
1087 /** @defgroup DMA_Handle_index
1090 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
1091 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1092 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1093 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1094 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1095 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
1096 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
1101 /** @defgroup Channel_CC_State
1104 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
1105 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
1106 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
1107 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
1116 /* Exported macro ------------------------------------------------------------*/
1118 /** @brief Reset TIM handle state
1119 * @param __HANDLE__: TIM handle
1122 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1125 * @brief Enable the TIM peripheral.
1126 * @param __HANDLE__: TIM handle
1129 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1132 * @brief Enable the TIM main Output.
1133 * @param __HANDLE__: TIM handle
1136 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1139 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1140 channels have been disabled */
1141 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1142 #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1145 * @brief Disable the TIM peripheral.
1146 * @param __HANDLE__: TIM handle
1149 #define __HAL_TIM_DISABLE(__HANDLE__) \
1151 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
1153 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
1155 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1160 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
1161 channels have been disabled */
1163 * @brief Disable the TIM main Output.
1164 * @param __HANDLE__: TIM handle
1167 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1169 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
1171 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
1173 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1178 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1179 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1180 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1181 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1182 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1183 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1185 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1186 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1188 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1189 #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1191 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
1192 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1193 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
1194 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1195 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
1197 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
1198 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1199 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1200 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1201 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1204 * @brief Sets the TIM Capture Compare Register value on runtime without
1205 * calling another time ConfigChannel function.
1206 * @param __HANDLE__: TIM handle.
1207 * @param __CHANNEL__ : TIM Channels to be configured.
1208 * This parameter can be one of the following values:
1209 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1210 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1211 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1212 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1213 * @param __COMPARE__: specifies the Capture Compare register new value.
1216 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
1217 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
1220 * @brief Gets the TIM Capture Compare Register value on runtime
1221 * @param __HANDLE__: TIM handle.
1222 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
1223 * This parameter can be one of the following values:
1224 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1225 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1226 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1227 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1230 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
1231 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
1234 * @brief Sets the TIM Counter Register value on runtime.
1235 * @param __HANDLE__: TIM handle.
1236 * @param __COUNTER__: specifies the Counter register new value.
1239 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1242 * @brief Gets the TIM Counter Register value on runtime.
1243 * @param __HANDLE__: TIM handle.
1246 #define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1249 * @brief Sets the TIM Autoreload Register value on runtime without calling
1250 * another time any Init function.
1251 * @param __HANDLE__: TIM handle.
1252 * @param __AUTORELOAD__: specifies the Counter register new value.
1255 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
1257 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1258 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1261 * @brief Gets the TIM Autoreload Register value on runtime
1262 * @param __HANDLE__: TIM handle.
1265 #define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1268 * @brief Sets the TIM Clock Division value on runtime without calling
1269 * another time any Init function.
1270 * @param __HANDLE__: TIM handle.
1271 * @param __CKD__: specifies the clock division value.
1272 * This parameter can be one of the following value:
1273 * @arg TIM_CLOCKDIVISION_DIV1
1274 * @arg TIM_CLOCKDIVISION_DIV2
1275 * @arg TIM_CLOCKDIVISION_DIV4
1278 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
1280 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1281 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1282 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1285 * @brief Gets the TIM Clock Division value on runtime
1286 * @param __HANDLE__: TIM handle.
1289 #define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1292 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1293 * another time HAL_TIM_IC_ConfigChannel() function.
1294 * @param __HANDLE__: TIM handle.
1295 * @param __CHANNEL__ : TIM Channels to be configured.
1296 * This parameter can be one of the following values:
1297 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1298 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1299 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1300 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1301 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1302 * This parameter can be one of the following values:
1303 * @arg TIM_ICPSC_DIV1: no prescaler
1304 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1305 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1306 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1309 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
1311 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
1312 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1316 * @brief Gets the TIM Input Capture prescaler on runtime
1317 * @param __HANDLE__: TIM handle.
1318 * @param __CHANNEL__ : TIM Channels to be configured.
1319 * This parameter can be one of the following values:
1320 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1321 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1322 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1323 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1326 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
1327 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1328 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1329 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1330 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1335 /* Include TIM HAL Extension module */
1336 #include "stm32f4xx_hal_tim_ex.h"
1338 /* Exported functions --------------------------------------------------------*/
1340 /* Time Base functions ********************************************************/
1341 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1342 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1343 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1344 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1345 /* Blocking mode: Polling */
1346 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1347 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1348 /* Non-Blocking mode: Interrupt */
1349 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1350 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1351 /* Non-Blocking mode: DMA */
1352 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1353 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1355 /* Timer Output Compare functions **********************************************/
1356 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1357 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1358 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1359 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1360 /* Blocking mode: Polling */
1361 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1362 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1363 /* Non-Blocking mode: Interrupt */
1364 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1365 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1366 /* Non-Blocking mode: DMA */
1367 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1368 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1370 /* Timer PWM functions *********************************************************/
1371 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1372 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1373 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1374 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1375 /* Blocking mode: Polling */
1376 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1377 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1378 /* Non-Blocking mode: Interrupt */
1379 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1380 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1381 /* Non-Blocking mode: DMA */
1382 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1383 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1385 /* Timer Input Capture functions ***********************************************/
1386 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1387 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1388 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1389 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1390 /* Blocking mode: Polling */
1391 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1392 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1393 /* Non-Blocking mode: Interrupt */
1394 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1395 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1396 /* Non-Blocking mode: DMA */
1397 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1398 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1400 /* Timer One Pulse functions ***************************************************/
1401 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1402 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1403 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1404 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1405 /* Blocking mode: Polling */
1406 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1407 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1409 /* Non-Blocking mode: Interrupt */
1410 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1411 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1413 /* Timer Encoder functions *****************************************************/
1414 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1415 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1416 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1417 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1418 /* Blocking mode: Polling */
1419 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1420 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1421 /* Non-Blocking mode: Interrupt */
1422 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1423 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1424 /* Non-Blocking mode: DMA */
1425 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1426 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1428 /* Interrupt Handler functions **********************************************/
1429 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1431 /* Control functions *********************************************************/
1432 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1433 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1434 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1435 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1436 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1437 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1438 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1439 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1440 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1441 uint32_t *BurstBuffer, uint32_t BurstLength);
1442 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1443 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1444 uint32_t *BurstBuffer, uint32_t BurstLength);
1445 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1446 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1447 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1449 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1450 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1451 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1452 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1453 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1454 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1455 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1457 /* Peripheral State functions **************************************************/
1458 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1459 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1460 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1461 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1462 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1463 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1465 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1466 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1467 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1468 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1469 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
1470 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1471 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1485 #endif /* __STM32F4xx_HAL_TIM_H */
1487 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/