2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.h
4 * @author MCD Application Team
7 * @brief Header file of FMC HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FMC_H
40 #define __STM32F4xx_LL_FMC_H
46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f4xx_hal_def.h"
51 /** @addtogroup STM32F4xx_HAL_Driver
59 /* Exported typedef ----------------------------------------------------------*/
60 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
61 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
62 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
63 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
64 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
66 #define FMC_NORSRAM_DEVICE FMC_Bank1
67 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
68 #define FMC_NAND_DEVICE FMC_Bank2_3
69 #define FMC_PCCARD_DEVICE FMC_Bank4
70 #define FMC_SDRAM_DEVICE FMC_Bank5_6
73 * @brief FMC_NORSRAM Configuration Structure definition
77 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
78 This parameter can be a value of @ref FMC_NORSRAM_Bank */
80 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
81 multiplexed on the data bus or not.
82 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
84 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
85 the corresponding memory device.
86 This parameter can be a value of @ref FMC_Memory_Type */
88 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
89 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
91 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
92 valid only with synchronous burst Flash memories.
93 This parameter can be a value of @ref FMC_Burst_Access_Mode */
95 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
96 the Flash memory in burst mode.
97 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
99 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
100 memory, valid only when accessing Flash memories in burst mode.
101 This parameter can be a value of @ref FMC_Wrap_Mode */
103 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
104 clock cycle before the wait state or during the wait state,
105 valid only when accessing memories in burst mode.
106 This parameter can be a value of @ref FMC_Wait_Timing */
108 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
109 This parameter can be a value of @ref FMC_Write_Operation */
111 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
112 signal, valid for Flash memory access in burst mode.
113 This parameter can be a value of @ref FMC_Wait_Signal */
115 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
116 This parameter can be a value of @ref FMC_Extended_Mode */
118 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
119 valid only with asynchronous Flash memories.
120 This parameter can be a value of @ref FMC_AsynchronousWait */
122 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
123 This parameter can be a value of @ref FMC_Write_Burst */
125 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
126 This parameter is only enabled through the FMC_BCR1 register, and don't care
127 through FMC_BCR2..4 registers.
128 This parameter can be a value of @ref FMC_Continous_Clock */
130 }FMC_NORSRAM_InitTypeDef;
133 * @brief FMC_NORSRAM Timing parameters structure definition
137 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
138 the duration of the address setup time.
139 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
140 @note This parameter is not used with synchronous NOR Flash memories. */
142 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
143 the duration of the address hold time.
144 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
145 @note This parameter is not used with synchronous NOR Flash memories. */
147 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
148 the duration of the data setup time.
149 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
150 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
151 NOR Flash memories. */
153 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
154 the duration of the bus turnaround.
155 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
156 @note This parameter is only used for multiplexed NOR Flash memories. */
158 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
159 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
160 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
163 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
164 to the memory before getting the first data.
165 The parameter value depends on the memory type as shown below:
166 - It must be set to 0 in case of a CRAM
167 - It is don't care in asynchronous NOR, SRAM or ROM accesses
168 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
169 with synchronous burst mode enable */
171 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
172 This parameter can be a value of @ref FMC_Access_Mode */
173 }FMC_NORSRAM_TimingTypeDef;
176 * @brief FMC_NAND Configuration Structure definition
180 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
181 This parameter can be a value of @ref FMC_NAND_Bank */
183 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
184 This parameter can be any value of @ref FMC_Wait_feature */
186 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
187 This parameter can be any value of @ref FMC_NAND_Data_Width */
189 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
190 This parameter can be any value of @ref FMC_ECC */
192 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
193 This parameter can be any value of @ref FMC_ECC_Page_Size */
195 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
196 delay between CLE low and RE low.
197 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
199 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
200 delay between ALE low and RE low.
201 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
202 }FMC_NAND_InitTypeDef;
205 * @brief FMC_NAND_PCCARD Timing parameters structure definition
209 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
210 the command assertion for NAND-Flash read or write access
211 to common/Attribute or I/O memory space (depending on
212 the memory space timing to be configured).
213 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
215 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
216 command for NAND-Flash read or write access to
217 common/Attribute or I/O memory space (depending on the
218 memory space timing to be configured).
219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
221 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
222 (and data for write access) after the command de-assertion
223 for NAND-Flash read or write access to common/Attribute
224 or I/O memory space (depending on the memory space timing
226 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
228 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
229 data bus is kept in HiZ after the start of a NAND-Flash
230 write access to common/Attribute or I/O memory space (depending
231 on the memory space timing to be configured).
232 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
233 }FMC_NAND_PCC_TimingTypeDef;
236 * @brief FMC_NAND Configuration Structure definition
240 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
241 This parameter can be any value of @ref FMC_Wait_feature */
243 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
244 delay between CLE low and RE low.
245 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
247 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
248 delay between ALE low and RE low.
249 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
250 }FMC_PCCARD_InitTypeDef;
253 * @brief FMC_SDRAM Configuration Structure definition
257 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
258 This parameter can be a value of @ref FMC_SDRAM_Bank */
260 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
261 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
263 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
264 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
266 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
267 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
269 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
270 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
272 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
273 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
275 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
276 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
278 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
279 to disable the clock before changing frequency.
280 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
282 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
283 commands during the CAS latency and stores data in the Read FIFO.
284 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
286 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
287 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
288 }FMC_SDRAM_InitTypeDef;
291 * @brief FMC_SDRAM Timing parameters structure definition
295 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
296 an active or Refresh command in number of memory clock cycles.
297 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
299 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
300 issuing the Activate command in number of memory clock cycles.
301 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
303 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
305 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
307 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
308 and the delay between two consecutive Refresh commands in number of
310 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
312 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
313 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
315 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
316 in number of memory clock cycles.
317 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
319 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
320 command in number of memory clock cycles.
321 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
322 }FMC_SDRAM_TimingTypeDef;
325 * @brief SDRAM command parameters structure definition
329 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
330 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
332 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
333 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
335 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
336 in auto refresh mode.
337 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
338 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
339 }FMC_SDRAM_CommandTypeDef;
341 /* Exported constants --------------------------------------------------------*/
343 /** @defgroup FMC_NOR_SRAM_Controller
347 /** @defgroup FMC_NORSRAM_Bank
350 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
351 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
352 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
353 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
355 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
356 ((BANK) == FMC_NORSRAM_BANK2) || \
357 ((BANK) == FMC_NORSRAM_BANK3) || \
358 ((BANK) == FMC_NORSRAM_BANK4))
363 /** @defgroup FMC_Data_Address_Bus_Multiplexing
366 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
367 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
369 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
370 ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
375 /** @defgroup FMC_Memory_Type
378 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
379 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
380 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
382 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
383 ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
384 ((MEMORY) == FMC_MEMORY_TYPE_NOR))
389 /** @defgroup FMC_NORSRAM_Data_Width
392 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
393 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
394 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
396 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
397 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
398 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
403 /** @defgroup FMC_NORSRAM_Flash_Access
406 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
407 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
412 /** @defgroup FMC_Burst_Access_Mode
415 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
416 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
418 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
419 ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
425 /** @defgroup FMC_Wait_Signal_Polarity
428 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
429 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
431 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
432 ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
437 /** @defgroup FMC_Wrap_Mode
440 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
441 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
443 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
444 ((MODE) == FMC_WRAP_MODE_ENABLE))
449 /** @defgroup FMC_Wait_Timing
452 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
453 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
455 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
456 ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
461 /** @defgroup FMC_Write_Operation
464 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
465 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
467 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
468 ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
473 /** @defgroup FMC_Wait_Signal
476 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
477 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
479 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
480 ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
485 /** @defgroup FMC_Extended_Mode
488 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
489 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
491 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
492 ((MODE) == FMC_EXTENDED_MODE_ENABLE))
497 /** @defgroup FMC_AsynchronousWait
500 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
501 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
503 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
504 ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
509 /** @defgroup FMC_Write_Burst
512 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
513 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
515 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
516 ((BURST) == FMC_WRITE_BURST_ENABLE))
521 /** @defgroup FMC_Continous_Clock
524 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
525 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
527 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
528 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
533 /** @defgroup FMC_Address_Setup_Time
536 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
541 /** @defgroup FMC_Address_Hold_Time
544 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
549 /** @defgroup FMC_Data_Setup_Time
552 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
557 /** @defgroup FMC_Bus_Turn_around_Duration
560 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
565 /** @defgroup FMC_CLK_Division
568 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
573 /** @defgroup FMC_Data_Latency
576 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
581 /** @defgroup FMC_Access_Mode
584 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
585 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
586 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
587 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
589 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
590 ((MODE) == FMC_ACCESS_MODE_B) || \
591 ((MODE) == FMC_ACCESS_MODE_C) || \
592 ((MODE) == FMC_ACCESS_MODE_D))
601 /** @defgroup FMC_NAND_Controller
605 /** @defgroup FMC_NAND_Bank
608 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
609 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
611 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
612 ((BANK) == FMC_NAND_BANK3))
617 /** @defgroup FMC_Wait_feature
620 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
621 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
623 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
624 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
629 /** @defgroup FMC_PCR_Memory_Type
632 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
633 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
638 /** @defgroup FMC_NAND_Data_Width
641 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
642 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
644 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
645 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
650 /** @defgroup FMC_ECC
653 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
654 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
656 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
657 ((STATE) == FMC_NAND_ECC_ENABLE))
662 /** @defgroup FMC_ECC_Page_Size
665 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
666 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
667 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
668 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
669 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
670 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
672 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
673 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
674 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
675 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
676 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
677 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
682 /** @defgroup FMC_TCLR_Setup_Time
685 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
690 /** @defgroup FMC_TAR_Setup_Time
693 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
698 /** @defgroup FMC_Setup_Time
701 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
706 /** @defgroup FMC_Wait_Setup_Time
709 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
714 /** @defgroup FMC_Hold_Setup_Time
717 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
722 /** @defgroup FMC_HiZ_Setup_Time
725 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
734 /** @defgroup FMC_SDRAM_Controller
738 /** @defgroup FMC_SDRAM_Bank
741 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
742 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
744 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
745 ((BANK) == FMC_SDRAM_BANK2))
750 /** @defgroup FMC_SDRAM_Column_Bits_number
753 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
754 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
755 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
756 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
758 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
759 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
760 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
761 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
766 /** @defgroup FMC_SDRAM_Row_Bits_number
769 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
770 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
771 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
773 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
774 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
775 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
780 /** @defgroup FMC_SDRAM_Memory_Bus_Width
783 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
784 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
785 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
787 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
788 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
789 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
794 /** @defgroup FMC_SDRAM_Internal_Banks_Number
797 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
798 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
800 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
801 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
806 /** @defgroup FMC_SDRAM_CAS_Latency
809 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
810 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
811 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
813 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
814 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
815 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
820 /** @defgroup FMC_SDRAM_Write_Protection
823 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
824 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
826 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
827 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
832 /** @defgroup FMC_SDRAM_Clock_Period
835 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
836 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
837 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
839 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
840 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
841 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
846 /** @defgroup FMC_SDRAM_Read_Burst
849 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
850 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
852 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
853 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
858 /** @defgroup FMC_SDRAM_Read_Pipe_Delay
861 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
862 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
863 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
865 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
866 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
867 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
872 /** @defgroup FMC_SDRAM_LoadToActive_Delay
875 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
880 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
883 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
888 /** @defgroup FMC_SDRAM_SelfRefresh_Time
891 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
896 /** @defgroup FMC_SDRAM_RowCycle_Delay
899 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
904 /** @defgroup FMC_SDRAM_Write_Recovery_Time
907 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
912 /** @defgroup FMC_SDRAM_RP_Delay
915 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
920 /** @defgroup FMC_SDRAM_RCD_Delay
923 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
929 /** @defgroup FMC_SDRAM_Command_Mode
932 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
933 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
934 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
935 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
936 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
937 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
938 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
940 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
941 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
942 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
943 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
944 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
945 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
946 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
951 /** @defgroup FMC_SDRAM_Command_Target
954 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
955 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
956 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
958 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
959 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
960 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
965 /** @defgroup FMC_SDRAM_AutoRefresh_Number
968 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
973 /** @defgroup FMC_SDRAM_ModeRegister_Definition
976 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
981 /** @defgroup FMC_SDRAM_Refresh_rate
984 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
989 /** @defgroup FMC_SDRAM_Mode_Status
992 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
993 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
994 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
999 /** @defgroup FMC_NORSRAM_Device_Instance
1002 #define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
1007 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
1010 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
1015 /** @defgroup FMC_NAND_Device_Instance
1018 #define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
1023 /** @defgroup FMC_PCCARD_Device_Instance
1026 #define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
1031 /** @defgroup FMC_SDRAM_Device_Instance
1034 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
1043 /** @defgroup FMC_Interrupt_definition
1044 * @brief FMC Interrupt definition
1047 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
1048 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
1049 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
1050 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
1052 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
1054 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
1055 ((IT) == FMC_IT_LEVEL) || \
1056 ((IT) == FMC_IT_FALLING_EDGE) || \
1057 ((IT) == FMC_IT_REFRESH_ERROR))
1062 /** @defgroup FMC_Flag_definition
1063 * @brief FMC Flag definition
1066 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
1067 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
1068 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
1069 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
1070 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
1071 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
1072 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
1074 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
1075 ((FLAG) == FMC_FLAG_LEVEL) || \
1076 ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
1077 ((FLAG) == FMC_FLAG_FEMPT) || \
1078 ((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) || \
1079 ((FLAG) == FMC_SDRAM_FLAG_BUSY))
1081 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
1086 /* Exported macro ------------------------------------------------------------*/
1088 /** @defgroup FMC_NOR_Macros
1089 * @brief macros to handle NOR device enable/disable and read/write operations
1094 * @brief Enable the NORSRAM device access.
1095 * @param __INSTANCE__: FMC_NORSRAM Instance
1096 * @param __BANK__: FMC_NORSRAM Bank
1099 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
1102 * @brief Disable the NORSRAM device access.
1103 * @param __INSTANCE__: FMC_NORSRAM Instance
1104 * @param __BANK__: FMC_NORSRAM Bank
1107 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
1113 /** @defgroup FMC_NAND_Macros
1114 * @brief macros to handle NAND device enable/disable
1119 * @brief Enable the NAND device access.
1120 * @param __INSTANCE__: FMC_NAND Instance
1121 * @param __BANK__: FMC_NAND Bank
1124 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
1125 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
1128 * @brief Disable the NAND device access.
1129 * @param __INSTANCE__: FMC_NAND Instance
1130 * @param __BANK__: FMC_NAND Bank
1133 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
1134 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
1139 /** @defgroup FMC_PCCARD_Macros
1140 * @brief macros to handle SRAM read/write operations
1145 * @brief Enable the PCCARD device access.
1146 * @param __INSTANCE__: FMC_PCCARD Instance
1149 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
1152 * @brief Disable the PCCARD device access.
1153 * @param __INSTANCE__: FMC_PCCARD Instance
1156 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
1161 /** @defgroup FMC_Interrupt
1162 * @brief macros to handle FMC interrupts
1167 * @brief Enable the NAND device interrupt.
1168 * @param __INSTANCE__: FMC_NAND instance
1169 * @param __BANK__: FMC_NAND Bank
1170 * @param __INTERRUPT__: FMC_NAND interrupt
1171 * This parameter can be any combination of the following values:
1172 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1173 * @arg FMC_IT_LEVEL: Interrupt level.
1174 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1177 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
1178 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
1181 * @brief Disable the NAND device interrupt.
1182 * @param __INSTANCE__: FMC_NAND handle
1183 * @param __BANK__: FMC_NAND Bank
1184 * @param __INTERRUPT__: FMC_NAND interrupt
1185 * This parameter can be any combination of the following values:
1186 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1187 * @arg FMC_IT_LEVEL: Interrupt level.
1188 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1191 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
1192 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
1195 * @brief Get flag status of the NAND device.
1196 * @param __INSTANCE__: FMC_NAND handle
1197 * @param __BANK__: FMC_NAND Bank
1198 * @param __FLAG__: FMC_NAND flag
1199 * This parameter can be any combination of the following values:
1200 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1201 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1202 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1203 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1204 * @retval The state of FLAG (SET or RESET).
1206 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
1207 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
1209 * @brief Clear flag status of the NAND device.
1210 * @param __INSTANCE__: FMC_NAND handle
1211 * @param __BANK__: FMC_NAND Bank
1212 * @param __FLAG__: FMC_NAND flag
1213 * This parameter can be any combination of the following values:
1214 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1215 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1216 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1217 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1220 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
1221 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
1223 * @brief Enable the PCCARD device interrupt.
1224 * @param __INSTANCE__: FMC_PCCARD instance
1225 * @param __INTERRUPT__: FMC_PCCARD interrupt
1226 * This parameter can be any combination of the following values:
1227 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1228 * @arg FMC_IT_LEVEL: Interrupt level.
1229 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1232 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
1235 * @brief Disable the PCCARD device interrupt.
1236 * @param __INSTANCE__: FMC_PCCARD instance
1237 * @param __INTERRUPT__: FMC_PCCARD interrupt
1238 * This parameter can be any combination of the following values:
1239 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1240 * @arg FMC_IT_LEVEL: Interrupt level.
1241 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1244 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1247 * @brief Get flag status of the PCCARD device.
1248 * @param __INSTANCE__: FMC_PCCARD instance
1249 * @param __FLAG__: FMC_PCCARD flag
1250 * This parameter can be any combination of the following values:
1251 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1252 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1253 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1254 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1255 * @retval The state of FLAG (SET or RESET).
1257 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1260 * @brief Clear flag status of the PCCARD device.
1261 * @param __INSTANCE__: FMC_PCCARD instance
1262 * @param __FLAG__: FMC_PCCARD flag
1263 * This parameter can be any combination of the following values:
1264 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1265 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1266 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1267 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1270 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1273 * @brief Enable the SDRAM device interrupt.
1274 * @param __INSTANCE__: FMC_SDRAM instance
1275 * @param __INTERRUPT__: FMC_SDRAM interrupt
1276 * This parameter can be any combination of the following values:
1277 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1280 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1283 * @brief Disable the SDRAM device interrupt.
1284 * @param __INSTANCE__: FMC_SDRAM instance
1285 * @param __INTERRUPT__: FMC_SDRAM interrupt
1286 * This parameter can be any combination of the following values:
1287 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1290 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1293 * @brief Get flag status of the SDRAM device.
1294 * @param __INSTANCE__: FMC_SDRAM instance
1295 * @param __FLAG__: FMC_SDRAM flag
1296 * This parameter can be any combination of the following values:
1297 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1298 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1299 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1300 * @retval The state of FLAG (SET or RESET).
1302 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1305 * @brief Clear flag status of the SDRAM device.
1306 * @param __INSTANCE__: FMC_SDRAM instance
1307 * @param __FLAG__: FMC_SDRAM flag
1308 * This parameter can be any combination of the following values:
1309 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1312 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1317 /* Exported functions --------------------------------------------------------*/
1319 /* FMC_NORSRAM Controller functions *******************************************/
1320 /* Initialization/de-initialization functions */
1321 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1322 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1323 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1324 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1326 /* FMC_NORSRAM Control functions */
1327 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1328 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1330 /* FMC_NAND Controller functions **********************************************/
1331 /* Initialization/de-initialization functions */
1332 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1333 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1334 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1335 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1337 /* FMC_NAND Control functions */
1338 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1339 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1340 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1342 /* FMC_PCCARD Controller functions ********************************************/
1343 /* Initialization/de-initialization functions */
1344 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1345 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1346 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1347 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1348 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1350 /* FMC_SDRAM Controller functions *********************************************/
1351 /* Initialization/de-initialization functions */
1352 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1353 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1354 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1356 /* FMC_SDRAM Control functions */
1357 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1358 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1359 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1360 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1361 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1362 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1364 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1377 #endif /* __STM32F4xx_LL_FMC_H */
1379 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/