2 ******************************************************************************
3 * @file stm32f4xx_ll_fsmc.h
4 * @author MCD Application Team
7 * @brief Header file of FSMC HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FSMC_H
40 #define __STM32F4xx_LL_FSMC_H
46 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f4xx_hal_def.h"
51 /** @addtogroup STM32F4xx_HAL_Driver
59 /* Exported typedef ----------------------------------------------------------*/
60 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
61 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
62 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
63 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
65 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
66 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
67 #define FSMC_NAND_DEVICE FSMC_Bank2_3
68 #define FSMC_PCCARD_DEVICE FSMC_Bank4
71 * @brief FSMC_NORSRAM Configuration Structure definition
75 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
76 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
78 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
79 multiplexed on the data bus or not.
80 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
82 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
83 the corresponding memory device.
84 This parameter can be a value of @ref FSMC_Memory_Type */
86 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
87 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
89 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
90 valid only with synchronous burst Flash memories.
91 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
93 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
94 the Flash memory in burst mode.
95 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
97 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
98 memory, valid only when accessing Flash memories in burst mode.
99 This parameter can be a value of @ref FSMC_Wrap_Mode */
101 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
102 clock cycle before the wait state or during the wait state,
103 valid only when accessing memories in burst mode.
104 This parameter can be a value of @ref FSMC_Wait_Timing */
106 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
107 This parameter can be a value of @ref FSMC_Write_Operation */
109 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
110 signal, valid for Flash memory access in burst mode.
111 This parameter can be a value of @ref FSMC_Wait_Signal */
113 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
114 This parameter can be a value of @ref FSMC_Extended_Mode */
116 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
117 valid only with asynchronous Flash memories.
118 This parameter can be a value of @ref FSMC_AsynchronousWait */
120 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
121 This parameter can be a value of @ref FSMC_Write_Burst */
123 }FSMC_NORSRAM_InitTypeDef;
126 * @brief FSMC_NORSRAM Timing parameters structure definition
130 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
131 the duration of the address setup time.
132 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
133 @note This parameter is not used with synchronous NOR Flash memories. */
135 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
136 the duration of the address hold time.
137 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
138 @note This parameter is not used with synchronous NOR Flash memories. */
140 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
141 the duration of the data setup time.
142 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
143 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
144 NOR Flash memories. */
146 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
147 the duration of the bus turnaround.
148 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
149 @note This parameter is only used for multiplexed NOR Flash memories. */
151 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
152 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
153 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
156 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
157 to the memory before getting the first data.
158 The parameter value depends on the memory type as shown below:
159 - It must be set to 0 in case of a CRAM
160 - It is don't care in asynchronous NOR, SRAM or ROM accesses
161 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
162 with synchronous burst mode enable */
164 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
165 This parameter can be a value of @ref FSMC_Access_Mode */
167 }FSMC_NORSRAM_TimingTypeDef;
170 * @brief FSMC_NAND Configuration Structure definition
174 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
175 This parameter can be a value of @ref FSMC_NAND_Bank */
177 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
178 This parameter can be any value of @ref FSMC_Wait_feature */
180 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
181 This parameter can be any value of @ref FSMC_NAND_Data_Width */
183 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
184 This parameter can be any value of @ref FSMC_ECC */
186 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
187 This parameter can be any value of @ref FSMC_ECC_Page_Size */
189 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
190 delay between CLE low and RE low.
191 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
193 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
194 delay between ALE low and RE low.
195 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
197 }FSMC_NAND_InitTypeDef;
200 * @brief FSMC_NAND_PCCARD Timing parameters structure definition
204 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
205 the command assertion for NAND-Flash read or write access
206 to common/Attribute or I/O memory space (depending on
207 the memory space timing to be configured).
208 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
210 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
211 command for NAND-Flash read or write access to
212 common/Attribute or I/O memory space (depending on the
213 memory space timing to be configured).
214 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
216 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
217 (and data for write access) after the command de-assertion
218 for NAND-Flash read or write access to common/Attribute
219 or I/O memory space (depending on the memory space timing
221 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
223 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
224 data bus is kept in HiZ after the start of a NAND-Flash
225 write access to common/Attribute or I/O memory space (depending
226 on the memory space timing to be configured).
227 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
229 }FSMC_NAND_PCC_TimingTypeDef;
232 * @brief FSMC_NAND Configuration Structure definition
236 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
237 This parameter can be any value of @ref FSMC_Wait_feature */
239 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
240 delay between CLE low and RE low.
241 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
243 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
244 delay between ALE low and RE low.
245 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
247 }FSMC_PCCARD_InitTypeDef;
249 /* Exported constants --------------------------------------------------------*/
251 /** @defgroup FSMC_NOR_SRAM_Controller
255 /** @defgroup FSMC_NORSRAM_Bank
258 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
259 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
260 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
261 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
263 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
264 ((BANK) == FSMC_NORSRAM_BANK2) || \
265 ((BANK) == FSMC_NORSRAM_BANK3) || \
266 ((BANK) == FSMC_NORSRAM_BANK4))
271 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
275 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
276 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
278 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
279 ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
284 /** @defgroup FSMC_Memory_Type
288 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
289 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
290 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
293 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
294 ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
295 ((MEMORY) == FSMC_MEMORY_TYPE_NOR))
300 /** @defgroup FSMC_NORSRAM_Data_Width
304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
306 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
308 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
309 ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
310 ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
315 /** @defgroup FSMC_NORSRAM_Flash_Access
318 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
319 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
324 /** @defgroup FSMC_Burst_Access_Mode
328 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
329 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
331 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
332 ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
338 /** @defgroup FSMC_Wait_Signal_Polarity
341 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
342 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
344 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
345 ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
350 /** @defgroup FSMC_Wrap_Mode
353 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
354 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
356 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
357 ((MODE) == FSMC_WRAP_MODE_ENABLE))
362 /** @defgroup FSMC_Wait_Timing
365 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
366 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
368 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
369 ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
374 /** @defgroup FSMC_Write_Operation
377 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
378 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
380 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
381 ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
386 /** @defgroup FSMC_Wait_Signal
389 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
390 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
392 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
393 ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
399 /** @defgroup FSMC_Extended_Mode
402 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
403 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
405 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
406 ((MODE) == FSMC_EXTENDED_MODE_ENABLE))
411 /** @defgroup FSMC_AsynchronousWait
414 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
415 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
417 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
418 ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
424 /** @defgroup FSMC_Write_Burst
428 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
429 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
431 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
432 ((BURST) == FSMC_WRITE_BURST_ENABLE))
438 /** @defgroup FSMC_Continous_Clock
442 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
443 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
445 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
446 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
452 /** @defgroup FSMC_Address_Setup_Time
455 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
460 /** @defgroup FSMC_Address_Hold_Time
463 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
468 /** @defgroup FSMC_Data_Setup_Time
471 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
476 /** @defgroup FSMC_Bus_Turn_around_Duration
479 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
484 /** @defgroup FSMC_CLK_Division
487 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
492 /** @defgroup FSMC_Data_Latency
495 #define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
500 /** @defgroup FSMC_Access_Mode
503 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
504 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
505 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
506 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
508 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
509 ((MODE) == FSMC_ACCESS_MODE_B) || \
510 ((MODE) == FSMC_ACCESS_MODE_C) || \
511 ((MODE) == FSMC_ACCESS_MODE_D))
520 /** @defgroup FSMC_NAND_Controller
524 /** @defgroup FSMC_NAND_Bank
527 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
528 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
530 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
531 ((BANK) == FSMC_NAND_BANK3))
537 /** @defgroup FSMC_Wait_feature
540 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
541 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
543 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
544 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
549 /** @defgroup FSMC_PCR_Memory_Type
552 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
553 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
558 /** @defgroup FSMC_NAND_Data_Width
561 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
562 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
564 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
565 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
570 /** @defgroup FSMC_ECC
573 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
574 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
576 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
577 ((STATE) == FSMC_NAND_ECC_ENABLE))
582 /** @defgroup FSMC_ECC_Page_Size
585 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
586 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
587 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
588 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
589 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
590 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
592 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
593 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
594 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
595 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
596 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
597 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
602 /** @defgroup FSMC_TCLR_Setup_Time
605 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
610 /** @defgroup FSMC_TAR_Setup_Time
613 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
618 /** @defgroup FSMC_Setup_Time
621 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
626 /** @defgroup FSMC_Wait_Setup_Time
629 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
634 /** @defgroup FSMC_Hold_Setup_Time
637 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
642 /** @defgroup FSMC_HiZ_Setup_Time
645 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
655 /** @defgroup FSMC_NORSRAM_Device_Instance
658 #define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
664 /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
667 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
673 /** @defgroup FSMC_NAND_Device_Instance
676 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
682 /** @defgroup FSMC_PCCARD_Device_Instance
685 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
691 /** @defgroup FSMC_Interrupt_definition
692 * @brief FSMC Interrupt definition
695 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
696 #define FSMC_IT_LEVEL ((uint32_t)0x00000010)
697 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
698 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
700 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
701 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \
702 ((IT) == FSMC_IT_LEVEL) || \
703 ((IT) == FSMC_IT_FALLING_EDGE) || \
704 ((IT) == FSMC_IT_REFRESH_ERROR))
709 /** @defgroup FSMC_Flag_definition
710 * @brief FSMC Flag definition
713 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
714 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
715 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
716 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
718 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \
719 ((FLAG) == FSMC_FLAG_LEVEL) || \
720 ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
721 ((FLAG) == FSMC_FLAG_FEMPT))
723 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
731 /* Exported macro ------------------------------------------------------------*/
734 /** @defgroup FSMC_NOR_Macros
735 * @brief macros to handle NOR device enable/disable and read/write operations
740 * @brief Enable the NORSRAM device access.
741 * @param __INSTANCE__: FSMC_NORSRAM Instance
742 * @param __BANK__: FSMC_NORSRAM Bank
745 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
748 * @brief Disable the NORSRAM device access.
749 * @param __INSTANCE__: FSMC_NORSRAM Instance
750 * @param __BANK__: FSMC_NORSRAM Bank
753 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
760 /** @defgroup FSMC_NAND_Macros
761 * @brief macros to handle NAND device enable/disable
766 * @brief Enable the NAND device access.
767 * @param __INSTANCE__: FSMC_NAND Instance
768 * @param __BANK__: FSMC_NAND Bank
771 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
772 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
776 * @brief Disable the NAND device access.
777 * @param __INSTANCE__: FSMC_NAND Instance
778 * @param __BANK__: FSMC_NAND Bank
781 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
782 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
789 /** @defgroup FSMC_PCCARD_Macros
790 * @brief macros to handle SRAM read/write operations
795 * @brief Enable the PCCARD device access.
796 * @param __INSTANCE__: FSMC_PCCARD Instance
799 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
802 * @brief Disable the PCCARD device access.
803 * @param __INSTANCE__: FSMC_PCCARD Instance
806 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
812 /** @defgroup FSMC_Interrupt
813 * @brief macros to handle FSMC interrupts
818 * @brief Enable the NAND device interrupt.
819 * @param __INSTANCE__: FSMC_NAND Instance
820 * @param __BANK__: FSMC_NAND Bank
821 * @param __INTERRUPT__: FSMC_NAND interrupt
822 * This parameter can be any combination of the following values:
823 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
824 * @arg FSMC_IT_LEVEL: Interrupt level.
825 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
828 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
829 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
832 * @brief Disable the NAND device interrupt.
833 * @param __INSTANCE__: FSMC_NAND Instance
834 * @param __BANK__: FSMC_NAND Bank
835 * @param __INTERRUPT__: FSMC_NAND interrupt
836 * This parameter can be any combination of the following values:
837 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
838 * @arg FSMC_IT_LEVEL: Interrupt level.
839 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
842 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
843 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
846 * @brief Get flag status of the NAND device.
847 * @param __INSTANCE__: FSMC_NAND Instance
848 * @param __BANK__: FSMC_NAND Bank
849 * @param __FLAG__: FSMC_NAND flag
850 * This parameter can be any combination of the following values:
851 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
852 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
853 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
854 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
855 * @retval The state of FLAG (SET or RESET).
857 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
858 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
860 * @brief Clear flag status of the NAND device.
861 * @param __INSTANCE__: FSMC_NAND Instance
862 * @param __BANK__: FSMC_NAND Bank
863 * @param __FLAG__: FSMC_NAND flag
864 * This parameter can be any combination of the following values:
865 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
866 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
867 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
868 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
871 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
872 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
874 * @brief Enable the PCCARD device interrupt.
875 * @param __INSTANCE__: FSMC_PCCARD Instance
876 * @param __INTERRUPT__: FSMC_PCCARD interrupt
877 * This parameter can be any combination of the following values:
878 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
879 * @arg FSMC_IT_LEVEL: Interrupt level.
880 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
883 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
886 * @brief Disable the PCCARD device interrupt.
887 * @param __INSTANCE__: FSMC_PCCARD Instance
888 * @param __INTERRUPT__: FSMC_PCCARD interrupt
889 * This parameter can be any combination of the following values:
890 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
891 * @arg FSMC_IT_LEVEL: Interrupt level.
892 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
895 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
898 * @brief Get flag status of the PCCARD device.
899 * @param __INSTANCE__: FSMC_PCCARD Instance
900 * @param __FLAG__: FSMC_PCCARD flag
901 * This parameter can be any combination of the following values:
902 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
903 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
904 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
905 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
906 * @retval The state of FLAG (SET or RESET).
908 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
911 * @brief Clear flag status of the PCCARD device.
912 * @param __INSTANCE__: FSMC_PCCARD Instance
913 * @param __FLAG__: FSMC_PCCARD flag
914 * This parameter can be any combination of the following values:
915 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
916 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
917 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
918 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
921 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
927 /* Exported functions --------------------------------------------------------*/
929 /* FSMC_NORSRAM Controller functions ******************************************/
930 /* Initialization/de-initialization functions */
931 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
932 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
933 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
934 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
936 /* FSMC_NORSRAM Control functions */
937 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
938 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
940 /* FSMC_NAND Controller functions *********************************************/
941 /* Initialization/de-initialization functions */
942 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
943 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
944 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
945 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
947 /* FSMC_NAND Control functions */
948 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
949 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
950 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
952 /* FSMC_PCCARD Controller functions *******************************************/
953 /* Initialization/de-initialization functions */
954 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
955 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
956 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
957 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
958 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
960 /* FSMC APIs, macros and typedefs redefinition */
961 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
962 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
963 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
964 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
966 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
967 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
968 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
969 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
970 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
971 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
973 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
974 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
976 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
977 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
978 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
980 #define FMC_NAND_Init FSMC_NAND_Init
981 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
982 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
983 #define FMC_NAND_DeInit FSMC_NAND_DeInit
984 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
985 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
986 #define FMC_NAND_GetECC FSMC_NAND_GetECC
987 #define FMC_PCCARD_Init FSMC_PCCARD_Init
988 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
989 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
990 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
991 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
993 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
994 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
995 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
996 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
997 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
998 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
999 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
1000 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
1001 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
1002 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
1003 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
1004 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
1006 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
1007 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
1008 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
1009 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
1011 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
1012 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
1013 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
1014 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
1016 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
1018 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
1019 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
1020 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
1022 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
1023 #define FMC_IT_LEVEL FSMC_IT_LEVEL
1024 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
1025 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
1027 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
1028 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
1029 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
1030 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
1032 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
1046 #endif /* __STM32F4xx_LL_FSMC_H */
1048 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/