2 ******************************************************************************
3 * @file stm32l0xx_hal_rcc.c
4 * @author MCD Application Team
6 * @date 06-February-2015
7 * @brief RCC HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Reset and Clock Control (RCC) peripheral:
10 * + Initialization and de-initialization functions
11 * + Peripheral Control functions
14 ==============================================================================
15 ##### RCC specific features #####
16 ==============================================================================
17 [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS,
18 all peripherals are off except internal SRAM, Flash and SW-DP.
19 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
20 all peripherals mapped on these busses are running at MSI speed.
21 (+) The clock for all peripherals is switched off, except the SRAM and
23 (+) All GPIOs are in input floating state, except the SW-DP pins which
24 are assigned to be used for debug purpose.
25 [..] Once the device started from reset, the user application has to:
26 (+) Configure the clock source to be used to drive the System clock
27 (if the application needs higher frequency/performance)
28 (+) Configure the System clock frequency and Flash settings
29 (+) Configure the AHB and APB busses prescalers
30 (+) Enable the clock for the peripheral(s) to be used
31 (+) Configure the clock source(s) for peripherals whose clocks are not
32 derived from the System clock (ADC, RTC/LCD, RNG and IWDG)
34 ##### RCC Limitations #####
35 ==============================================================================
37 A delay between an RCC peripheral clock enable and the effective peripheral
38 enabling should be taken into account in order to manage the peripheral read/write
40 (+) This delay depends on the peripheral mapping.
41 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
42 after the clock enable bit is set on the hardware register
43 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
44 after the clock enable bit is set on the hardware register
48 (#) Enable the peripheral clock sometimes before the peripheral read/write
50 (#) For AHB peripheral, insert two dummy read to the peripheral register.
51 (#) For APB peripheral, insert a dummy read to the peripheral register.
54 ******************************************************************************
57 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
59 * Redistribution and use in source and binary forms, with or without modification,
60 * are permitted provided that the following conditions are met:
61 * 1. Redistributions of source code must retain the above copyright notice,
62 * this list of conditions and the following disclaimer.
63 * 2. Redistributions in binary form must reproduce the above copyright notice,
64 * this list of conditions and the following disclaimer in the documentation
65 * and/or other materials provided with the distribution.
66 * 3. Neither the name of STMicroelectronics nor the names of its contributors
67 * may be used to endorse or promote products derived from this software
68 * without specific prior written permission.
70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
73 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
74 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
75 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
76 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
77 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
78 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
79 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 ******************************************************************************
84 /* Includes ------------------------------------------------------------------*/
85 #include "stm32l0xx_hal.h"
87 /** @addtogroup STM32L0xx_HAL_Driver
92 * @brief RCC HAL module driver
96 #ifdef HAL_RCC_MODULE_ENABLED
98 /** @defgroup RCC_Private_Constants RCC Private constants
101 #define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
102 #define RCC_HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
103 #define RCC_LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
104 #define RCC_PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
105 #define RCC_HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
106 #define RCC_MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
107 #define RCC_CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
109 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
110 #define MCO1_GPIO_PORT GPIOA
111 #define MCO1_PIN GPIO_PIN_8
112 #define MCO2_PIN GPIO_PIN_9
118 /** @defgroup RCC_Private_Vatiables RCC Private Data
121 const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
122 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
128 /** @addtogroup RCC_Exported_Functions
132 /** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
133 * @brief Initialization and Configuration functions
136 ===============================================================================
137 ##### Initialization and de-initialization functions #####
138 ===============================================================================
140 This section provide functions allowing to configure the internal/external
141 clocks, PLL, CSS and MCO.
142 [..] Internal/external clock and PLL configuration
143 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly
144 or through the PLL as System clock source.
145 (#) MSI (multi-speed internal), multispeed low power RC
146 (65.536 KHz to 4.194 MHz) MHz used as System clock source.
147 (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG
148 and/or RTC clock source.
149 (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used
150 directly or through the PLL as System clock source. Can be used
151 also as RTC clock source.
152 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
153 (#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).
154 (#) CSS (Clock security system), once enable and if a HSE clock failure
155 occurs (HSE used directly or through PLL as System clock source),
156 the System clock is automatically switched to MSI and an interrupt
157 is generated if enabled.
158 The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
160 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI,
161 HSE, PLL, LSI or LSE clock (through a configurable prescaler) on
163 [..] System, AHB and APB busses clocks configuration
164 (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
166 The AHB clock (HCLK) is derived from System clock through configurable
167 prescaler and used to clock the CPU, memory and peripherals mapped
168 on IOPORT, AHB bus (DMA,Flash...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
169 from AHB clock through configurable prescalers and used to clock
170 the peripherals mapped on these busses. You can use
171 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
173 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
174 (+@) I2S: the I2S clock can be derived from an external clock mapped on the I2S_CKIN pin.
176 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
177 divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
178 macros to configure this clock.
179 (+@) USB FS,and RNG require a frequency equal to 48 MHz to work correctly
180 This clock is derived from the main PLL or HSI48 RC oscillator.
181 (+@) IWDG clock which is always the LSI clock.
183 (#) For the STM32L0xx devices, the maximum
184 frequency of the SYSCLK ,HCLK, APB1 and APB2 is 32 MHz.
185 Depending on the device voltage range, the maximum frequency should
186 be adapted accordingly:
187 ----------------------------------------------------------------
188 | Wait states | HCLK clock frequency (MHz) |
189 | |------------------------------------------------|
190 | (Latency) | voltage range | voltage range |
191 | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
192 | |----------------|---------------|---------------|
193 | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
194 |-------------- |----------------|---------------|---------------|
195 |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
196 |---------------|----------------|---------------|---------------|
197 |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
198 ----------------------------------------------------------------
204 * @brief Resets the RCC clock configuration to the default reset state.
205 * @note The default reset state of the clock configuration is given below:
206 * - MSI ON and used as system clock source (MSI range is not modified
207 * - by this function, it keep the value configured by user application)
208 * - HSI, HSE and PLL OFF
209 * - AHB, APB1 and APB2 prescaler set to 1.
211 * - All interrupts disabled
212 * @note This function does not modify the configuration of the
213 * @note -Peripheral clocks
214 * @note -HSI48, LSI, LSE and RTC clocks
218 __weak void HAL_RCC_DeInit(void)
220 /* This function is now defined in the file stm32L0xx_rcc_ex.c */
224 * @brief Initializes the RCC Oscillators according to the specified parameters in the
225 * RCC_OscInitTypeDef.
226 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
227 * contains the configuration information for the RCC Oscillators.
228 * @note The PLL is not disabled when used as system clock.
231 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
234 uint32_t tickstart = 0;
236 /* Check the parameters */
237 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
238 /*------------------------------- HSE Configuration ------------------------*/
239 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
241 /* Check the parameters */
242 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
243 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
244 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSE)))
246 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
253 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
254 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
257 tickstart = HAL_GetTick();
259 /* Wait till HSE is disabled */
260 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
262 if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
268 /* Set the new HSE configuration ---------------------------------------*/
269 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
271 /* Check the HSE State */
272 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
275 tickstart = HAL_GetTick();
277 /* Wait till HSE is ready */
278 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
280 if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
289 tickstart = HAL_GetTick();
291 /* Wait till HSE is disabled */
292 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
294 if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
302 /*----------------------------- HSI Configuration --------------------------*/
303 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
305 /* Check the parameters */
306 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
307 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
309 /* When the HSI is used as system clock it will not disabled */
310 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSI)))
312 /* When HSI is used as system clock it will not disabled */
313 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
317 /* Otherwise, just the calibration is allowed */
320 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
321 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
326 /* Check the HSI State */
327 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
329 /* Enable the Internal High Speed oscillator (HSI or HSIdiv4 */
330 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
333 tickstart = HAL_GetTick();
335 /* Wait till HSI is ready */
336 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
338 if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE)
344 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
345 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
349 /* Disable the Internal High Speed oscillator (HSI). */
350 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
353 tickstart = HAL_GetTick();
355 /* Wait till HSI is ready */
356 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
358 if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE)
366 /*----------------------------- MSI Configuration --------------------------*/
367 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
369 /* Check the parameters */
370 assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
371 assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
374 /* When the MSI is used as system clock it will not disabled */
375 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
377 if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON))
382 /* Otherwise, just the calibration and MSI range change are allowed */
385 /* Selects the Multiple Speed oscillator (MSI) clock range .*/
386 __HAL_RCC_MSI_RANGE_CONFIG (RCC_OscInitStruct->MSIClockRange);
387 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
388 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
393 /* Check the MSI State */
394 if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF)
396 /* Enable the Internal High Speed oscillator (MSI). */
397 __HAL_RCC_MSI_ENABLE();
400 tickstart = HAL_GetTick();
402 /* Wait till MSI is ready */
403 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
405 if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE)
410 /* Selects the Multiple Speed oscillator (MSI) clock range .*/
411 __HAL_RCC_MSI_RANGE_CONFIG (RCC_OscInitStruct->MSIClockRange);
412 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
413 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
418 /* Disable the Internal High Speed oscillator (MSI). */
419 __HAL_RCC_MSI_DISABLE();
422 tickstart = HAL_GetTick();
424 /* Wait till MSI is ready */
425 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET)
427 if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE)
435 /*------------------------------ LSI Configuration -------------------------*/
436 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
438 /* Check the parameters */
439 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
441 /* Check the LSI State */
442 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
444 /* Enable the Internal Low Speed oscillator (LSI). */
445 __HAL_RCC_LSI_ENABLE();
448 tickstart = HAL_GetTick();
450 /* Wait till LSI is ready */
451 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
453 if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE)
461 /* Disable the Internal Low Speed oscillator (LSI). */
462 __HAL_RCC_LSI_DISABLE();
465 tickstart = HAL_GetTick();
467 /* Wait till LSI is ready */
468 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
470 if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE)
478 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
479 /*------------------------------ HSI48 Configuration -------------------------*/
480 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
482 /* Check the parameters */
483 assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
485 /* Check the HSI48 State */
486 if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
488 /* Enable the Internal Low Speed oscillator (HSI48). */
489 __HAL_RCC_HSI48_ENABLE();
492 tickstart = HAL_GetTick();
494 /* Wait till HSI48 is ready */
495 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
497 if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE)
505 /* Disable the Internal Low Speed oscillator (HSI48). */
506 __HAL_RCC_HSI48_DISABLE();
509 tickstart = HAL_GetTick();
511 /* Wait till HSI48 is ready */
512 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
514 if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE)
521 #endif /* !(STM32L031xx) && !(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)*/
523 /*------------------------------ LSE Configuration -------------------------*/
524 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
526 /* Check the parameters */
527 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
529 /* Enable Power Clock*/
530 __HAL_RCC_PWR_CLK_ENABLE();
532 /* Enable write access to Backup domain */
533 PWR->CR |= PWR_CR_DBP;
535 /* Wait for Backup domain Write protection disable */
536 tickstart = HAL_GetTick();
538 while((PWR->CR & PWR_CR_DBP) == RESET)
540 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
546 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
547 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
550 tickstart = HAL_GetTick();
552 /* Wait till LSE is ready */
553 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
555 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
561 /* Set the new LSE configuration -----------------------------------------*/
562 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
563 /* Check the LSE State */
564 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
567 tickstart = HAL_GetTick();
569 /* Wait till LSE is ready */
570 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
572 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
581 tickstart = HAL_GetTick();
583 /* Wait till LSE is ready */
584 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
586 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
593 /*-------------------------------- PLL Configuration -----------------------*/
594 /* Check the parameters */
595 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
596 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
598 /* Check if the PLL is used as system clock or not */
599 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
601 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
603 /* Check the parameters */
604 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
605 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
606 assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
609 /* Disable the main PLL. */
610 __HAL_RCC_PLL_DISABLE();
613 tickstart = HAL_GetTick();
615 /* Wait till PLL is ready */
616 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
618 if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
624 /* Configure the main PLL clock source, multiplication and division factors. */
625 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
626 RCC_OscInitStruct->PLL.PLLMUL,
627 RCC_OscInitStruct->PLL.PLLDIV);
628 /* Enable the main PLL. */
629 __HAL_RCC_PLL_ENABLE();
632 tickstart = HAL_GetTick();
634 /* Wait till PLL is ready */
635 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
637 if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
645 /* Disable the main PLL. */
646 __HAL_RCC_PLL_DISABLE();
648 tickstart = HAL_GetTick();
650 /* Wait till PLL is ready */
651 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
653 if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
669 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
670 * parameters in the RCC_ClkInitStruct.
671 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
672 * contains the configuration information for the RCC peripheral.
673 * @param FLatency: FLASH Latency, this parameter depends on System Clock Frequency
675 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
676 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
678 * @note The MSI is used (enabled by hardware) as system clock source after
679 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
680 * of failure of the HSE used directly or indirectly as system clock
681 * (if the Clock Security System CSS is enabled).
683 * @note A switch from one clock source to another occurs only if the target
684 * clock source is ready (clock stable after startup delay or PLL locked).
685 * If a clock source which is not yet ready is selected, the switch will
686 * occur when the clock source will be ready.
689 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
692 uint32_t tickstart = 0;
694 /* Check the parameters */
695 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
696 assert_param(IS_FLASH_LATENCY(FLatency));
698 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
699 must be correctly programmed according to the frequency of the CPU clock
700 (HCLK) and the supply voltage of the device. */
702 /* Increasing the CPU frequency */
703 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
705 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
706 __HAL_FLASH_SET_LATENCY(FLatency);
708 /* Check that the new number of wait states is taken into account to access the Flash
709 memory by reading the FLASH_ACR register */
710 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
715 /*-------------------------- HCLK Configuration --------------------------*/
716 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
718 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
719 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
722 /*------------------------- SYSCLK Configuration ---------------------------*/
723 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
725 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
727 /* HSE is selected as System Clock Source */
728 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
730 /* Check the HSE ready flag */
731 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
737 /* MSI is selected as System Clock Source */
738 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
740 /* Check the MSI ready flag */
741 if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
746 /* PLL is selected as System Clock Source */
747 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
749 /* Check the PLL ready flag */
750 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
755 /* HSI is selected as System Clock Source */
758 /* Check the HSI ready flag */
759 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
764 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
767 tickstart = HAL_GetTick();
769 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
771 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
773 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
779 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
781 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
783 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
789 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
791 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
793 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
801 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
803 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
811 /* Decreasing the CPU frequency */
814 /*-------------------------- HCLK Configuration --------------------------*/
815 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
817 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
818 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
821 /*------------------------- SYSCLK Configuration -------------------------*/
822 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
824 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
826 /* HSE is selected as System Clock Source */
827 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
829 /* Check the HSE ready flag */
830 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
836 /* MSI is selected as System Clock Source */
837 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
839 /* Check the MSI ready flag */
840 if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
845 /* PLL is selected as System Clock Source */
846 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
848 /* Check the PLL ready flag */
849 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
854 /* HSI is selected as System Clock Source */
857 /* Check the HSI ready flag */
858 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
863 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
866 tickstart = HAL_GetTick();
868 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
870 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
872 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
878 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
880 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
882 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
888 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
890 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
892 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
900 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
902 if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
910 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
911 __HAL_FLASH_SET_LATENCY(FLatency);
913 /* Check that the new number of wait states is taken into account to access the Flash
914 memory by reading the FLASH_ACR register */
915 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
921 /*-------------------------- PCLK1 Configuration ---------------------------*/
922 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
924 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
925 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
928 /*-------------------------- PCLK2 Configuration ---------------------------*/
929 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
931 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
932 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
935 /* Configure the source of time base considering new system clocks settings*/
936 HAL_InitTick (TICK_INT_PRIORITY);
945 /** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
946 * @brief RCC clocks control functions
949 ===============================================================================
950 ##### Peripheral Control functions #####
951 ===============================================================================
953 This subsection provides a set of functions allowing to control the RCC Clocks
961 * @brief Selects the clock source to output on MCO pin.
962 * @note MCO pin should be configured in alternate function mode.
963 * @param RCC_MCOx: specifies the output direction for the clock source.
964 * For STM32L0xx family this parameter can have only one value:
965 * @arg RCC_MCO1: Clock source to output on MCO pin(PA8).
966 * @arg RCC_MCO2: Clock source to output on MCO pin(PA9).
967 * @param RCC_MCOSource: specifies the clock source to output.
968 * This parameter can be one of the following values:
969 * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
970 * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected
971 * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected
972 * @arg RCC_MCO1SOURCE_MSI: MSI oscillator clock selected
973 * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
974 * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected
975 * @arg RCC_MCO1SOURCE_LSI: LSI clock selected
976 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected
977 * and in STM32L052xx,STM32L053xx,STM32L062xx, STM32L063xx
978 * STM32L072xx,STM32L073xx,STM32L082xx, STM32L083xx
979 * @arg RCC_MCO1SOURCE_HSI48: HSI48 clock selected
980 * @param RCC_MCODIV: specifies the MCO DIV.
981 * This parameter can be one of the following values:
982 * @arg RCC_MCODIV_1: no division applied to MCO clock
983 * @arg RCC_MCODIV_2: division by 2 applied to MCO clock
984 * @arg RCC_MCODIV_4: division by 4 applied to MCO clock
985 * @arg RCC_MCODIV_8: division by 8 applied to MCO clock
986 * @arg RCC_MCODIV_16: division by 16 applied to MCO clock
989 void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
991 GPIO_InitTypeDef GPIO_InitStruct;
992 /* Check the parameters */
993 assert_param(IS_RCC_MCO(RCC_MCOx));
994 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
995 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
997 /* MCO Clock Enable */
1000 /* Configure the MCO1 pin in alternate function mode */
1001 if(RCC_MCOx == RCC_MCO1)
1003 GPIO_InitStruct.Pin = MCO1_PIN;
1007 GPIO_InitStruct.Pin = MCO2_PIN;
1009 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1010 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
1011 GPIO_InitStruct.Pull = GPIO_NOPULL;
1012 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
1013 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
1015 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
1016 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((RCC_MCOSource | RCC_MCODiv )));
1020 * @brief Enables the Clock Security System.
1021 * @note If a failure is detected on the HSE oscillator clock, this oscillator
1022 * is automatically disabled and an interrupt is generated to inform the
1023 * software about the failure (Clock Security System Interrupt, CSSI),
1024 * allowing the MCU to perform rescue operations. The CSSI is linked to
1025 * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
1029 void HAL_RCC_EnableCSS(void)
1031 SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
1036 * @brief Returns the SYSCLK frequency
1038 * @note The system frequency computed by this function is not the real
1039 * frequency in the chip. It is calculated based on the predefined
1040 * constant and the selected clock source:
1041 * @note If SYSCLK source is MSI, function returns values based on MSI
1042 * Value as defined by the MSI range.
1043 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1044 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
1045 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
1046 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
1047 * @note (*) HSI_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
1048 * 16 MHz) but the real value may vary depending on the variations
1049 * in voltage and temperature.
1050 * @note (**) HSE_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
1051 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
1052 * frequency of the crystal used. Otherwise, this function may
1053 * have wrong result.
1055 * @note The result of this function could be not correct when using fractional
1056 * value for HSE crystal.
1058 * @note This function can be used by the user application to compute the
1059 * baudrate for the communication peripherals or configure other parameters.
1061 * @note Each time SYSCLK changes, this function must be called to update the
1062 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1066 * @retval SYSCLK frequency
1068 uint32_t HAL_RCC_GetSysClockFreq(void)
1070 uint32_t pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
1071 uint32_t sysclockfreq = 0;
1073 /* Get SYSCLK source -------------------------------------------------------*/
1075 /*MSI frequency range in HZ*/
1076 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
1078 switch (RCC->CFGR & RCC_CFGR_SWS)
1080 case RCC_CFGR_SWS_MSI: /* MSI used as system clock */
1082 sysclockfreq = (32768 * (1 << (msirange + 1)));
1085 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock */
1087 if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
1089 sysclockfreq = (HSI_VALUE >> 2);
1093 sysclockfreq = HSI_VALUE;
1097 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
1099 sysclockfreq = HSE_VALUE;
1102 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
1104 /* Get PLL clock source and multiplication factor ----------------------*/
1105 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
1106 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
1107 pllmul = PLLMulTable[(pllmul >> 18)];
1108 plldiv = (plldiv >> 22) + 1;
1110 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
1112 if (pllsource == RCC_CFGR_PLLSRC_HSI)
1114 /* HSI oscillator clock selected as PLL clock source */
1115 if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
1117 sysclockfreq = (HSI_VALUE >> 2) * (pllmul / plldiv);
1121 sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv);
1126 /* HSE selected as PLL clock source */
1127 sysclockfreq = (((HSE_VALUE) * pllmul) / plldiv);
1131 default: /* MSI used as system clock */
1133 sysclockfreq = (32768 * (1 << (msirange + 1)));
1137 return sysclockfreq;
1141 * @brief Returns the HCLK frequency
1142 * @note Each time HCLK changes, this function must be called to update the
1143 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1145 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
1146 * and updated within this function
1148 * @retval HCLK frequency
1150 uint32_t HAL_RCC_GetHCLKFreq(void)
1152 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
1154 return (SystemCoreClock);
1159 * @brief Returns the PCLK1 frequency
1160 * @note Each time PCLK1 changes, this function must be called to update the
1161 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1163 * @retval PCLK1 frequency
1165 uint32_t HAL_RCC_GetPCLK1Freq(void)
1168 return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE1) >> 8)]);
1173 * @brief Returns the PCLK2 frequency
1174 * @note Each time PCLK2 changes, this function must be called to update the
1175 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1177 * @retval PCLK2 frequency
1179 uint32_t HAL_RCC_GetPCLK2Freq(void)
1182 return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE2) >> 11)]);
1187 * @brief Configures the RCC_OscInitStruct according to the internal
1188 * RCC configuration registers.
1189 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
1190 * will be configured.
1193 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
1195 /* Set all possible values for the Oscillator type parameter ---------------*/
1196 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | \
1197 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
1198 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
1199 RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
1202 /* Get the HSE configuration -----------------------------------------------*/
1203 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
1205 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1207 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
1209 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1213 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1216 /* Get the MSI configuration -----------------------------------------------*/
1217 if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION)
1219 RCC_OscInitStruct->MSIState = RCC_MSI_ON;
1223 RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
1226 RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24);
1227 RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13);
1229 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
1230 /* Get the HSI48 configuration -----------------------------------------------*/
1231 if((RCC->CRRCR &RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
1233 RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
1237 RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
1241 /* Get the HSI configuration -----------------------------------------------*/
1242 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
1244 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1248 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1251 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> 8);
1253 /* Get the LSE configuration -----------------------------------------------*/
1254 if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)
1256 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1258 else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON)
1260 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1264 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1267 /* Get the LSI configuration -----------------------------------------------*/
1268 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
1270 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1274 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1277 /* Get the PLL configuration -----------------------------------------------*/
1278 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
1280 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1284 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1286 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
1287 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL) >> 18;
1288 RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV) >> 22;
1293 * @brief Configures the RCC_ClkInitStruct according to the internal
1294 * RCC configuration registers.
1295 * @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1296 * will be configured.
1297 * @param pFLatency: Pointer on the Flash Latency.
1300 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1302 /* Set all possible values for the Clock type parameter --------------------*/
1303 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1305 /* Get the SYSCLK configuration --------------------------------------------*/
1306 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1308 /* Get the HCLK configuration ----------------------------------------------*/
1309 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1311 /* Get the APB1 configuration ----------------------------------------------*/
1312 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1314 /* Get the APB2 configuration ----------------------------------------------*/
1315 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1317 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1318 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1322 * @brief This function handles the RCC CSS interrupt request.
1323 * @note This API should be called under the NMI_Handler().
1327 void HAL_RCC_NMI_IRQHandler(void)
1329 /* Check RCC CSSF flag */
1330 if(__HAL_RCC_GET_IT_SOURCE(RCC_IT_CSS))
1332 /* RCC Clock Security System interrupt user callback */
1333 HAL_RCC_CSSCallback();
1335 /* Clear RCC CSS pending bit */
1336 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1341 * @brief RCC Clock Security System interrupt callback
1345 __weak void HAL_RCC_CSSCallback(void)
1347 /* NOTE : This function Should not be modified, when the callback is needed,
1348 the HAL_RCC_CSSCallback could be implemented in the user file
1360 #endif /* HAL_RCC_MODULE_ENABLED */
1369 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/