2 ******************************************************************************
3 * @file stm32l0xx_hal_rcc_ex.c
4 * @author MCD Application Team
6 * @date 06-February-2015
7 * @brief Extended RCC HAL module driver.
9 * This file provides firmware functions to manage the following
10 * functionalities RCC extension peripheral:
11 * + Extended Peripheral Control functions
14 ==============================================================================
15 ##### RCC specific features #####
16 ==============================================================================
17 For CRS, RCC Extension HAL driver can be used as follows:
19 (#) In System clock configuration, HSI48 need to be enabled
21 (#] Enable CRS clock in IP MSP init which will use CRS functions
23 (#) Call CRS functions like this
24 (##) Prepare synchronization configuration necessary for HSI48 calibration
25 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
26 and also HSI48 oscillator smooth trimming.
27 (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate
28 directly reload value with target and synchronization frequencies values
29 (##) Call function HAL_RCCEx_CRSConfig which
30 (+++) Reset CRS registers to their default values.
31 (+++) Configure CRS registers with synchronization configuration
32 (+++) Enable automatic calibration and frequency error counter feature
34 (##) A polling function is provided to wait for complete Synchronization
35 (+++) Call function 'HAL_RCCEx_CRSWaitSynchronization()'
36 (+++) According to CRS status, user can decide to adjust again the calibration or continue
37 application if synchronization is OK
39 (#) User can retrieve information related to synchronization in calling function
40 HAL_RCCEx_CRSGetSynchronizationInfo()
42 (#) Regarding synchronization status and synchronization information, user can try a new calibration
43 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
44 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
45 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
46 incremented), while when it is detected during the upcounting phase it means that the actual frequency
47 is higher (and that the TRIM value should be decremented).
49 (#) To use IT mode, user needs to handle it in calling different macros available to do it
50 (__HAL_RCC_CRS_XXX_IT). Interruptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler)
51 (+++) Call function HAL_RCCEx_CRSConfig()
52 (+++) Enable RCC_IRQn (thnaks to NVIC functions)
53 (+++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT)
54 [+++) Implement CRS status management in RCC_CRS_IRQHandler
56 (#) To force a SYNC EVENT, user can use function 'HAL_RCCEx_CRSSoftwareSynchronizationGenerate()'. Function can be
57 called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
60 ******************************************************************************
63 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
65 * Redistribution and use in source and binary forms, with or without modification,
66 * are permitted provided that the following conditions are met:
67 * 1. Redistributions of source code must retain the above copyright notice,
68 * this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright notice,
70 * this list of conditions and the following disclaimer in the documentation
71 * and/or other materials provided with the distribution.
72 * 3. Neither the name of STMicroelectronics nor the names of its contributors
73 * may be used to endorse or promote products derived from this software
74 * without specific prior written permission.
76 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
77 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
79 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
82 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
83 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
84 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
85 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
87 ******************************************************************************
90 /* Includes ------------------------------------------------------------------*/
91 #include "stm32l0xx_hal.h"
93 /** @addtogroup STM32L0xx_HAL_Driver
98 * @brief RCC Extension HAL module driver
102 #ifdef HAL_RCC_MODULE_ENABLED
104 /** @defgroup RCCEx_Private_Constants
107 /* Bit position in register */
108 #define CRS_CFGR_FELIM_BITNUMBER 16
109 #define CRS_CR_TRIM_BITNUMBER 8
110 #define CRS_ISR_FECAP_BITNUMBER 16
116 /** @addtogroup RCCEx_Exported_Functions
120 /** @addtogroup RCCEx_Exported_Functions_Group1
121 * @brief Extended Peripheral Initialization and Control functions
124 ===============================================================================
125 ##### Extended Peripheral Control functions #####
126 ===============================================================================
128 This subsection provides a set of functions allowing to control the RCC Clocks
136 * @brief Resets the RCC clock configuration to the default reset state.
137 * @note The default reset state of the clock configuration is given below:
138 * - MSI ON and used as system clock source (MSI range is not modified
139 * - by this function, it keep the value configured by user application)
140 * - HSI, HSI_OUT, HSE and PLL OFF
141 * - AHB, APB1 and APB2 prescaler set to 1.
143 * - All interrupts disabled
144 * @note This function does not modify the configuration of the
145 * @note -Peripheral clocks
146 * @note -HSI48, LSI, LSE and RTC clocks
150 void HAL_RCC_DeInit(void)
153 SET_BIT(RCC->CR, RCC_CR_MSION);
155 #if defined(STM32L073xx) || defined(STM32L083xx) || \
156 defined(STM32L072xx) || defined(STM32L082xx) || \
157 defined(STM32L071xx) || defined(STM32L081xx)
158 /* Reset HSE, HSI, CSS, PLL */
159 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
160 RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
162 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
163 RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
166 /* Reset HSEBYP bit */
167 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
169 /* Reset CFGR register */
170 CLEAR_REG(RCC->CFGR);
172 /* Disable all interrupts */
173 CLEAR_REG(RCC->CIER);
177 * @brief Initializes the RCC extended peripherals clocks
178 * @note Initializes the RCC extended peripherals clocks according to the specified parameters in the
179 * RCC_PeriphCLKInitTypeDef.
180 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
181 * contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
182 * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
185 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
187 uint32_t tickstart = 0;
190 /* Check the parameters */
191 assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
193 #if !defined (STM32L031xx) && !defined (STM32L041xx)
194 /*------------------------------- USART1 Configuration ------------------------*/
195 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
197 /* Check the parameters */
198 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
200 /* Configure the USART1 clock source */
201 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
205 /*----------------------------- USART2 Configuration --------------------------*/
206 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
208 /* Check the parameters */
209 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
211 /* Configure the USART2 clock source */
212 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
215 /*------------------------------ LPUART1 Configuration ------------------------*/
216 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
218 /* Check the parameters */
219 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
221 /* Configure the LPUAR1 clock source */
222 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
225 /*------------------------------ I2C1 Configuration ------------------------*/
226 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
228 /* Check the parameters */
229 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
231 /* Configure the I2C1 clock source */
232 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
235 #if defined (STM32L071xx) || (STM32L072xx) || defined(STM32L073xx) || \
236 defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
237 /*------------------------------ I2C3 Configuration ------------------------*/
238 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
240 /* Check the parameters */
241 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
243 /* Configure the I2C3 clock source */
244 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
246 #endif /* defined (STM32L071xx) (STM32L072xx)|| (STM32L073xx)|| (STM32L081xx)|| (STM32L082xx) || (STM32L083xx) */
248 /*---------------------------- RTC/LCD configuration -------------------------------*/
249 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
250 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
251 || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
252 #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
255 /* Enable Power Clock*/
256 __HAL_RCC_PWR_CLK_ENABLE();
258 /* Enable write access to Backup domain */
259 PWR->CR |= PWR_CR_DBP;
261 /* Wait for Backup domain Write protection disable */
262 tickstart = HAL_GetTick();
264 while((PWR->CR & PWR_CR_DBP) == RESET)
266 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
272 /* Reset the Backup domain only if the RTC Clock source selection is modified */
273 if(((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
274 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
275 || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
276 #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
279 /* Store the content of CSR register before the reset of Backup Domain */
280 tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
281 /* RTC Clock selection can be changed only if the Backup Domain is reset */
282 __HAL_RCC_BACKUPRESET_FORCE();
283 __HAL_RCC_BACKUPRESET_RELEASE();
284 /* Restore the Content of CSR register */
288 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
289 if((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
290 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
291 || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE)
292 #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
296 tickstart = HAL_GetTick();
298 /* Wait till LSE is ready */
299 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
301 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
307 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
309 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
310 /*---------------------------- USB and RNG configuration --------------------*/
311 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
313 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
314 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
318 /*---------------------------- LPTIM1 configuration ------------------------*/
319 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
321 assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
322 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
330 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
331 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
332 * returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
333 * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
336 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
338 /* Set all possible values for the extended clock type parameter -----------*/
339 /* Common part first */
340 #if defined(STM32L031xx) || defined(STM32L041xx)
341 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \
342 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1;
344 #if defined(STM32L052xx) || defined(STM32L062xx)
345 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
346 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
347 RCC_PERIPHCLK_LPTIM1 ;
349 #if defined(STM32L053xx) || defined(STM32L063xx)
350 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
351 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
352 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD;
354 #if defined(STM32L072xx) || defined(STM32L082xx)
355 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
356 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \
357 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 ;
359 #if defined(STM32L073xx) || defined(STM32L083xx)
360 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
361 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \
362 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD;
365 #if defined(STM32L051xx) || defined(STM32L061xx)
366 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
367 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1;
369 #if defined(STM32L071xx) || defined(STM32L081xx)
370 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
371 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \
372 RCC_PERIPHCLK_LPTIM1;
375 #if !defined (STM32L031xx) && !defined (STM32L041xx)
376 /* Get the USART1 configuration --------------------------------------------*/
377 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
379 /* Get the USART2 clock source ---------------------------------------------*/
380 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
381 /* Get the LPUART1 clock source ---------------------------------------------*/
382 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
383 /* Get the I2C1 clock source -----------------------------------------------*/
384 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
385 #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || \
386 defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
387 /* Get the I2C3 clock source -----------------------------------------------*/
388 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
389 #endif /* defined (STM32L071xx) || (STM32L073xx) || (STM32L082xx) || (STM32L082xx) || (STM32L083xx) */
390 /* Get the LPTIM1 clock source -----------------------------------------------*/
391 PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
392 /* Get the RTC clock source -----------------------------------------------*/
393 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
394 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
395 PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
396 #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
398 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
399 /* Get the USB/RNG clock source -----------------------------------------------*/
400 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
405 * @brief Enables the LSE Clock Security System.
409 void HAL_RCCEx_EnableLSECSS(void)
411 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
415 * @brief Disables the LSE Clock Security System.
419 void HAL_RCCEx_DisableLSECSS(void)
421 CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
424 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
427 * @brief Start automatic synchronization using polling mode
428 * @param pInit Pointer on RCC_CRSInitTypeDef structure
431 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
433 /* Check the parameters */
434 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
435 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
436 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
437 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
438 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
439 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
444 /* Before configuration, reset CRS registers to their default values*/
445 __HAL_RCC_CRS_FORCE_RESET();
446 __HAL_RCC_CRS_RELEASE_RESET();
448 /* Configure Synchronization input */
449 /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */
450 CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL);
452 /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */
453 CRS->CFGR |= pInit->Prescaler;
455 /* Set the SYNCSRC[1:0] bits according to Source value */
456 CRS->CFGR |= pInit->Source;
458 /* Set the SYNCSPOL bits according to Polarity value */
459 CRS->CFGR |= pInit->Polarity;
461 /* Configure Frequency Error Measurement */
462 /* Clear RELOAD[15:0] & FELIM[7:0] bits*/
463 CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM);
465 /* Set the RELOAD[15:0] bits according to ReloadValue value */
466 CRS->CFGR |= pInit->ReloadValue;
468 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
469 CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
471 /* Adjust HSI48 oscillator smooth trimming */
472 /* Clear TRIM[5:0] bits */
473 CRS->CR &= ~CRS_CR_TRIM;
475 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
476 CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER);
479 /* START AUTOMATIC SYNCHRONIZATION*/
481 /* Enable Automatic trimming */
482 __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB();
484 /* Enable Frequency error counter */
485 __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER();
490 * @brief Generate the software synchronization event
494 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
496 CRS->CR |= CRS_CR_SWSYNC;
501 * @brief Function to return synchronization info
502 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
505 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
507 /* Check the parameter */
508 assert_param(pSynchroInfo != NULL);
510 /* Get the reload value */
511 pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD);
513 /* Get HSI48 oscillator smooth trimming */
514 pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
516 /* Get Frequency error capture */
517 pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
519 /* Get Frequency error direction */
520 pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR);
526 * @brief This function handles CRS Synchronization Timeout.
527 * @param Timeout: Duration of the timeout
528 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
530 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
531 * @retval Combination of Synchronization status
532 * This parameter can be a combination of the following values:
533 * @arg RCC_CRS_TIMEOUT
534 * @arg RCC_CRS_SYNCOK
535 * @arg RCC_CRS_SYNCWARM
536 * @arg RCC_CRS_SYNCERR
537 * @arg RCC_CRS_SYNCMISS
538 * @arg RCC_CRS_TRIMOV
540 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
542 uint32_t crsstatus = RCC_CRS_NONE;
543 uint32_t tickstart = 0;
546 tickstart = HAL_GetTick();
548 /* Check that if one of CRS flags have been set */
549 while(RCC_CRS_NONE == crsstatus)
551 if(Timeout != HAL_MAX_DELAY)
553 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
555 crsstatus = RCC_CRS_TIMEOUT;
558 /* Check CRS SYNCOK flag */
559 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
561 /* CRS SYNC event OK */
562 crsstatus |= RCC_CRS_SYNCOK;
564 /* Clear CRS SYNC event OK bit */
565 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
568 /* Check CRS SYNCWARN flag */
569 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
571 /* CRS SYNC warning */
572 crsstatus |= RCC_CRS_SYNCWARM;
574 /* Clear CRS SYNCWARN bit */
575 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
578 /* Check CRS TRIM overflow flag */
579 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
582 crsstatus |= RCC_CRS_TRIMOV;
584 /* Clear CRS Error bit */
585 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
588 /* Check CRS Error flag */
589 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
592 crsstatus |= RCC_CRS_SYNCERR;
594 /* Clear CRS Error bit */
595 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
598 /* Check CRS SYNC Missed flag */
599 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
601 /* CRS SYNC Missed */
602 crsstatus |= RCC_CRS_SYNCMISS;
604 /* Clear CRS SYNC Missed bit */
605 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
608 /* Check CRS Expected SYNC flag */
609 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
611 /* frequency error counter reached a zero value */
612 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
619 * @brief Enables Vrefint for the HSI48.
621 * @note This is functional only if the LOCK is not set
624 void HAL_RCCEx_EnableHSI48_VREFINT(void)
626 /* Enable the Buffer for the ADC by setting EN_VREFINT bit */
627 /* and the SYSCFG_CFGR3_ENREF_HSI48 in the CFGR3 register */
628 SET_BIT (SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT));
632 * @brief Disables the Vrefint for the HSI48.
634 * @note This is functional only if the LOCK is not set
637 void HAL_RCCEx_DisableHSI48_VREFINT(void)
639 /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit */
640 /* and the EN_VREFINT bit in the CFGR3 register */
641 CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT));
643 #endif /* !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
654 #endif /* HAL_RCC_MODULE_ENABLED */
663 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/