2 ******************************************************************************
3 * @file stm32l0xx_hal_rcc_ex.h
4 * @author MCD Application Team
6 * @date 06-February-2015
7 * @brief Header file of RCC HAL Extension module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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14 * are permitted provided that the following conditions are met:
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18 * this list of conditions and the following disclaimer in the documentation
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L0xx_HAL_RCC_EX_H
40 #define __STM32L0xx_HAL_RCC_EX_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l0xx_hal_def.h"
49 /** @addtogroup STM32L0xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
59 * @brief RCC extended clocks structure definition
61 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
64 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
65 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
66 uint32_t Usart1ClockSelection; /*!< USART1 clock source
67 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
69 uint32_t Usart2ClockSelection; /*!< USART2 clock source
70 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
72 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
73 This parameter can be a value of @ref RCCEx_LPUART_Clock_Source */
75 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
76 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
77 #if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
78 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
79 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
82 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
83 This parameter can be a value of @ref RCC_RTC_Clock_Source */
84 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
85 uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
86 This parameter can be a value of @ref RCC_RTC_Clock_Source */
89 uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
90 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
92 uint32_t LptimClockSelection; /*!< LPTIM1 clock source
93 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
95 }RCC_PeriphCLKInitTypeDef;
98 #else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
102 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
103 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
104 #if !defined (STM32L031xx) && !defined (STM32L041xx)
105 uint32_t Usart1ClockSelection; /*!< USART1 clock source
106 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
108 uint32_t Usart2ClockSelection; /*!< USART2 clock source
109 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
111 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
112 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
114 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
115 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
117 #if defined (STM32L071xx) || defined(STM32L081xx)
118 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
119 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
122 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
123 This parameter can be a value of @ref RCC_RTC_Clock_Source */
125 uint32_t LptimClockSelection; /*!< LPTIM1 clock source
126 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
128 }RCC_PeriphCLKInitTypeDef;
130 #endif /* STM32L0x1xx */
133 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
134 /** @defgroup RCCEx_Exported_Constants
138 * @brief RCC CRS Status definition
141 #define RCC_CRS_NONE ((uint32_t) 0x00000000)
142 #define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
143 #define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
144 #define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
145 #define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
146 #define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
147 #define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
153 * @brief RCC_CRS Init structure definition
157 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
158 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
160 uint32_t Source; /*!< Specifies the SYNC signal source.
161 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
163 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
164 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
166 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
167 It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
168 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
170 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
171 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
173 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
174 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
179 * @brief RCC_CRS Synchronization structure definition
183 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
184 This parameter must be a number between 0 and 0xFFFF*/
186 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
187 This parameter must be a number between 0 and 0x3F */
189 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
190 value latched in the time of the last SYNC event.
191 This parameter must be a number between 0 and 0xFFFF */
193 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
194 frequency error counter latched in the time of the last SYNC event.
195 It shows whether the actual frequency is below or above the target.
196 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
198 }RCC_CRSSynchroInfoTypeDef;
199 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
201 /* Exported constants --------------------------------------------------------*/
202 /** @addtogroup RCCEx_Exported_Constants
206 /** @defgroup RCCEx_Periph_Clock_Selection
209 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
211 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
212 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
213 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
214 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
215 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
216 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
217 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
218 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
219 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
220 #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
222 #if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
223 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
226 #if defined (STM32L052xx) || defined(STM32L062xx)
227 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
228 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
229 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
230 #elif defined (STM32L053xx) || defined(STM32L063xx)
231 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
232 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
233 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
234 #elif defined (STM32L072xx) || defined(STM32L082xx)
235 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
236 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
237 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 ))
238 #elif defined (STM32L073xx) || defined(STM32L083xx)
239 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
240 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
241 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \
245 #else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
247 #if !defined(STM32L031xx) && !defined(STM32L041xx)
248 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
250 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
251 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
252 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
253 #if !defined(STM32L031xx) && !defined(STM32L041xx)
254 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
256 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
257 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
258 #if defined(STM32L071xx) || defined(STM32L081xx)
259 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
262 #if defined(STM32L031xx) || defined(STM32L041xx)
263 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
264 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC ))
265 #elif defined(STM32L051xx) || defined(STM32L061xx)
266 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
267 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
268 RCC_PERIPHCLK_LPTIM1))
269 #elif defined(STM32L071xx) || defined(STM32L081xx)
270 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
271 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
272 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
275 #endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
280 /** @defgroup RCCEx_USART1_Clock_Source
283 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
284 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
285 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
286 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
287 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
288 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
289 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
290 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
295 /** @defgroup RCCEx_USART2_Clock_Source
298 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
299 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
300 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
301 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
302 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
303 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
304 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
305 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
310 /** @defgroup RCCEx_LPUART_Clock_Source
313 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
314 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
315 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
316 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
317 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
318 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
319 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
320 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
325 /** @defgroup RCCEx_I2C1_Clock_Source
328 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
329 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
330 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
331 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
332 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
333 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
338 #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx)|| defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
340 /** @defgroup RCCEx_I2C3_Clock_Source
343 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
344 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
345 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
346 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
347 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
348 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
349 #endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */
355 /** @defgroup RCCEx_TIM_PRescaler_Selection
358 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
359 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
364 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
365 /** @defgroup RCCEx_USB_Clock_Source
368 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
369 #define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
371 #define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
372 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
377 /** @defgroup RCCEx_RNG_Clock_Source
380 #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
381 #define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
383 #define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
384 ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
389 /** @defgroup RCCEx_HSI48M_Clock_Source
392 #define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
394 #define RCC_HSI48M_PLL ((uint32_t)0x00000000)
395 #define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
397 #define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
402 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
404 /** @defgroup RCC_HSI_Config
407 #define RCC_HSI_OFF ((uint8_t)0x00)
408 #define RCC_HSI_ON RCC_CR_HSION
409 #define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION)
410 #if defined(STM32L073xx) || defined(STM32L083xx) || \
411 defined(STM32L072xx) || defined(STM32L082xx) || \
412 defined(STM32L071xx) || defined(STM32L081xx)
413 #define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
415 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
416 ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))
418 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
419 ((__HSI__) == RCC_HSI_DIV4))
426 /** @defgroup RCCEx_LPTIM1_Clock_Source
429 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
430 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
431 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
432 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
434 #define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
435 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \
436 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \
437 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
442 /** @defgroup RCCEx_StopWakeUp_Clock
446 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
447 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
449 #define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
450 ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
455 /** @defgroup RCCEx_LSEDrive_Configuration
459 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
460 #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
461 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
462 #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
463 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
464 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
469 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
470 /** @defgroup RCCEx_CRS_SynchroSource
473 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal source GPIO */
474 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
475 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
477 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
478 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
479 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
484 /** @defgroup RCCEx_CRS_SynchroDivider
487 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
488 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
489 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
490 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
491 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
492 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
493 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
494 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
496 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) ||\
497 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
498 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
499 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
504 /** @defgroup RCCEx_CRS_SynchroPolarity
507 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
508 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
510 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
511 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
516 /** @defgroup RCCEx_CRS_ReloadValueDefault
519 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
520 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
522 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
527 /** @defgroup RCCEx_CRS_ErrorLimitDefault
530 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
532 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
537 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault
540 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
541 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
542 corresponds to a higher output frequency */
544 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
549 /** @defgroup RCCEx_CRS_FreqErrorDirection
552 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
553 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
555 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
556 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
561 /** @defgroup RCCEx_CRS_Interrupt_Sources
564 #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
565 #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
566 #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
567 #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
568 #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
569 #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
570 #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
576 /** @defgroup RCCEx_CRS_Flags
579 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
580 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
581 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
582 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
583 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
584 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
585 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
591 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
596 /* Exported macro ------------------------------------------------------------*/
597 /** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
601 /** @brief Enable or disable the AHB peripheral clock.
602 * @note After reset, the peripheral clock (used for registers read/write access)
603 * is disabled and the application software has to enable this clock before
607 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
608 #define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN))
609 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
610 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
612 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
613 #define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
614 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
616 #define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN))
617 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
618 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
621 #if defined(STM32L073xx) || defined(STM32L083xx) || \
622 defined(STM32L072xx) || defined(STM32L082xx) || \
623 defined(STM32L071xx) || defined(STM32L081xx)
624 /** @brief Enable or disable the IOPORT peripheral clock.
625 * @note After reset, the peripheral clock (used for registers read/write access)
626 * is disabled and the application software has to enable this clock before
629 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
630 __IO uint32_t tmpreg; \
631 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
632 /* Delay after an RCC peripheral clock enabling */ \
633 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
637 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
639 #endif /* STM32L071xx || STM32L081xx || */
640 /* STM32L072xx || STM32L082xx || */
641 /* STM32L073xx || STM32L083xx */
643 /** @brief Enable or disable the APB1 peripheral clock.
644 * @note After reset, the peripheral clock (used for registers read/write access)
645 * is disabled and the application software has to enable this clock before
649 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
650 #define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
651 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
653 #define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
654 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
655 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
658 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
659 #define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
660 #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
661 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
663 #if defined(STM32L053xx) || defined(STM32L063xx) || \
664 defined(STM32L052xx) || defined(STM32L062xx) || \
665 defined(STM32L051xx) || defined(STM32L061xx)
666 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
667 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
668 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
669 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
670 #define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
671 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
672 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
673 #define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
674 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
676 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
677 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
678 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
679 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
680 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
681 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
682 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
683 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
684 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
685 #endif /* STM32L051xx || STM32L061xx || */
686 /* STM32L052xx || STM32L062xx || */
687 /* STM32L053xx || STM32L063xx || */
689 #if defined(STM32L031xx) || defined(STM32L041xx)
690 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
691 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
692 #define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
693 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
694 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
696 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
697 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
698 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
699 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
700 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
701 #endif /* STM32L031xx || STM32L041xx || */
704 #if defined(STM32L073xx) || defined(STM32L083xx) || \
705 defined(STM32L072xx) || defined(STM32L082xx) || \
706 defined(STM32L071xx) || defined(STM32L081xx)
707 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
708 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
709 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
710 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
711 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
712 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
713 #define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
714 #define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
715 #define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
716 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
717 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
718 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
719 #define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
720 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
722 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
723 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
724 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
725 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
726 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
727 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
728 #define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
729 #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
730 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
731 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
732 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
733 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
734 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
735 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
736 #endif /* STM32L071xx || STM32L081xx || */
737 /* STM32L072xx || STM32L082xx || */
738 /* STM32L073xx || STM32L083xx */
740 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
741 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
742 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
743 defined(STM32L031xx) || defined(STM32L041xx)
745 /** @brief Enable or disable the APB2 peripheral clock.
746 * @note After reset, the peripheral clock (used for registers read/write access)
747 * is disabled and the application software has to enable this clock before
750 #define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN))
751 #define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN))
752 #define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN))
753 #define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
754 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
755 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
757 #define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
758 #define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
759 #define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
760 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
761 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
762 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
763 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
764 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
765 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
767 /** @brief Force or release AHB peripheral reset.
769 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
770 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST))
771 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
772 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
774 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
775 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
776 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
777 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST))
778 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
779 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
781 /** @brief Force or release IOPORT peripheral reset.
783 #if defined(STM32L073xx) || defined(STM32L083xx) || \
784 defined(STM32L072xx) || defined(STM32L082xx) || \
785 defined(STM32L071xx) || defined(STM32L081xx)
786 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOERST))
788 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
790 #endif /* STM32L071xx || STM32L081xx || */
791 /* STM32L072xx || STM32L082xx || */
792 /* STM32L073xx || STM32L083xx */
794 /** @brief Force or release APB1 peripheral reset.
797 #if defined(STM32L053xx) || defined(STM32L063xx) || \
798 defined(STM32L052xx) || defined(STM32L062xx) || \
799 defined(STM32L051xx) || defined(STM32L061xx)
800 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
801 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
802 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
803 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
804 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
805 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
806 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
807 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
808 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
810 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
811 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
812 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
813 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
814 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
815 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
816 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
817 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
818 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
819 #endif /* STM32L051xx || STM32L061xx || */
820 /* STM32L052xx || STM32L062xx || */
821 /* STM32L053xx || STM32L063xx */
822 #if defined(STM32L031xx) || defined(STM32L041xx)
823 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
824 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
825 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
826 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
827 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
829 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
830 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
831 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
832 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
833 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
834 #endif /* STM32L031xx || STM32L041xx || */
836 #if defined(STM32L073xx) || defined(STM32L083xx) || \
837 defined(STM32L072xx) || defined(STM32L082xx) || \
838 defined(STM32L071xx) || defined(STM32L081xx)
839 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
840 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
841 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
842 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
843 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
844 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
845 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
846 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
847 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
848 #define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
849 #define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
850 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
851 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
852 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
854 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
855 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
856 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
857 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
858 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
859 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
860 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
861 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
862 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
863 #define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
864 #define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
865 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
866 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
867 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
868 #endif /* STM32L071xx || STM32L081xx || */
869 /* STM32L072xx || STM32L082xx || */
870 /* STM32L073xx || STM32L083xx || */
872 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
873 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
874 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
875 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
876 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
877 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
879 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
880 #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
881 #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
882 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
884 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
885 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
886 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
887 /** @brief Force or release APB2 peripheral reset.
889 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
890 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
891 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
892 #define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST))
893 #define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST))
895 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
896 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
897 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
898 #define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
899 #define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
900 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
901 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
902 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
904 /** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
907 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
908 * @note By default, all peripheral clocks are enabled during SLEEP mode.
911 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
912 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN))
913 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN))
914 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
915 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
916 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
918 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
919 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN))
920 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
921 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
923 #if defined(STM32L073xx) || defined(STM32L083xx) || \
924 defined(STM32L072xx) || defined(STM32L082xx) || \
925 defined(STM32L071xx) || defined(STM32L081xx)
926 /** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
927 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
929 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
930 * @note By default, all peripheral clocks are enabled during SLEEP mode.
933 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOESMEN))
934 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
936 #endif /* STM32L071xx || STM32L081xx || */
937 /* STM32L072xx || STM32L082xx || */
938 /* STM32L073xx || STM32L083xx || */
940 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
941 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
943 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
944 * @note By default, all peripheral clocks are enabled during SLEEP mode.
947 #if defined(STM32L053xx) || defined(STM32L063xx) || \
948 defined(STM32L052xx) || defined(STM32L062xx) || \
949 defined(STM32L051xx) || defined(STM32L061xx)
950 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
951 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
952 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
953 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
954 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
955 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
956 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
957 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
958 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
960 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
961 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
962 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
963 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
964 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
965 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
966 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
967 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
968 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
969 #endif /* STM32L051xx || STM32L061xx || */
970 /* STM32L052xx || STM32L062xx || */
971 /* STM32L053xx || STM32L063xx */
973 #if defined(STM32L073xx) || defined(STM32L083xx) || \
974 defined(STM32L072xx) || defined(STM32L082xx) || \
975 defined(STM32L071xx) || defined(STM32L081xx)
976 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
977 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM3SMEN))
978 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
979 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM7SMEN))
980 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
981 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
982 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART4SMEN))
983 #define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART5SMEN))
984 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
985 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
986 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
987 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C3SMEN))
988 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
989 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
991 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
992 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
993 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
994 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
995 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
996 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
997 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
998 #define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
999 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
1000 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
1001 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
1002 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
1003 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
1004 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
1005 #endif /* STM32L071xx || STM32L081xx || */
1006 /* STM32L072xx || STM32L082xx || */
1007 /* STM32L073xx || STM32L083xx || */
1009 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
1010 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN))
1011 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
1012 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN))
1013 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
1014 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
1016 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
1017 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN))
1018 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
1019 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
1021 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
1022 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
1023 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
1024 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
1025 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1026 * power consumption.
1027 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1028 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1030 #define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN))
1031 #define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN))
1032 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN))
1033 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN))
1034 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN))
1036 #define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
1037 #define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
1038 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
1039 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
1040 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
1041 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
1042 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
1043 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
1045 /** @brief macro to configure the I2C1 clock (I2C1CLK).
1047 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
1048 * This parameter can be one of the following values:
1049 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
1050 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
1051 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
1053 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
1054 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
1056 /** @brief macro to get the I2C1 clock source.
1057 * @retval The clock source can be one of the following values:
1058 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
1059 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
1060 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
1062 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
1064 #if defined (STM32L073xx) || defined(STM32L083xx) || \
1065 defined(STM32L072xx) || defined(STM32L082xx) || \
1066 defined(STM32L071xx) || defined(STM32L081xx)
1067 /** @brief macro to configure the I2C3 clock (I2C3CLK).
1069 * @param __I2C3CLKSource__: specifies the I2C3 clock source.
1070 * This parameter can be one of the following values:
1071 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
1072 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
1073 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
1075 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
1076 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
1078 /** @brief macro to get the I2C3 clock source.
1079 * @retval The clock source can be one of the following values:
1080 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
1081 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
1082 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
1084 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
1086 #endif /* STM32L071xx || STM32L081xx || */
1087 /* STM32L072xx || STM32L082xx || */
1088 /* STM32L073xx || STM32L083xx || */
1090 /** @brief macro to configure the USART1 clock (USART1CLK).
1092 * @param __USART1CLKSource__: specifies the USART1 clock source.
1093 * This parameter can be one of the following values:
1094 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
1095 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
1096 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
1097 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
1099 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
1100 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
1102 /** @brief macro to get the USART1 clock source.
1103 * @retval The clock source can be one of the following values:
1104 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
1105 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
1106 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
1107 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
1109 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
1111 /** @brief macro to configure the USART2 clock (USART2CLK).
1113 * @param __USART2CLKSource__: specifies the USART2 clock source.
1114 * This parameter can be one of the following values:
1115 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
1116 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
1117 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
1118 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
1120 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
1121 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
1123 /** @brief macro to get the USART2 clock source.
1124 * @retval The clock source can be one of the following values:
1125 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
1126 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
1127 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
1128 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
1130 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
1132 /** @brief macro to configure the LPUART1 clock (LPUART1CLK).
1134 * @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
1135 * This parameter can be one of the following values:
1136 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
1137 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
1138 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
1139 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
1141 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
1142 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
1144 /** @brief macro to get the LPUART1 clock source.
1145 * @retval The clock source can be one of the following values:
1146 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
1147 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
1148 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
1149 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
1151 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
1153 /** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
1155 * @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
1156 * This parameter can be one of the following values:
1157 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
1158 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
1159 * @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
1160 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
1162 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
1163 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
1165 /** @brief macro to get the LPTIM1 clock source.
1166 * @retval The clock source can be one of the following values:
1167 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
1168 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
1169 * @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
1170 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
1172 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
1174 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
1175 /** @brief Macro to configure the USB clock (USBCLK).
1176 * @param __USBCLKSource__: specifies the USB clock source.
1177 * This parameter can be one of the following values:
1178 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
1179 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
1181 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
1182 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
1184 /** @brief Macro to get the USB clock source.
1185 * @retval The clock source can be one of the following values:
1186 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
1187 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
1189 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
1191 /** @brief Macro to configure the RNG clock (RNGCLK).
1192 * @param __RNGCLKSource__: specifies the USB clock source.
1193 * This parameter can be one of the following values:
1194 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
1195 * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
1197 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
1198 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
1200 /** @brief Macro to get the RNG clock source.
1201 * @retval The clock source can be one of the following values:
1202 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
1203 * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
1205 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
1207 /** @brief macro to select the HSI48M clock source
1208 * @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
1209 * __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
1211 * @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
1212 * USB an RNG peripherals.
1213 * This parameter can be one of the following values:
1214 * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
1215 * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
1217 #define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
1218 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
1220 /** @brief macro to get the HSI48M clock source.
1221 * @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
1222 * __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
1223 * @retval The clock source can be one of the following values:
1224 * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
1225 * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
1227 #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
1228 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
1231 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
1232 * in STOP mode to be quickly available as kernel clock for USART and I2C.
1233 * @note The Enable of this function has not effect on the HSION bit.
1234 * This parameter can be: ENABLE or DISABLE.
1237 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
1238 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
1241 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
1242 * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
1243 * This parameter can be one of the following values:
1244 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
1245 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
1246 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
1247 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
1250 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
1251 RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
1254 * @brief Macro to configures the wake up from stop clock.
1255 * @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
1256 * This parameter can be one of the following values:
1257 * @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
1258 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
1261 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
1262 RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
1264 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
1266 * @brief Enables the specified CRS interrupts.
1267 * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
1268 * This parameter can be any combination of the following values:
1269 * @arg RCC_CRS_IT_SYNCOK
1270 * @arg RCC_CRS_IT_SYNCWARN
1271 * @arg RCC_CRS_IT_ERR
1272 * @arg RCC_CRS_IT_ESYNC
1275 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
1278 * @brief Disables the specified CRS interrupts.
1279 * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
1280 * This parameter can be any combination of the following values:
1281 * @arg RCC_CRS_IT_SYNCOK
1282 * @arg RCC_CRS_IT_SYNCWARN
1283 * @arg RCC_CRS_IT_ERR
1284 * @arg RCC_CRS_IT_ESYNC
1287 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
1289 /** @brief Check the CRS interrupt has occurred or not.
1290 * @param __INTERRUPT__: specifies the CRS interrupt source to check.
1291 * This parameter can be one of the following values:
1292 * @arg RCC_CRS_IT_SYNCOK
1293 * @arg RCC_CRS_IT_SYNCWARN
1294 * @arg RCC_CRS_IT_ERR
1295 * @arg RCC_CRS_IT_ESYNC
1296 * @retval The new state of __INTERRUPT__ (SET or RESET).
1298 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
1300 /** @brief Clear the CRS interrupt pending bits
1301 * bits to clear the selected interrupt pending bits.
1302 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1303 * This parameter can be any combination of the following values:
1304 * @arg RCC_CRS_IT_SYNCOK
1305 * @arg RCC_CRS_IT_SYNCWARN
1306 * @arg RCC_CRS_IT_ERR
1307 * @arg RCC_CRS_IT_ESYNC
1308 * @arg RCC_CRS_IT_TRIMOVF
1309 * @arg RCC_CRS_IT_SYNCERR
1310 * @arg RCC_CRS_IT_SYNCMISS
1312 /* CRS IT Error Mask */
1313 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
1315 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
1316 (CRS->ICR = (__INTERRUPT__)))
1319 * @brief Checks whether the specified CRS flag is set or not.
1320 * @param _FLAG_: specifies the flag to check.
1321 * This parameter can be one of the following values:
1322 * @arg RCC_CRS_FLAG_SYNCOK
1323 * @arg RCC_CRS_FLAG_SYNCWARN
1324 * @arg RCC_CRS_FLAG_ERR
1325 * @arg RCC_CRS_FLAG_ESYNC
1326 * @arg RCC_CRS_FLAG_TRIMOVF
1327 * @arg RCC_CRS_FLAG_SYNCERR
1328 * @arg RCC_CRS_FLAG_SYNCMISS
1329 * @retval The new state of _FLAG_ (TRUE or FALSE).
1331 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
1334 * @brief Clears the CRS specified FLAG.
1335 * @param _FLAG_: specifies the flag to clear.
1336 * This parameter can be one of the following values:
1337 * @arg RCC_CRS_FLAG_SYNCOK
1338 * @arg RCC_CRS_FLAG_SYNCWARN
1339 * @arg RCC_CRS_FLAG_ERR
1340 * @arg RCC_CRS_FLAG_ESYNC
1341 * @arg RCC_CRS_FLAG_TRIMOVF
1342 * @arg RCC_CRS_FLAG_SYNCERR
1343 * @arg RCC_CRS_FLAG_SYNCMISS
1347 /* CRS Flag Error Mask */
1348 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
1350 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
1351 (CRS->ICR = (__FLAG__)))
1355 * @brief Enables the oscillator clock for frequency error counter.
1356 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
1360 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
1363 * @brief Disables the oscillator clock for frequency error counter.
1367 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
1370 * @brief Enables the automatic hardware adjustment of TRIM bits.
1371 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
1375 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
1378 * @brief Enables or disables the automatic hardware adjustment of TRIM bits.
1382 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
1385 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
1386 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
1387 * of the synchronization source after prescaling. It is then decreased by one in order to
1388 * reach the expected synchronization on the zero value. The formula is the following:
1389 * RELOAD = (fTARGET / fSYNC) -1
1390 * @param _FTARGET_ Target frequency (value in Hz)
1391 * @param _FSYNC_ Synchronization signal frequency (value in Hz)
1394 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
1396 #endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
1398 #if defined(STM32L073xx) || defined(STM32L083xx) || \
1399 defined(STM32L072xx) || defined(STM32L082xx) || \
1400 defined(STM32L071xx) || defined(STM32L081xx)
1401 /** @brief Enable or disable the HSI OUT .
1402 * @note After reset, the HSI output is not available
1405 #define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
1406 #define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
1408 #endif /* STM32L071xx || STM32L081xx || */
1409 /* STM32L072xx || STM32L082xx || */
1410 /* STM32L073xx || STM32L083xx */
1412 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) ||\
1413 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx)
1416 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
1417 * @note After enabling the HSI48, the application software should wait on
1418 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
1419 * be used to clock the USB.
1420 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
1422 #define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
1423 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \
1424 SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \
1426 #define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
1427 SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \
1429 /** @brief Enable or disable the HSI48M DIV6 OUT .
1430 * @note After reset, the HSI48Mhz (divided by 6) output is not available
1433 #define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
1434 #define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
1436 #endif /* STM32L071xx || STM32L081xx || */
1437 /* STM32L072xx || STM32L082xx || */
1438 /* STM32L073xx || STM32L083xx */
1444 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
1448 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
1452 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1453 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1454 void HAL_RCCEx_EnableLSECSS(void);
1455 void HAL_RCCEx_DisableLSECSS(void);
1456 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
1457 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
1458 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
1459 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
1460 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
1461 void HAL_RCCEx_EnableHSI48_VREFINT(void);
1462 void HAL_RCCEx_DisableHSI48_VREFINT(void);
1463 #endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
1484 #endif /* __STM32L0xx_HAL_RCC_EX_H */
1486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/