2 ******************************************************************************
3 * @file stm32l0xx_hal_tim.c
4 * @author MCD Application Team
6 * @date 06-February-2015
7 * @brief TIM HAL module driver.
8 * @brief This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Timer Base Initialization
12 * + Timer Base Start Interruption
13 * + Timer Base Start DMA
14 * + Timer Output Compare/PWM Initialization
15 * + Timer Output Compare/PWM Channel Configuration
16 * + Timer Output Compare/PWM Start
17 * + Timer Output Compare/PWM Start Interruption
18 * + Timer Output Compare/PWM Start DMA
19 * + Timer Input Capture Initialization
20 * + Timer Input Capture Channel Configuration
21 * + Timer Input Capture Start
22 * + Timer Input Capture Start Interruption
23 * + Timer Input Capture Start DMA
24 * + Timer One Pulse Initialization
25 * + Timer One Pulse Channel Configuration
26 * + Timer One Pulse Start
27 * + Timer Encoder Interface Initialization
28 * + Timer Encoder Interface Start
29 * + Timer Encoder Interface Start Interruption
30 * + Timer Encoder Interface Start DMA
31 * + Timer OCRef clear configuration
32 * + Timer External Clock configuration
33 * + Timer Complementary signal bread and dead time configuration
34 * + Timer Master and Slave synchronization configuration
36 ==============================================================================
37 ##### TIMER Generic features #####
38 ==============================================================================
39 [..] The Timer features include:
40 (#) 16-bit up, down, up/down auto-reload counter.
41 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
42 frequency either by any factor between 1 and 65536.
43 (#) Up to 4 independent channels for:
46 (++) PWM generation (Edge and Center-aligned Mode)
47 (++) One-pulse mode output
48 (#) Synchronization circuit to control the timer with external signals and to interconnect
49 several timers together.
50 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
53 ##### How to use this driver #####
54 ================================================================================
56 (#) Initialize the TIM low level resources by implementing the following functions
57 depending from feature used :
58 (++) Time Base : HAL_TIM_Base_MspInit()
59 (++) Input Capture : HAL_TIM_IC_MspInit()
60 (++) Output Compare : HAL_TIM_OC_MspInit()
61 (++) PWM generation : HAL_TIM_PWM_MspInit()
62 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
63 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
65 (#) Initialize the TIM low level resources :
66 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
67 (##) TIM pins configuration
68 (+++) Enable the clock for the TIM GPIOs using the following function:
69 __HAL_RCC_GPIOx_CLK_ENABLE();
70 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
72 (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
73 using the following function:
74 HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
76 (#) Configure the TIM in the desired functioning mode using one of the
77 initialization function of this driver:
78 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
79 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
80 Output Compare signal.
81 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
83 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
85 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode.
86 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
88 (#) Activate the TIM peripheral using one of the start functions:
89 HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(),
90 HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(),
91 HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(),
92 HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(),
93 HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(),
94 HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT()
96 (#) The DMA Burst is managed with the two following functions:
97 HAL_TIM_DMABurst_WriteStart
98 HAL_TIM_DMABurst_ReadStart
101 ******************************************************************************
104 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
106 * Redistribution and use in source and binary forms, with or without modification,
107 * are permitted provided that the following conditions are met:
108 * 1. Redistributions of source code must retain the above copyright notice,
109 * this list of conditions and the following disclaimer.
110 * 2. Redistributions in binary form must reproduce the above copyright notice,
111 * this list of conditions and the following disclaimer in the documentation
112 * and/or other materials provided with the distribution.
113 * 3. Neither the name of STMicroelectronics nor the names of its contributors
114 * may be used to endorse or promote products derived from this software
115 * without specific prior written permission.
117 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
118 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
119 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
120 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
121 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
122 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
123 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
124 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
125 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
126 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
128 ******************************************************************************
131 /* Includes ------------------------------------------------------------------*/
132 #include "stm32l0xx_hal.h"
134 /** @addtogroup STM32L0xx_HAL_Driver
139 * @brief TIM HAL module driver
143 #ifdef HAL_TIM_MODULE_ENABLED
145 /* Private typedef -----------------------------------------------------------*/
146 /* Private define ------------------------------------------------------------*/
147 /* Private macro -------------------------------------------------------------*/
148 /* Private variables ---------------------------------------------------------*/
149 /* Private function prototypes -----------------------------------------------*/
150 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
152 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
153 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
154 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
155 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
156 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
157 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
158 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
159 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
161 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
162 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
163 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
166 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,TIM_SlaveConfigTypeDef * sSlaveConfig);
168 /*******************************************************************************/
169 /* Exported functions ---------------------------------------------------------*/
170 /*******************************************************************************/
172 /** @addtogroup TIM_Exported_Functions
176 /** @addtogroup TIM_Exported_Functions_Group1
177 * @brief Time Base functions
180 ==============================================================================
181 ##### Timer Base functions #####
182 ==============================================================================
184 This section provides functions allowing to:
185 (+) Initialize and configure the TIM base.
186 (+) De-initialize the TIM base.
187 (+) Start the Timer Base.
188 (+) Stop the Timer Base.
189 (+) Start the Timer Base and enable interrupt.
190 (+) Stop the Timer Base and disable interrupt.
191 (+) Start the Timer Base and enable DMA transfer.
192 (+) Stop the Timer Base and disable DMA transfer.
198 * @brief Initializes the TIM Time base Unit according to the specified
199 * parameters in the TIM_HandleTypeDef and create the associated handle.
200 * @param htim : TIM handle
203 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
205 /* Check the TIM handle allocation */
211 /* Check the parameters */
212 assert_param(IS_TIM_INSTANCE(htim->Instance));
213 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
214 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
215 assert_param(IS_TIM_PERIOD(htim->Init.Period));
216 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
218 if(htim->State == HAL_TIM_STATE_RESET)
220 /* Init the low level hardware : GPIO, CLOCK, NVIC */
221 HAL_TIM_Base_MspInit(htim);
224 /* Set the TIM state */
225 htim->State= HAL_TIM_STATE_BUSY;
227 /* Set the Time Base configuration */
228 TIM_Base_SetConfig(htim->Instance, &htim->Init);
230 /* Initialize the TIM state*/
231 htim->State= HAL_TIM_STATE_READY;
237 * @brief DeInitializes the TIM Base peripheral
238 * @param htim : TIM handle
241 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
243 /* Check the parameters */
244 assert_param(IS_TIM_INSTANCE(htim->Instance));
246 htim->State = HAL_TIM_STATE_BUSY;
248 /* Disable the TIM Peripheral Clock */
249 __HAL_TIM_DISABLE(htim);
251 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
252 HAL_TIM_Base_MspDeInit(htim);
254 /* Change TIM state */
255 htim->State = HAL_TIM_STATE_RESET;
264 * @brief Initializes the TIM Base MSP.
265 * @param htim : TIM handle
268 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
270 /* NOTE : This function Should not be modified, when the callback is needed,
271 the HAL_TIM_Base_MspInit could be implemented in the user file
276 * @brief DeInitializes TIM Base MSP.
277 * @param htim : TIM handle
280 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
282 /* NOTE : This function Should not be modified, when the callback is needed,
283 the HAL_TIM_Base_MspDeInit could be implemented in the user file
288 * @brief Starts the TIM Base generation.
289 * @param htim : TIM handle
292 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
294 /* Check the parameters */
295 assert_param(IS_TIM_INSTANCE(htim->Instance));
297 /* Set the TIM state */
298 htim->State= HAL_TIM_STATE_BUSY;
300 /* Enable the Peripheral */
301 __HAL_TIM_ENABLE(htim);
303 /* Change the TIM state*/
304 htim->State= HAL_TIM_STATE_READY;
306 /* Return function status */
311 * @brief Stops the TIM Base generation.
312 * @param htim : TIM handle
315 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
317 /* Check the parameters */
318 assert_param(IS_TIM_INSTANCE(htim->Instance));
320 /* Set the TIM state */
321 htim->State= HAL_TIM_STATE_BUSY;
323 /* Disable the Peripheral */
324 __HAL_TIM_DISABLE(htim);
326 /* Change the TIM state*/
327 htim->State= HAL_TIM_STATE_READY;
329 /* Return function status */
334 * @brief Starts the TIM Base generation in interrupt mode.
335 * @param htim : TIM handle
338 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
340 /* Check the parameters */
341 assert_param(IS_TIM_INSTANCE(htim->Instance));
343 /* Enable the TIM Update interrupt */
344 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
346 /* Enable the Peripheral */
347 __HAL_TIM_ENABLE(htim);
349 /* Return function status */
354 * @brief Stops the TIM Base generation in interrupt mode.
355 * @param htim : TIM handle
358 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
360 /* Check the parameters */
361 assert_param(IS_TIM_INSTANCE(htim->Instance));
362 /* Disable the TIM Update interrupt */
363 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
365 /* Disable the Peripheral */
366 __HAL_TIM_DISABLE(htim);
368 /* Return function status */
373 * @brief Starts the TIM Base generation in DMA mode.
374 * @param htim : TIM handle
375 * @param pData: The source Buffer address.
376 * @param Length: The length of data to be transferred from memory to peripheral.
379 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
381 /* Check the parameters */
382 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
384 if((htim->State == HAL_TIM_STATE_BUSY))
388 else if((htim->State == HAL_TIM_STATE_READY))
390 if((pData == 0 ) && (Length > 0))
396 htim->State = HAL_TIM_STATE_BUSY;
399 /* Set the DMA Period elapsed callback */
400 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
402 /* Set the DMA error callback */
403 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
405 /* Enable the DMA Stream */
406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
408 /* Enable the TIM Update DMA request */
409 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
411 /* Enable the Peripheral */
412 __HAL_TIM_ENABLE(htim);
414 /* Return function status */
419 * @brief Stops the TIM Base generation in DMA mode.
420 * @param htim : TIM handle
423 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
425 /* Check the parameters */
426 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
428 /* Disable the TIM Update DMA request */
429 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
431 /* Disable the Peripheral */
432 __HAL_TIM_DISABLE(htim);
434 /* Change the htim state */
435 htim->State = HAL_TIM_STATE_READY;
437 /* Return function status */
446 /** @addtogroup TIM_Exported_Functions_Group2
447 * @brief Time Output Compare functions
450 ==============================================================================
451 ##### Timer Output Compare functions #####
452 ==============================================================================
454 This section provides functions allowing to:
455 (+) Initialize and configure the TIM Output Compare.
456 (+) De-initialize the TIM Output Compare.
457 (+) Start the Timer Output Compare.
458 (+) Stop the Timer Output Compare.
459 (+) Start the Timer Output Compare and enable interrupt.
460 (+) Stop the Timer Output Compare and disable interrupt.
461 (+) Start the Timer Output Compare and enable DMA transfer.
462 (+) Stop the Timer Output Compare and disable DMA transfer.
468 * @brief Initializes the TIM Output Compare according to the specified
469 * parameters in the TIM_HandleTypeDef and create the associated handle.
470 * @param htim: TIM Output Compare handle
473 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
475 /* Check the TIM handle allocation */
481 /* Check the parameters */
482 assert_param(IS_TIM_INSTANCE(htim->Instance));
483 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
484 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
485 assert_param(IS_TIM_PERIOD(htim->Init.Period));
486 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
488 if(htim->State == HAL_TIM_STATE_RESET)
490 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/
491 HAL_TIM_OC_MspInit(htim);
493 /* Set the TIM state */
494 htim->State= HAL_TIM_STATE_BUSY;
496 /* Init the base time for the Output Compare */
497 TIM_Base_SetConfig(htim->Instance, &htim->Init);
499 /* Initialize the TIM state*/
500 htim->State= HAL_TIM_STATE_READY;
506 * @brief DeInitializes the TIM peripheral
507 * @param htim: TIM Output Compare handle
510 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
512 /* Check the parameters */
513 assert_param(IS_TIM_INSTANCE(htim->Instance));
515 htim->State = HAL_TIM_STATE_BUSY;
517 /* Disable the TIM Peripheral Clock */
518 __HAL_TIM_DISABLE(htim);
520 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
521 HAL_TIM_OC_MspDeInit(htim);
523 /* Change TIM state */
524 htim->State = HAL_TIM_STATE_RESET;
533 * @brief Initializes the TIM Output Compare MSP.
534 * @param htim : TIM handle
537 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
539 /* NOTE : This function Should not be modified, when the callback is needed,
540 the HAL_TIM_OC_MspInit could be implemented in the user file
545 * @brief DeInitializes TIM Output Compare MSP.
546 * @param htim : TIM handle
549 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
551 /* NOTE : This function Should not be modified, when the callback is needed,
552 the HAL_TIM_OC_MspDeInit could be implemented in the user file
557 * @brief Starts the TIM Output Compare signal generation.
558 * @param htim : TIM handle
559 * @param Channel: TIM Channel to be enabled.
560 * This parameter can be one of the following values:
561 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
562 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
563 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
564 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
567 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
569 /* Check the parameters */
570 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
572 /* Enable the Output compare channel */
573 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
575 /* Enable the Peripheral */
576 __HAL_TIM_ENABLE(htim);
578 /* Return function status */
583 * @brief Stops the TIM Output Compare signal generation.
584 * @param htim : TIM handle
585 * @param Channel: TIM Channel to be disabled.
586 * This parameter can be one of the following values:
587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
593 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
595 /* Check the parameters */
596 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
598 /* Disable the Output compare channel */
599 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
601 /* Disable the Peripheral */
602 __HAL_TIM_DISABLE(htim);
604 /* Return function status */
609 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
610 * @param htim : TIM handle
611 * @param Channel: TIM Channel to be enabled.
612 * This parameter can be one of the following values:
613 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
614 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
615 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
616 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
619 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
621 /* Check the parameters */
622 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
628 /* Enable the TIM Capture/Compare 1 interrupt */
629 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
635 /* Enable the TIM Capture/Compare 2 interrupt */
636 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
642 /* Enable the TIM Capture/Compare 3 interrupt */
643 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
649 /* Enable the TIM Capture/Compare 4 interrupt */
650 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
658 /* Enable the Output compare channel */
659 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
661 /* Enable the Peripheral */
662 __HAL_TIM_ENABLE(htim);
664 /* Return function status */
669 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
670 * @param htim : TIM handle
671 * @param Channel: TIM Channel to be disabled.
672 * This parameter can be one of the following values:
673 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
674 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
675 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
676 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
679 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
681 /* Check the parameters */
682 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
688 /* Disable the TIM Capture/Compare 1 interrupt */
689 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
695 /* Disable the TIM Capture/Compare 2 interrupt */
696 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
702 /* Disable the TIM Capture/Compare 3 interrupt */
703 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
709 /* Disable the TIM Capture/Compare 4 interrupt */
710 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
718 /* Disable the Output compare channel */
719 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
721 /* Disable the Peripheral */
722 __HAL_TIM_DISABLE(htim);
724 /* Return function status */
729 * @brief Starts the TIM Output Compare signal generation in DMA mode.
730 * @param htim : TIM handle
731 * @param Channel: TIM Channel to be enabled.
732 * This parameter can be one of the following values:
733 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
734 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
735 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
736 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
737 * @param pData: The source Buffer address.
738 * @param Length: The length of data to be transferred from memory to TIM peripheral
741 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
743 /* Check the parameters */
744 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
746 if((htim->State == HAL_TIM_STATE_BUSY))
750 else if((htim->State == HAL_TIM_STATE_READY))
752 if(((uint32_t)pData == 0 ) && (Length > 0))
758 htim->State = HAL_TIM_STATE_BUSY;
765 /* Set the DMA Period elapsed callback */
766 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
768 /* Set the DMA error callback */
769 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
771 /* Enable the DMA Stream */
772 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
774 /* Enable the TIM Capture/Compare 1 DMA request */
775 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
781 /* Set the DMA Period elapsed callback */
782 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
784 /* Set the DMA error callback */
785 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
787 /* Enable the DMA Stream */
788 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
790 /* Enable the TIM Capture/Compare 2 DMA request */
791 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
797 /* Set the DMA Period elapsed callback */
798 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
800 /* Set the DMA error callback */
801 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
803 /* Enable the DMA Stream */
804 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
806 /* Enable the TIM Capture/Compare 3 DMA request */
807 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
813 /* Set the DMA Period elapsed callback */
814 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
816 /* Set the DMA error callback */
817 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
819 /* Enable the DMA Stream */
820 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
822 /* Enable the TIM Capture/Compare 4 DMA request */
823 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
831 /* Enable the Output compare channel */
832 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
834 /* Enable the Peripheral */
835 __HAL_TIM_ENABLE(htim);
837 /* Return function status */
842 * @brief Stops the TIM Output Compare signal generation in DMA mode.
843 * @param htim : TIM handle
844 * @param Channel: TIM Channel to be disabled.
845 * This parameter can be one of the following values:
846 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
847 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
848 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
849 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
852 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
854 /* Check the parameters */
855 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
861 /* Disable the TIM Capture/Compare 1 DMA request */
862 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
868 /* Disable the TIM Capture/Compare 2 DMA request */
869 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
875 /* Disable the TIM Capture/Compare 3 DMA request */
876 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
882 /* Disable the TIM Capture/Compare 4 interrupt */
883 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
891 /* Disable the Output compare channel */
892 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
894 /* Disable the Peripheral */
895 __HAL_TIM_DISABLE(htim);
897 /* Change the htim state */
898 htim->State = HAL_TIM_STATE_READY;
900 /* Return function status */
908 /** @addtogroup TIM_Exported_Functions_Group3
909 * @brief Time PWM functions
912 ==============================================================================
913 ##### Timer PWM functions #####
914 ==============================================================================
916 This section provides functions allowing to:
917 (+) Initialize and configure the TIM OPWM.
918 (+) De-initialize the TIM PWM.
919 (+) Start the Timer PWM.
920 (+) Stop the Timer PWM.
921 (+) Start the Timer PWM and enable interrupt.
922 (+) Stop the Timer PWM and disable interrupt.
923 (+) Start the Timer PWM and enable DMA transfer.
924 (+) Stop the Timer PWM and disable DMA transfer.
930 * @brief Initializes the TIM PWM Time Base according to the specified
931 * parameters in the TIM_HandleTypeDef and create the associated handle.
932 * @param htim : TIM handle
937 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
939 /* Check the TIM handle allocation */
945 /* Check the parameters */
946 assert_param(IS_TIM_INSTANCE(htim->Instance));
947 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
948 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
949 assert_param(IS_TIM_PERIOD(htim->Init.Period));
950 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
952 if(htim->State == HAL_TIM_STATE_RESET)
954 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
955 HAL_TIM_PWM_MspInit(htim);
958 /* Set the TIM state */
959 htim->State= HAL_TIM_STATE_BUSY;
961 /* Init the base time for the PWM */
962 TIM_Base_SetConfig(htim->Instance, &htim->Init);
964 /* Initialize the TIM state*/
965 htim->State= HAL_TIM_STATE_READY;
971 * @brief DeInitializes the TIM peripheral
972 * @param htim : TIM handle
975 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
977 /* Check the parameters */
978 assert_param(IS_TIM_INSTANCE(htim->Instance));
980 htim->State = HAL_TIM_STATE_BUSY;
982 /* Disable the TIM Peripheral Clock */
983 __HAL_TIM_DISABLE(htim);
985 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
986 HAL_TIM_PWM_MspDeInit(htim);
988 /* Change TIM state */
989 htim->State = HAL_TIM_STATE_RESET;
998 * @brief Initializes the TIM PWM MSP.
999 * @param htim : TIM handle
1002 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1004 /* NOTE : This function Should not be modified, when the callback is needed,
1005 the HAL_TIM_PWM_MspInit could be implemented in the user file
1010 * @brief DeInitializes TIM PWM MSP.
1011 * @param htim : TIM handle
1014 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1016 /* NOTE : This function Should not be modified, when the callback is needed,
1017 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1022 * @brief Starts the PWM signal generation.
1023 * @param htim : TIM handle
1024 * @param Channel: TIM Channels to be enabled.
1025 * This parameter can be one of the following values:
1026 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1027 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1028 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1029 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1030 * @retval HAL status
1032 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1034 /* Check the parameters */
1035 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1037 /* Enable the Capture compare channel */
1038 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1040 /* Enable the Peripheral */
1041 __HAL_TIM_ENABLE(htim);
1043 /* Return function status */
1048 * @brief Stops the PWM signal generation.
1049 * @param htim : TIM handle
1050 * @param Channel: TIM Channels to be disabled.
1051 * This parameter can be one of the following values:
1052 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1053 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1054 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1055 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1056 * @retval HAL status
1058 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1060 /* Check the parameters */
1061 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1063 /* Disable the Capture compare channel */
1064 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1066 /* Disable the Peripheral */
1067 __HAL_TIM_DISABLE(htim);
1069 /* Change the htim state */
1070 htim->State = HAL_TIM_STATE_READY;
1072 /* Return function status */
1077 * @brief Starts the PWM signal generation in interrupt mode.
1078 * @param htim : TIM handle
1079 * @param Channel: TIM Channel to be disabled.
1080 * This parameter can be one of the following values:
1081 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1082 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1083 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1084 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1085 * @retval HAL status
1087 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1089 /* Check the parameters */
1090 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1096 /* Enable the TIM Capture/Compare 1 interrupt */
1097 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1103 /* Enable the TIM Capture/Compare 2 interrupt */
1104 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1110 /* Enable the TIM Capture/Compare 3 interrupt */
1111 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1117 /* Enable the TIM Capture/Compare 4 interrupt */
1118 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1126 /* Enable the Capture compare channel */
1127 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1129 /* Enable the Peripheral */
1130 __HAL_TIM_ENABLE(htim);
1132 /* Return function status */
1137 * @brief Stops the PWM signal generation in interrupt mode.
1138 * @param htim : TIM handle
1139 * @param Channel: TIM Channels to be disabled.
1140 * This parameter can be one of the following values:
1141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1143 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1144 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1145 * @retval HAL status
1147 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1149 /* Check the parameters */
1150 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1156 /* Disable the TIM Capture/Compare 1 interrupt */
1157 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1163 /* Disable the TIM Capture/Compare 2 interrupt */
1164 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1170 /* Disable the TIM Capture/Compare 3 interrupt */
1171 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1177 /* Disable the TIM Capture/Compare 4 interrupt */
1178 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1186 /* Disable the Capture compare channel */
1187 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1189 /* Disable the Peripheral */
1190 __HAL_TIM_DISABLE(htim);
1192 /* Return function status */
1197 * @brief Starts the TIM PWM signal generation in DMA mode.
1198 * @param htim : TIM handle
1199 * @param Channel: TIM Channels to be enabled.
1200 * This parameter can be one of the following values:
1201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1205 * @param pData: The source Buffer address. This buffer contains the values
1206 * which will be loaded inside the capture/compare registers.
1207 * @param Length: The length of data to be transferred from memory to TIM peripheral
1208 * @retval HAL status
1210 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1212 /* Check the parameters */
1213 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1215 if((htim->State == HAL_TIM_STATE_BUSY))
1219 else if((htim->State == HAL_TIM_STATE_READY))
1221 if(((uint32_t)pData == 0 ) && (Length > 0))
1227 htim->State = HAL_TIM_STATE_BUSY;
1234 /* Set the DMA Period elapsed callback */
1235 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1237 /* Set the DMA error callback */
1238 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1240 /* Enable the DMA Stream */
1241 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1243 /* Enable the TIM Capture/Compare 1 DMA request */
1244 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1250 /* Set the DMA Period elapsed callback */
1251 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1253 /* Set the DMA error callback */
1254 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1256 /* Enable the DMA Stream */
1257 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1259 /* Enable the TIM Capture/Compare 2 DMA request */
1260 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1266 /* Set the DMA Period elapsed callback */
1267 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1269 /* Set the DMA error callback */
1270 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1272 /* Enable the DMA Stream */
1273 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1275 /* Enable the TIM Output Capture/Compare 3 request */
1276 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1282 /* Set the DMA Period elapsed callback */
1283 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1285 /* Set the DMA error callback */
1286 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1288 /* Enable the DMA Stream */
1289 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1291 /* Enable the TIM Capture/Compare 4 DMA request */
1292 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1300 /* Enable the Capture compare channel */
1301 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1303 /* Enable the Peripheral */
1304 __HAL_TIM_ENABLE(htim);
1306 /* Return function status */
1311 * @brief Stops the TIM PWM signal generation in DMA mode.
1312 * @param htim : TIM handle
1313 * @param Channel: TIM Channels to be disabled.
1314 * This parameter can be one of the following values:
1315 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1316 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1317 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1318 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1319 * @retval HAL status
1321 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1323 /* Check the parameters */
1324 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1330 /* Disable the TIM Capture/Compare 1 DMA request */
1331 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1337 /* Disable the TIM Capture/Compare 2 DMA request */
1338 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1344 /* Disable the TIM Capture/Compare 3 DMA request */
1345 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1351 /* Disable the TIM Capture/Compare 4 interrupt */
1352 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1360 /* Disable the Capture compare channel */
1361 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1363 /* Disable the Peripheral */
1364 __HAL_TIM_DISABLE(htim);
1366 /* Change the htim state */
1367 htim->State = HAL_TIM_STATE_READY;
1369 /* Return function status */
1377 /** @addtogroup TIM_Exported_Functions_Group4
1378 * @brief Time Input Capture functions
1381 ==============================================================================
1382 ##### Timer Input Capture functions #####
1383 ==============================================================================
1385 This section provides functions allowing to:
1386 (+) Initialize and configure the TIM Input Capture.
1387 (+) De-initialize the TIM Input Capture.
1388 (+) Start the Timer Input Capture.
1389 (+) Stop the Timer Input Capture.
1390 (+) Start the Timer Input Capture and enable interrupt.
1391 (+) Stop the Timer Input Capture and disable interrupt.
1392 (+) Start the Timer Input Capture and enable DMA transfer.
1393 (+) Stop the Timer Input Capture and disable DMA transfer.
1399 * @brief Initializes the TIM Input Capture Time base according to the specified
1400 * parameters in the TIM_HandleTypeDef and create the associated handle.
1401 * @param htim: TIM Input Capture handle
1402 * @retval HAL status
1404 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1406 /* Check the TIM handle allocation */
1412 /* Check the parameters */
1413 assert_param(IS_TIM_INSTANCE(htim->Instance));
1414 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1415 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1416 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1417 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
1419 if(htim->State == HAL_TIM_STATE_RESET)
1421 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1422 HAL_TIM_IC_MspInit(htim);
1425 /* Set the TIM state */
1426 htim->State= HAL_TIM_STATE_BUSY;
1428 /* Init the base time for the input capture */
1429 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1431 /* Initialize the TIM state*/
1432 htim->State= HAL_TIM_STATE_READY;
1438 * @brief DeInitializes the TIM peripheral
1439 * @param htim: TIM Input Capture handle
1440 * @retval HAL status
1442 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1444 /* Check the parameters */
1445 assert_param(IS_TIM_INSTANCE(htim->Instance));
1447 htim->State = HAL_TIM_STATE_BUSY;
1449 /* Disable the TIM Peripheral Clock */
1450 __HAL_TIM_DISABLE(htim);
1452 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1453 HAL_TIM_IC_MspDeInit(htim);
1455 /* Change TIM state */
1456 htim->State = HAL_TIM_STATE_RESET;
1465 * @brief Initializes the TIM INput Capture MSP.
1466 * @param htim : TIM handle
1469 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1471 /* NOTE : This function Should not be modified, when the callback is needed,
1472 the HAL_TIM_IC_MspInit could be implemented in the user file
1477 * @brief DeInitializes TIM Input Capture MSP.
1478 * @param htim : TIM handle
1481 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1483 /* NOTE : This function Should not be modified, when the callback is needed,
1484 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1488 * @brief Starts the TIM Input Capture measurement.
1489 * @param htim : TIM handle
1490 * @param Channel: TIM Channels to be enabled.
1491 * This parameter can be one of the following values:
1492 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1493 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1494 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1495 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1496 * @retval HAL status
1498 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1500 /* Check the parameters */
1501 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1503 /* Enable the Input Capture channel */
1504 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1506 /* Enable the Peripheral */
1507 __HAL_TIM_ENABLE(htim);
1509 /* Return function status */
1514 * @brief Stops the TIM Input Capture measurement.
1515 * @param htim : TIM handle
1516 * @param Channel: TIM Channels to be disabled.
1517 * This parameter can be one of the following values:
1518 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1519 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1520 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1521 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1522 * @retval HAL status
1524 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1526 /* Check the parameters */
1527 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1529 /* Disable the Input Capture channel */
1530 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1532 /* Disable the Peripheral */
1533 __HAL_TIM_DISABLE(htim);
1535 /* Return function status */
1540 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1541 * @param htim : TIM handle
1542 * @param Channel: TIM Channels to be enabled.
1543 * This parameter can be one of the following values:
1544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1546 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1547 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1548 * @retval HAL status
1550 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1552 /* Check the parameters */
1553 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1559 /* Enable the TIM Capture/Compare 1 interrupt */
1560 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1566 /* Enable the TIM Capture/Compare 2 interrupt */
1567 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1573 /* Enable the TIM Capture/Compare 3 interrupt */
1574 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1580 /* Enable the TIM Capture/Compare 4 interrupt */
1581 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1588 /* Enable the Input Capture channel */
1589 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1591 /* Enable the Peripheral */
1592 __HAL_TIM_ENABLE(htim);
1594 /* Return function status */
1599 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1600 * @param htim : TIM handle
1601 * @param Channel : TIM Channels to be disabled
1602 * This parameter can be one of the following values:
1603 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1604 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1605 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1606 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1607 * @retval HAL status
1609 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1611 /* Check the parameters */
1612 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1618 /* Disable the TIM Capture/Compare 1 interrupt */
1619 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1625 /* Disable the TIM Capture/Compare 2 interrupt */
1626 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1632 /* Disable the TIM Capture/Compare 3 interrupt */
1633 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1639 /* Disable the TIM Capture/Compare 4 interrupt */
1640 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1648 /* Disable the Input Capture channel */
1649 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1651 /* Disable the Peripheral */
1652 __HAL_TIM_DISABLE(htim);
1654 /* Return function status */
1659 * @brief Starts the TIM Input Capture measurement on in DMA mode.
1660 * @param htim : TIM handle
1661 * @param Channel : TIM Channels to be enabled
1662 * This parameter can be one of the following values:
1663 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1664 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1665 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1666 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1667 * @param pData: The destination Buffer address.
1668 * @param Length: The length of data to be transferred from TIM peripheral to memory.
1669 * @retval HAL status
1671 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1673 /* Check the parameters */
1674 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1675 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1677 if((htim->State == HAL_TIM_STATE_BUSY))
1681 else if((htim->State == HAL_TIM_STATE_READY))
1683 if((pData == 0 ) && (Length > 0))
1689 htim->State = HAL_TIM_STATE_BUSY;
1697 /* Set the DMA Period elapsed callback */
1698 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
1700 /* Set the DMA error callback */
1701 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1703 /* Enable the DMA Stream */
1704 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1706 /* Enable the TIM Capture/Compare 1 DMA request */
1707 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1713 /* Set the DMA Period elapsed callback */
1714 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
1716 /* Set the DMA error callback */
1717 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1719 /* Enable the DMA Stream */
1720 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1722 /* Enable the TIM Capture/Compare 2 DMA request */
1723 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1729 /* Set the DMA Period elapsed callback */
1730 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
1732 /* Set the DMA error callback */
1733 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1735 /* Enable the DMA Stream */
1736 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1738 /* Enable the TIM Capture/Compare 3 DMA request */
1739 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1745 /* Set the DMA Period elapsed callback */
1746 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
1748 /* Set the DMA error callback */
1749 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1751 /* Enable the DMA Stream */
1752 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1754 /* Enable the TIM Capture/Compare 4 DMA request */
1755 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1763 /* Enable the Input Capture channel */
1764 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1766 /* Enable the Peripheral */
1767 __HAL_TIM_ENABLE(htim);
1769 /* Return function status */
1774 * @brief Stops the TIM Input Capture measurement on in DMA mode.
1775 * @param htim : TIM handle
1776 * @param Channel : TIM Channels to be disabled
1777 * This parameter can be one of the following values:
1778 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1779 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1780 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1781 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1782 * @retval HAL status
1784 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1786 /* Check the parameters */
1787 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1788 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1794 /* Disable the TIM Capture/Compare 1 DMA request */
1795 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1801 /* Disable the TIM Capture/Compare 2 DMA request */
1802 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1808 /* Disable the TIM Capture/Compare 3 DMA request */
1809 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1815 /* Disable the TIM Capture/Compare 4 DMA request */
1816 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1824 /* Disable the Input Capture channel */
1825 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1827 /* Disable the Peripheral */
1828 __HAL_TIM_DISABLE(htim);
1830 /* Change the htim state */
1831 htim->State = HAL_TIM_STATE_READY;
1833 /* Return function status */
1841 /** @addtogroup TIM_Exported_Functions_Group5
1842 * @brief Time One Pulse functions
1845 ==============================================================================
1846 ##### Timer One Pulse functions #####
1847 ==============================================================================
1849 This section provides functions allowing to:
1850 (+) Initialize and configure the TIM One Pulse.
1851 (+) De-initialize the TIM One Pulse.
1852 (+) Start the Timer One Pulse.
1853 (+) Stop the Timer One Pulse.
1854 (+) Start the Timer One Pulse and enable interrupt.
1855 (+) Stop the Timer One Pulse and disable interrupt.
1856 (+) Start the Timer One Pulse and enable DMA transfer.
1857 (+) Stop the Timer One Pulse and disable DMA transfer.
1863 * @brief Initializes the TIM One Pulse Time Base according to the specified
1864 * parameters in the TIM_HandleTypeDef and create the associated handle.
1865 * @param htim: TIM OnePulse handle
1866 * @param OnePulseMode: Select the One pulse mode.
1867 * This parameter can be one of the following values:
1868 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1869 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
1870 * @retval HAL status
1872 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1874 /* Check the TIM handle allocation */
1880 /* Check the parameters */
1881 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1882 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1883 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1884 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1885 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1886 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
1888 if(htim->State == HAL_TIM_STATE_RESET)
1890 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1891 HAL_TIM_OnePulse_MspInit(htim);
1894 /* Set the TIM state */
1895 htim->State= HAL_TIM_STATE_BUSY;
1897 /* Configure the Time base in the One Pulse Mode */
1898 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1900 /* Reset the OPM Bit */
1901 htim->Instance->CR1 &= ~TIM_CR1_OPM;
1903 /* Configure the OPM Mode */
1904 htim->Instance->CR1 |= OnePulseMode;
1906 /* Initialize the TIM state*/
1907 htim->State= HAL_TIM_STATE_READY;
1913 * @brief DeInitializes the TIM One Pulse
1914 * @param htim: TIM One Pulse handle
1915 * @retval HAL status
1917 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
1919 /* Check the parameters */
1920 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1922 htim->State = HAL_TIM_STATE_BUSY;
1924 /* Disable the TIM Peripheral Clock */
1925 __HAL_TIM_DISABLE(htim);
1927 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
1928 HAL_TIM_OnePulse_MspDeInit(htim);
1930 /* Change TIM state */
1931 htim->State = HAL_TIM_STATE_RESET;
1940 * @brief Initializes the TIM One Pulse MSP.
1941 * @param htim : TIM handle
1944 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
1946 /* NOTE : This function Should not be modified, when the callback is needed,
1947 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
1952 * @brief DeInitializes TIM One Pulse MSP.
1953 * @param htim : TIM handle
1956 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
1958 /* NOTE : This function Should not be modified, when the callback is needed,
1959 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
1964 * @brief Starts the TIM One Pulse signal generation.
1965 * @param htim : TIM handle
1966 * @param OutputChannel : TIM Channels to be enabled.
1967 * This parameter is not used since both channels TIM_CHANNEL_1 and
1968 * TIM_CHANNEL_2 are automatically selected.
1969 * @retval HAL status
1971 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1973 /* Enable the Capture compare and the Input Capture channels
1974 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
1975 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
1976 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
1977 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
1979 No need to enable the counter, it's enabled automatically by hardware
1980 (the counter starts in response to a stimulus and generate a pulse */
1982 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
1983 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
1985 /* Return function status */
1990 * @brief Stops the TIM One Pulse signal generation.
1991 * @param htim : TIM handle
1992 * @param OutputChannel : TIM Channels to be disable.
1993 * This parameter can be one of the following values:
1994 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1995 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1996 * @retval HAL status
1998 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2000 /* Disable the Capture compare and the Input Capture channels
2001 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2002 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2003 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2004 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2006 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2007 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2009 /* Disable the Peripheral */
2010 __HAL_TIM_DISABLE(htim);
2012 /* Return function status */
2017 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2018 * @param htim : TIM handle
2019 * @param OutputChannel: TIM Channels to be enabled.
2020 * This parameter can be one of the following values:
2021 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2022 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2023 * @retval HAL status
2025 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2027 /* Enable the Capture compare and the Input Capture channels
2028 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2029 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2030 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2031 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2033 No need to enable the counter, it's enabled automatically by hardware
2034 (the counter starts in response to a stimulus and generate a pulse */
2036 /* Enable the TIM Capture/Compare 1 interrupt */
2037 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2039 /* Enable the TIM Capture/Compare 2 interrupt */
2040 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2042 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2043 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2045 /* Return function status */
2050 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2051 * @param htim : TIM handle
2052 * @param OutputChannel: TIM Channels to be enabled.
2053 * This parameter can be one of the following values:
2054 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2055 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2056 * @retval HAL status
2058 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2060 /* Disable the TIM Capture/Compare 1 interrupt */
2061 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2063 /* Disable the TIM Capture/Compare 2 interrupt */
2064 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2066 /* Disable the Capture compare and the Input Capture channels
2067 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2068 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2069 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2070 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2071 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2072 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2074 /* Disable the Peripheral */
2075 __HAL_TIM_DISABLE(htim);
2077 /* Return function status */
2085 /** @addtogroup TIM_Exported_Functions_Group6
2086 * @brief Time Encoder functions
2089 ==============================================================================
2090 ##### Timer Encoder functions #####
2091 ==============================================================================
2093 This section provides functions allowing to:
2094 (+) Initialize and configure the TIM Encoder.
2095 (+) De-initialize the TIM Encoder.
2096 (+) Start the Timer Encoder.
2097 (+) Stop the Timer Encoder.
2098 (+) Start the Timer Encoder and enable interrupt.
2099 (+) Stop the Timer Encoder and disable interrupt.
2100 (+) Start the Timer Encoder and enable DMA transfer.
2101 (+) Stop the Timer Encoder and disable DMA transfer.
2107 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2108 * @param htim: TIM Encoder Interface handle
2109 * @param sConfig: TIM Encoder Interface configuration structure
2110 * @retval HAL status
2112 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2114 uint32_t tmpsmcr = 0;
2115 uint32_t tmpccmr1 = 0;
2116 uint32_t tmpccer = 0;
2118 /* Check the TIM handle allocation */
2124 /* Check the parameters */
2125 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2126 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2127 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2128 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2129 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2130 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2131 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2132 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2133 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2134 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2135 assert_param(IS_TIM_PERIOD(htim->Init.Period));
2136 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
2138 if(htim->State == HAL_TIM_STATE_RESET)
2140 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2141 HAL_TIM_Encoder_MspInit(htim);
2144 /* Set the TIM state */
2145 htim->State= HAL_TIM_STATE_BUSY;
2147 /* Reset the SMS bits */
2148 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2150 /* Configure the Time base in the Encoder Mode */
2151 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2153 /* Get the TIMx SMCR register value */
2154 tmpsmcr = htim->Instance->SMCR;
2156 /* Get the TIMx CCMR1 register value */
2157 tmpccmr1 = htim->Instance->CCMR1;
2159 /* Get the TIMx CCER register value */
2160 tmpccer = htim->Instance->CCER;
2162 /* Set the encoder Mode */
2163 tmpsmcr |= sConfig->EncoderMode;
2165 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2166 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2167 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
2169 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2170 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2171 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2172 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
2173 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
2175 /* Set the TI1 and the TI2 Polarities */
2176 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2177 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2178 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
2180 /* Write to TIMx SMCR */
2181 htim->Instance->SMCR = tmpsmcr;
2183 /* Write to TIMx CCMR1 */
2184 htim->Instance->CCMR1 = tmpccmr1;
2186 /* Write to TIMx CCER */
2187 htim->Instance->CCER = tmpccer;
2189 /* Initialize the TIM state*/
2190 htim->State= HAL_TIM_STATE_READY;
2196 * @brief DeInitializes the TIM Encoder interface
2197 * @param htim: TIM Encoder handle
2198 * @retval HAL status
2200 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2202 /* Check the parameters */
2203 assert_param(IS_TIM_INSTANCE(htim->Instance));
2205 htim->State = HAL_TIM_STATE_BUSY;
2207 /* Disable the TIM Peripheral Clock */
2208 __HAL_TIM_DISABLE(htim);
2210 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2211 HAL_TIM_Encoder_MspDeInit(htim);
2213 /* Change TIM state */
2214 htim->State = HAL_TIM_STATE_RESET;
2224 * @brief Initializes the TIM Encoder Interface MSP.
2225 * @param htim : TIM handle
2228 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2230 /* NOTE : This function Should not be modified, when the callback is needed,
2231 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2237 * @brief DeInitializes TIM Encoder Interface MSP.
2238 * @param htim : TIM handle
2241 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2243 /* NOTE : This function Should not be modified, when the callback is needed,
2244 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2249 * @brief Starts the TIM Encoder Interface.
2250 * @param htim : TIM handle
2251 * @param Channel: TIM Channels to be enabled.
2252 * This parameter can be one of the following values:
2253 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2254 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2255 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2256 * @retval HAL status
2258 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2260 /* Check the parameters */
2261 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2263 /* Enable the encoder interface channels */
2268 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2273 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2278 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2279 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2283 /* Enable the Peripheral */
2284 __HAL_TIM_ENABLE(htim);
2286 /* Return function status */
2291 * @brief Stops the TIM Encoder Interface.
2292 * @param htim : TIM handle
2293 * @param Channel: TIM Channels to be disabled.
2294 * This parameter can be one of the following values:
2295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2297 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2298 * @retval HAL status
2300 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2302 /* Check the parameters */
2303 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2305 /* Disable the Input Capture channels 1 and 2
2306 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2311 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2316 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2321 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2322 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2326 /* Disable the Peripheral */
2327 __HAL_TIM_DISABLE(htim);
2329 /* Return function status */
2334 * @brief Starts the TIM Encoder Interface in interrupt mode.
2335 * @param htim : TIM handle
2336 * @param Channel: TIM Channels to be enabled.
2337 * This parameter can be one of the following values:
2338 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2339 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2340 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2341 * @retval HAL status
2343 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2345 /* Check the parameters */
2346 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2348 /* Enable the encoder interface channels */
2349 /* Enable the capture compare Interrupts 1 and/or 2 */
2354 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2355 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2360 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2361 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2366 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2367 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2368 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2369 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2374 /* Enable the Peripheral */
2375 __HAL_TIM_ENABLE(htim);
2377 /* Return function status */
2382 * @brief Stops the TIM Encoder Interface in interrupt mode.
2383 * @param htim : TIM handle
2384 * @param Channel: TIM Channels to be disabled.
2385 * This parameter can be one of the following values:
2386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2388 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2389 * @retval HAL status
2391 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2393 /* Check the parameters */
2394 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2396 /* Disable the Input Capture channels 1 and 2
2397 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2398 if(Channel == TIM_CHANNEL_1)
2400 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2402 /* Disable the capture compare Interrupts 1 */
2403 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2405 else if(Channel == TIM_CHANNEL_2)
2407 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2409 /* Disable the capture compare Interrupts 2 */
2410 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2417 /* Disable the capture compare Interrupts 1 and 2 */
2418 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2419 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2422 /* Disable the Peripheral */
2423 __HAL_TIM_DISABLE(htim);
2425 /* Change the htim state */
2426 htim->State = HAL_TIM_STATE_READY;
2428 /* Return function status */
2433 * @brief Starts the TIM Encoder Interface in DMA mode.
2434 * @param htim : TIM handle
2435 * @param Channel: TIM Channels to be enabled.
2436 * This parameter can be one of the following values:
2437 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2438 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2439 * @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected
2440 * @param pData1: The destination Buffer address for IC1.
2441 * @param pData2: The destination Buffer address for IC2.
2442 * @param Length: The length of data to be transferred from TIM peripheral to memory.
2443 * @retval HAL status
2445 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2447 /* Check the parameters */
2448 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2450 if((htim->State == HAL_TIM_STATE_BUSY))
2454 else if((htim->State == HAL_TIM_STATE_READY))
2456 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
2462 htim->State = HAL_TIM_STATE_BUSY;
2470 /* Set the DMA Period elapsed callback */
2471 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2473 /* Set the DMA error callback */
2474 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2476 /* Enable the DMA Stream */
2477 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2479 /* Enable the TIM Input Capture DMA request */
2480 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2482 /* Enable the Peripheral */
2483 __HAL_TIM_ENABLE(htim);
2485 /* Enable the Capture compare channel */
2486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2492 /* Set the DMA Period elapsed callback */
2493 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2495 /* Set the DMA error callback */
2496 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
2497 /* Enable the DMA Stream */
2498 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2500 /* Enable the TIM Input Capture DMA request */
2501 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2503 /* Enable the Peripheral */
2504 __HAL_TIM_ENABLE(htim);
2506 /* Enable the Capture compare channel */
2507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2511 case TIM_CHANNEL_ALL:
2513 /* Set the DMA Period elapsed callback */
2514 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2516 /* Set the DMA error callback */
2517 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2519 /* Enable the DMA Stream */
2520 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2522 /* Set the DMA Period elapsed callback */
2523 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2525 /* Set the DMA error callback */
2526 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2528 /* Enable the DMA Stream */
2529 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2531 /* Enable the Peripheral */
2532 __HAL_TIM_ENABLE(htim);
2534 /* Enable the Capture compare channel */
2535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2536 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2538 /* Enable the TIM Input Capture DMA request */
2539 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2540 /* Enable the TIM Input Capture DMA request */
2541 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2548 /* Return function status */
2553 * @brief Stops the TIM Encoder Interface in DMA mode.
2554 * @param htim : TIM handle
2555 * @param Channel: TIM Channels to be enabled.
2556 * This parameter can be one of the following values:
2557 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2558 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2559 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2560 * @retval HAL status
2562 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2564 /* Check the parameters */
2565 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2567 /* Disable the Input Capture channels 1 and 2
2568 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2569 if(Channel == TIM_CHANNEL_1)
2571 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2573 /* Disable the capture compare DMA Request 1 */
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2576 else if(Channel == TIM_CHANNEL_2)
2578 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2580 /* Disable the capture compare DMA Request 2 */
2581 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2585 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2586 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2588 /* Disable the capture compare DMA Request 1 and 2 */
2589 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2590 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2593 /* Disable the Peripheral */
2594 __HAL_TIM_DISABLE(htim);
2596 /* Change the htim state */
2597 htim->State = HAL_TIM_STATE_READY;
2599 /* Return function status */
2607 /** @addtogroup TIM_Exported_Functions_Group7
2608 * @brief IRQ handler management
2611 ==============================================================================
2612 ##### IRQ handler management #####
2613 ==============================================================================
2615 This section provides Timer IRQ handler function.
2621 * @brief This function handles TIM interrupts requests.
2622 * @param htim: TIM handle
2625 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2627 /* Capture compare 1 event */
2628 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2630 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
2633 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2634 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2636 /* Input capture event */
2637 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
2639 HAL_TIM_IC_CaptureCallback(htim);
2641 /* Output compare event */
2644 HAL_TIM_OC_DelayElapsedCallback(htim);
2645 HAL_TIM_PWM_PulseFinishedCallback(htim);
2647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2651 /* Capture compare 2 event */
2652 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2654 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
2656 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2657 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2658 /* Input capture event */
2659 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
2661 HAL_TIM_IC_CaptureCallback(htim);
2663 /* Output compare event */
2666 HAL_TIM_OC_DelayElapsedCallback(htim);
2667 HAL_TIM_PWM_PulseFinishedCallback(htim);
2669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2672 /* Capture compare 3 event */
2673 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2675 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
2677 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2678 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2679 /* Input capture event */
2680 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
2682 HAL_TIM_IC_CaptureCallback(htim);
2684 /* Output compare event */
2687 HAL_TIM_OC_DelayElapsedCallback(htim);
2688 HAL_TIM_PWM_PulseFinishedCallback(htim);
2690 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2693 /* Capture compare 4 event */
2694 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2696 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
2698 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2699 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2700 /* Input capture event */
2701 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
2703 HAL_TIM_IC_CaptureCallback(htim);
2705 /* Output compare event */
2708 HAL_TIM_OC_DelayElapsedCallback(htim);
2709 HAL_TIM_PWM_PulseFinishedCallback(htim);
2711 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2714 /* TIM Update event */
2715 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2717 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
2719 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2720 HAL_TIM_PeriodElapsedCallback(htim);
2723 /* TIM Trigger detection event */
2724 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2726 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
2728 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2729 HAL_TIM_TriggerCallback(htim);
2738 /** @addtogroup TIM_Exported_Functions_Group8
2739 * @brief Peripheral Control functions
2742 ==============================================================================
2743 ##### Peripheral Control functions #####
2744 ==============================================================================
2746 This section provides functions allowing to:
2747 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2748 (+) Configure External Clock source.
2749 (+) Configure Master and the Slave synchronization.
2750 (+) Configure the DMA Burst Mode.
2756 * @brief Initializes the TIM Output Compare Channels according to the specified
2757 * parameters in the TIM_OC_InitTypeDef.
2758 * @param htim : TIM handle
2759 * @param sConfig: TIM Output Compare configuration structure
2760 * @param Channel: TIM Channels to be enabled.
2761 * This parameter can be one of the following values:
2762 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2763 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2764 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2765 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2766 * @retval HAL status
2768 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2770 /* Check the parameters */
2771 assert_param(IS_TIM_CHANNELS(Channel));
2772 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2773 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2775 /* Check input state */
2778 htim->State = HAL_TIM_STATE_BUSY;
2784 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2785 /* Configure the TIM Channel 1 in Output Compare */
2786 TIM_OC1_SetConfig(htim->Instance, sConfig);
2792 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2793 /* Configure the TIM Channel 2 in Output Compare */
2794 TIM_OC2_SetConfig(htim->Instance, sConfig);
2800 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2801 /* Configure the TIM Channel 3 in Output Compare */
2802 TIM_OC3_SetConfig(htim->Instance, sConfig);
2808 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2809 /* Configure the TIM Channel 4 in Output Compare */
2810 TIM_OC4_SetConfig(htim->Instance, sConfig);
2817 htim->State = HAL_TIM_STATE_READY;
2825 * @brief Initializes the TIM Input Capture Channels according to the specified
2826 * parameters in the TIM_IC_InitTypeDef.
2827 * @param htim : TIM handle
2828 * @param sConfig: TIM Input Capture configuration structure
2829 * @param Channel: TIM Channels to be enabled.
2830 * This parameter can be one of the following values:
2831 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2832 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2833 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2834 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2835 * @retval HAL status
2837 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
2839 /* Check the parameters */
2840 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2841 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
2842 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
2843 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
2844 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
2848 htim->State = HAL_TIM_STATE_BUSY;
2850 if (Channel == TIM_CHANNEL_1)
2852 /* TI1 Configuration */
2853 TIM_TI1_SetConfig(htim->Instance,
2854 sConfig->ICPolarity,
2855 sConfig->ICSelection,
2858 /* Reset the IC1PSC Bits */
2859 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
2861 /* Set the IC1PSC value */
2862 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
2864 else if (Channel == TIM_CHANNEL_2)
2866 /* TI2 Configuration */
2867 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2869 TIM_TI2_SetConfig(htim->Instance,
2870 sConfig->ICPolarity,
2871 sConfig->ICSelection,
2874 /* Reset the IC2PSC Bits */
2875 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
2877 /* Set the IC2PSC value */
2878 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
2880 else if (Channel == TIM_CHANNEL_3)
2882 /* TI3 Configuration */
2883 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2885 TIM_TI3_SetConfig(htim->Instance,
2886 sConfig->ICPolarity,
2887 sConfig->ICSelection,
2890 /* Reset the IC3PSC Bits */
2891 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
2893 /* Set the IC3PSC value */
2894 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
2898 /* TI4 Configuration */
2899 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2901 TIM_TI4_SetConfig(htim->Instance,
2902 sConfig->ICPolarity,
2903 sConfig->ICSelection,
2906 /* Reset the IC4PSC Bits */
2907 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
2909 /* Set the IC4PSC value */
2910 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
2913 htim->State = HAL_TIM_STATE_READY;
2921 * @brief Initializes the TIM PWM channels according to the specified
2922 * parameters in the TIM_OC_InitTypeDef.
2923 * @param htim : TIM handle
2924 * @param sConfig: TIM PWM configuration structure
2925 * @param Channel: TIM Channels to be enabled.
2926 * This parameter can be one of the following values:
2927 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2928 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2929 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2930 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2931 * @retval HAL status
2933 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2937 /* Check the parameters */
2938 assert_param(IS_TIM_CHANNELS(Channel));
2939 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
2940 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2941 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
2943 htim->State = HAL_TIM_STATE_BUSY;
2949 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2950 /* Configure the Channel 1 in PWM mode */
2951 TIM_OC1_SetConfig(htim->Instance, sConfig);
2953 /* Set the Preload enable bit for channel1 */
2954 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
2956 /* Configure the Output Fast mode */
2957 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
2958 htim->Instance->CCMR1 |= sConfig->OCFastMode;
2964 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2965 /* Configure the Channel 2 in PWM mode */
2966 TIM_OC2_SetConfig(htim->Instance, sConfig);
2968 /* Set the Preload enable bit for channel2 */
2969 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
2971 /* Configure the Output Fast mode */
2972 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
2973 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
2979 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2980 /* Configure the Channel 3 in PWM mode */
2981 TIM_OC3_SetConfig(htim->Instance, sConfig);
2983 /* Set the Preload enable bit for channel3 */
2984 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
2986 /* Configure the Output Fast mode */
2987 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
2988 htim->Instance->CCMR2 |= sConfig->OCFastMode;
2994 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2995 /* Configure the Channel 4 in PWM mode */
2996 TIM_OC4_SetConfig(htim->Instance, sConfig);
2998 /* Set the Preload enable bit for channel4 */
2999 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3001 /* Configure the Output Fast mode */
3002 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3003 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
3011 htim->State = HAL_TIM_STATE_READY;
3019 * @brief Initializes the TIM One Pulse Channels according to the specified
3020 * parameters in the TIM_OnePulse_InitTypeDef.
3021 * @param htim : TIM handle
3022 * @param sConfig: TIM One Pulse configuration structure
3023 * @param OutputChannel: TIM Channels to be enabled.
3024 * This parameter can be one of the following values:
3025 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3026 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3027 * @param InputChannel: TIM Channels to be enabled.
3028 * This parameter can be one of the following values:
3029 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3030 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3031 * @retval HAL status
3033 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3035 TIM_OC_InitTypeDef temp1;
3037 /* Check the parameters */
3038 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3039 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3041 if(OutputChannel != InputChannel)
3045 htim->State = HAL_TIM_STATE_BUSY;
3047 /* Extract the Ouput compare configuration from sConfig structure */
3048 temp1.OCMode = sConfig->OCMode;
3049 temp1.Pulse = sConfig->Pulse;
3050 temp1.OCPolarity = sConfig->OCPolarity;
3052 switch (OutputChannel)
3056 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3058 TIM_OC1_SetConfig(htim->Instance, &temp1);
3063 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3065 TIM_OC2_SetConfig(htim->Instance, &temp1);
3071 switch (InputChannel)
3075 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3077 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3078 sConfig->ICSelection, sConfig->ICFilter);
3080 /* Reset the IC1PSC Bits */
3081 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3083 /* Select the Trigger source */
3084 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3085 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3087 /* Select the Slave Mode */
3088 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3089 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3094 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3096 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3097 sConfig->ICSelection, sConfig->ICFilter);
3099 /* Reset the IC2PSC Bits */
3100 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3102 /* Select the Trigger source */
3103 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3104 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3106 /* Select the Slave Mode */
3107 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3108 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3116 htim->State = HAL_TIM_STATE_READY;
3129 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3130 * @param htim : TIM handle
3131 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
3132 * This parameters can be on of the following values:
3133 * @arg TIM_DMABASE_CR1
3134 * @arg TIM_DMABASE_CR2
3135 * @arg TIM_DMABASE_SMCR
3136 * @arg TIM_DMABASE_DIER
3137 * @arg TIM_DMABASE_SR
3138 * @arg TIM_DMABASE_EGR
3139 * @arg TIM_DMABASE_CCMR1
3140 * @arg TIM_DMABASE_CCMR2
3141 * @arg TIM_DMABASE_CCER
3142 * @arg TIM_DMABASE_CNT
3143 * @arg TIM_DMABASE_PSC
3144 * @arg TIM_DMABASE_ARR
3145 * @arg TIM_DMABASE_CCR1
3146 * @arg TIM_DMABASE_CCR2
3147 * @arg TIM_DMABASE_CCR3
3148 * @arg TIM_DMABASE_CCR4
3149 * @arg TIM_DMABASE_DCR
3150 * @param BurstRequestSrc: TIM DMA Request sources.
3151 * This parameters can be on of the following values:
3152 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3153 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3154 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3155 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3156 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3157 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3158 * @param BurstBuffer: The Buffer address.
3159 * @param BurstLength: DMA Burst length. This parameter can be one value
3160 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
3161 * @retval HAL status
3163 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3164 uint32_t* BurstBuffer, uint32_t BurstLength)
3166 /* Check the parameters */
3167 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3168 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3169 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3170 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3172 if((htim->State == HAL_TIM_STATE_BUSY))
3176 else if((htim->State == HAL_TIM_STATE_READY))
3178 if((BurstBuffer == 0 ) && (BurstLength > 0))
3184 htim->State = HAL_TIM_STATE_BUSY;
3187 switch(BurstRequestSrc)
3189 case TIM_DMA_UPDATE:
3191 /* Set the DMA Period elapsed callback */
3192 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3194 /* Set the DMA error callback */
3195 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3197 /* Enable the DMA Stream */
3198 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3203 /* Set the DMA Period elapsed callback */
3204 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3206 /* Set the DMA error callback */
3207 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3209 /* Enable the DMA Stream */
3210 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3215 /* Set the DMA Period elapsed callback */
3216 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3218 /* Set the DMA error callback */
3219 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3221 /* Enable the DMA Stream */
3222 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3227 /* Set the DMA Period elapsed callback */
3228 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3230 /* Set the DMA error callback */
3231 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3233 /* Enable the DMA Stream */
3234 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3239 /* Set the DMA Period elapsed callback */
3240 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
3242 /* Set the DMA error callback */
3243 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3245 /* Enable the DMA Stream */
3246 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3249 case TIM_DMA_TRIGGER:
3251 /* Set the DMA Period elapsed callback */
3252 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3254 /* Set the DMA error callback */
3255 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3257 /* Enable the DMA Stream */
3258 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3264 /* configure the DMA Burst Mode */
3265 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3267 /* Enable the TIM DMA Request */
3268 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3270 htim->State = HAL_TIM_STATE_READY;
3272 /* Return function status */
3277 * @brief Stops the TIM DMA Burst mode
3278 * @param htim : TIM handle
3279 * @param BurstRequestSrc: TIM DMA Request sources to disable
3280 * @retval HAL status
3282 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3284 /* Check the parameters */
3285 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3287 /* Abort the DMA transfer (at least disable the DMA channel) */
3288 switch(BurstRequestSrc)
3290 case TIM_DMA_UPDATE:
3292 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3297 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3302 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3307 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3312 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3315 case TIM_DMA_TRIGGER:
3317 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3323 /* Disable the TIM Update DMA request */
3324 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3326 /* Return function status */
3331 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3332 * @param htim : TIM handle
3333 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
3334 * This parameters can be on of the following values:
3335 * @arg TIM_DMABASE_CR1
3336 * @arg TIM_DMABASE_CR2
3337 * @arg TIM_DMABASE_SMCR
3338 * @arg TIM_DMABASE_DIER
3339 * @arg TIM_DMABASE_SR
3340 * @arg TIM_DMABASE_EGR
3341 * @arg TIM_DMABASE_CCMR1
3342 * @arg TIM_DMABASE_CCMR2
3343 * @arg TIM_DMABASE_CCER
3344 * @arg TIM_DMABASE_CNT
3345 * @arg TIM_DMABASE_PSC
3346 * @arg TIM_DMABASE_ARR
3347 * @arg TIM_DMABASE_CCR1
3348 * @arg TIM_DMABASE_CCR2
3349 * @arg TIM_DMABASE_CCR3
3350 * @arg TIM_DMABASE_CCR4
3351 * @arg TIM_DMABASE_DCR
3352 * @param BurstRequestSrc: TIM DMA Request sources.
3353 * This parameters can be on of the following values:
3354 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3355 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3356 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3357 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3358 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3359 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3360 * @param BurstBuffer: The Buffer address.
3361 * @param BurstLength: DMA Burst length. This parameter can be one value
3362 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
3363 * @retval HAL status
3365 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3366 uint32_t *BurstBuffer, uint32_t BurstLength)
3368 /* Check the parameters */
3369 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3370 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3371 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3372 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3374 if((htim->State == HAL_TIM_STATE_BUSY))
3378 else if((htim->State == HAL_TIM_STATE_READY))
3380 if((BurstBuffer == 0 ) && (BurstLength > 0))
3386 htim->State = HAL_TIM_STATE_BUSY;
3389 switch(BurstRequestSrc)
3391 case TIM_DMA_UPDATE:
3393 /* Set the DMA Period elapsed callback */
3394 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3396 /* Set the DMA error callback */
3397 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3399 /* Enable the DMA Stream */
3400 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3405 /* Set the DMA Period elapsed callback */
3406 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3408 /* Set the DMA error callback */
3409 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3411 /* Enable the DMA Stream */
3412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3417 /* Set the DMA Period elapsed callback */
3418 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3420 /* Set the DMA error callback */
3421 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3423 /* Enable the DMA Stream */
3424 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3429 /* Set the DMA Period elapsed callback */
3430 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
3432 /* Set the DMA error callback */
3433 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3435 /* Enable the DMA Stream */
3436 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3441 /* Set the DMA Period elapsed callback */
3442 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
3444 /* Set the DMA error callback */
3445 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3447 /* Enable the DMA Stream */
3448 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3451 case TIM_DMA_TRIGGER:
3453 /* Set the DMA Period elapsed callback */
3454 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3456 /* Set the DMA error callback */
3457 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3459 /* Enable the DMA Stream */
3460 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3467 /* configure the DMA Burst Mode */
3468 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3470 /* Enable the TIM DMA Request */
3471 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3473 htim->State = HAL_TIM_STATE_READY;
3475 /* Return function status */
3480 * @brief Stop the DMA burst reading
3481 * @param htim : TIM handle
3482 * @param BurstRequestSrc: TIM DMA Request sources to disable.
3483 * @retval HAL status
3485 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3487 /* Check the parameters */
3488 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3490 /* Abort the DMA transfer (at least disable the DMA channel) */
3491 switch(BurstRequestSrc)
3493 case TIM_DMA_UPDATE:
3495 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3500 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3505 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3510 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3515 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3518 case TIM_DMA_TRIGGER:
3520 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3527 /* Disable the TIM Update DMA request */
3528 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3530 /* Return function status */
3535 * @brief Generate a software event
3536 * @param htim : TIM handle
3537 * @param EventSource: specifies the event source.
3538 * This parameter can be one of the following values:
3539 * @arg TIM_EventSource_Update: Timer update Event source
3540 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3541 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
3542 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
3543 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
3544 * @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source
3545 * @note TIM6 can only generate an update event.
3546 * @retval HAL status
3549 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3551 /* Check the parameters */
3552 assert_param(IS_TIM_INSTANCE(htim->Instance));
3553 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3555 /* Process Locked */
3558 /* Change the TIM state */
3559 htim->State = HAL_TIM_STATE_BUSY;
3561 /* Set the event sources */
3562 htim->Instance->EGR = EventSource;
3564 /* Change the TIM state */
3565 htim->State = HAL_TIM_STATE_READY;
3569 /* Return function status */
3574 * @brief Configures the OCRef clear feature
3575 * @param htim : TIM handle
3576 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
3577 * contains the OCREF clear feature and parameters for the TIM peripheral.
3578 * @param Channel: specifies the TIM Channel.
3579 * This parameter can be one of the following values:
3580 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3581 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3582 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3583 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3584 * @retval HAL status
3586 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3588 /* Check the parameters */
3589 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3590 assert_param(IS_TIM_CHANNELS(Channel));
3591 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3592 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3593 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3594 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3596 /* Process Locked */
3599 htim->State = HAL_TIM_STATE_BUSY;
3601 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
3603 TIM_ETR_SetConfig(htim->Instance,
3604 sClearInputConfig->ClearInputPrescaler,
3605 sClearInputConfig->ClearInputPolarity,
3606 sClearInputConfig->ClearInputFilter);
3613 if(sClearInputConfig->ClearInputState != RESET)
3615 /* Enable the Ocref clear feature for Channel 1 */
3616 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3620 /* Disable the Ocref clear feature for Channel 1 */
3621 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3627 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3628 if(sClearInputConfig->ClearInputState != RESET)
3630 /* Enable the Ocref clear feature for Channel 2 */
3631 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3635 /* Disable the Ocref clear feature for Channel 2 */
3636 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3642 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3643 if(sClearInputConfig->ClearInputState != RESET)
3645 /* Enable the Ocref clear feature for Channel 3 */
3646 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3650 /* Disable the Ocref clear feature for Channel 3 */
3651 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3657 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3658 if(sClearInputConfig->ClearInputState != RESET)
3660 /* Enable the Ocref clear feature for Channel 4 */
3661 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3665 /* Disable the Ocref clear feature for Channel 4 */
3666 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3674 htim->State = HAL_TIM_STATE_READY;
3682 * @brief Configures the clock source to be used
3683 * @param htim : TIM handle
3684 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
3685 * contains the clock source information for the TIM peripheral.
3686 * @retval HAL status
3688 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3690 uint32_t tmpsmcr = 0;
3692 /* Process Locked */
3695 htim->State = HAL_TIM_STATE_BUSY;
3697 /* Check the parameters */
3698 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3699 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3700 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3701 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3703 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3704 tmpsmcr = htim->Instance->SMCR;
3705 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3706 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3707 htim->Instance->SMCR = tmpsmcr;
3709 switch (sClockSourceConfig->ClockSource)
3711 case TIM_CLOCKSOURCE_INTERNAL:
3713 assert_param(IS_TIM_INSTANCE(htim->Instance));
3714 /* Disable slave mode to clock the prescaler directly with the internal clock */
3715 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3719 case TIM_CLOCKSOURCE_ETRMODE1:
3721 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
3722 /* Configure the ETR Clock source */
3723 TIM_ETR_SetConfig(htim->Instance,
3724 sClockSourceConfig->ClockPrescaler,
3725 sClockSourceConfig->ClockPolarity,
3726 sClockSourceConfig->ClockFilter);
3727 /* Get the TIMx SMCR register value */
3728 tmpsmcr = htim->Instance->SMCR;
3729 /* Reset the SMS and TS Bits */
3730 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3731 /* Select the External clock mode1 and the ETRF trigger */
3732 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3733 /* Write to TIMx SMCR */
3734 htim->Instance->SMCR = tmpsmcr;
3738 case TIM_CLOCKSOURCE_ETRMODE2:
3740 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
3741 /* Configure the ETR Clock source */
3742 TIM_ETR_SetConfig(htim->Instance,
3743 sClockSourceConfig->ClockPrescaler,
3744 sClockSourceConfig->ClockPolarity,
3745 sClockSourceConfig->ClockFilter);
3746 /* Enable the External clock mode2 */
3747 htim->Instance->SMCR |= TIM_SMCR_ECE;
3751 case TIM_CLOCKSOURCE_TI1:
3753 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3754 TIM_TI1_ConfigInputStage(htim->Instance,
3755 sClockSourceConfig->ClockPolarity,
3756 sClockSourceConfig->ClockFilter);
3757 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
3760 case TIM_CLOCKSOURCE_TI2:
3762 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3763 TIM_TI2_ConfigInputStage(htim->Instance,
3764 sClockSourceConfig->ClockPolarity,
3765 sClockSourceConfig->ClockFilter);
3766 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
3769 case TIM_CLOCKSOURCE_TI1ED:
3771 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3772 TIM_TI1_ConfigInputStage(htim->Instance,
3773 sClockSourceConfig->ClockPolarity,
3774 sClockSourceConfig->ClockFilter);
3775 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
3778 case TIM_CLOCKSOURCE_ITR0:
3780 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3781 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
3784 case TIM_CLOCKSOURCE_ITR1:
3786 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3787 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
3790 case TIM_CLOCKSOURCE_ITR2:
3792 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3793 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
3796 case TIM_CLOCKSOURCE_ITR3:
3798 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3799 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
3806 htim->State = HAL_TIM_STATE_READY;
3814 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
3815 * or a XOR combination between CH1_input, CH2_input & CH3_input
3816 * @param htim : TIM handle
3817 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
3818 * output of a XOR gate.
3819 * This parameter can be one of the following values:
3820 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
3821 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
3822 * pins are connected to the TI1 input (XOR combination)
3823 * @retval HAL status
3825 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
3827 uint32_t tmpcr2 = 0;
3829 /* Check the parameters */
3830 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
3831 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
3833 /* Get the TIMx CR2 register value */
3834 tmpcr2 = htim->Instance->CR2;
3836 /* Reset the TI1 selection */
3837 tmpcr2 &= ~TIM_CR2_TI1S;
3839 /* Set the the TI1 selection */
3840 tmpcr2 |= TI1_Selection;
3842 /* Write to TIMxCR2 */
3843 htim->Instance->CR2 = tmpcr2;
3849 * @brief Configures the TIM in Slave mode
3850 * @param htim : TIM handle
3851 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
3852 * contains the selected trigger (internal trigger input, filtered
3853 * timer input or external trigger input) and the ) and the Slave
3854 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
3855 * @retval HAL status
3857 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
3859 /* Check the parameters */
3860 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3861 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
3862 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
3866 htim->State = HAL_TIM_STATE_BUSY;
3868 /* Configuration in slave mode */
3869 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
3871 /* Disable Trigger Interrupt */
3872 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
3874 /* Disable Trigger DMA request */
3875 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
3877 /* Set the new state */
3878 htim->State = HAL_TIM_STATE_READY;
3886 * @brief Configures the TIM in Slave mode in interrupt mode
3887 * @param htim : TIM handle.
3888 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
3889 * contains the selected trigger (internal trigger input, filtered
3890 * timer input or external trigger input) and the ) and the Slave
3891 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
3892 * @retval HAL status
3894 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
3895 TIM_SlaveConfigTypeDef * sSlaveConfig)
3897 /* Check the parameters */
3898 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3899 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
3900 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
3904 htim->State = HAL_TIM_STATE_BUSY;
3906 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
3908 /* Enable Trigger Interrupt */
3909 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
3911 /* Disable Trigger DMA request */
3912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
3914 htim->State = HAL_TIM_STATE_READY;
3922 * @brief Read the captured value from Capture Compare unit
3923 * @param htim : TIM handle
3924 * @param Channel: TIM Channels to be enabled.
3925 * This parameter can be one of the following values:
3926 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3927 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3928 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3929 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3930 * @retval Captured value
3932 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
3934 uint32_t tmpreg = 0;
3942 /* Check the parameters */
3943 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3945 /* Return the capture 1 value */
3946 tmpreg = htim->Instance->CCR1;
3952 /* Check the parameters */
3953 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3955 /* Return the capture 2 value */
3956 tmpreg = htim->Instance->CCR2;
3963 /* Check the parameters */
3964 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3966 /* Return the capture 3 value */
3967 tmpreg = htim->Instance->CCR3;
3974 /* Check the parameters */
3975 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3977 /* Return the capture 4 value */
3978 tmpreg = htim->Instance->CCR4;
3995 /** @addtogroup TIM_Exported_Functions_Group9
3996 * @brief TIM Callbacks functions
3999 ==============================================================================
4000 ##### TIM Callbacks functions #####
4001 ==============================================================================
4003 This section provides TIM callback functions:
4004 (+) Timer Period elapsed callback
4005 (+) Timer Output Compare callback
4006 (+) Timer Input capture callback
4007 (+) Timer Trigger callback
4008 (+) Timer Error callback
4015 * @brief Period elapsed callback in non blocking mode
4016 * @param htim : TIM handle
4019 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4021 /* NOTE : This function Should not be modified, when the callback is needed,
4022 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4027 * @brief Output Compare callback in non blocking mode
4028 * @param htim : TIM handle
4031 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4033 /* NOTE : This function Should not be modified, when the callback is needed,
4034 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4038 * @brief Input Capture callback in non blocking mode
4039 * @param htim: TIM IC handle
4042 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4044 /* NOTE : This function Should not be modified, when the callback is needed,
4045 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4050 * @brief PWM Pulse finished callback in non blocking mode
4051 * @param htim : TIM handle
4054 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4056 /* NOTE : This function Should not be modified, when the callback is needed,
4057 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4062 * @brief Hall Trigger detection callback in non blocking mode
4063 * @param htim : TIM handle
4066 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4068 /* NOTE : This function Should not be modified, when the callback is needed,
4069 the HAL_TIM_TriggerCallback could be implemented in the user file
4074 * @brief Timer error callback in non blocking mode
4075 * @param htim : TIM handle
4078 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4080 /* NOTE : This function Should not be modified, when the callback is needed,
4081 the HAL_TIM_ErrorCallback could be implemented in the user file
4089 /** @addtogroup TIM_Exported_Functions_Group10
4090 * @brief Peripheral State functions
4093 ==============================================================================
4094 ##### Peripheral State functions #####
4095 ==============================================================================
4097 This subsection permits to get in run-time the status of the peripheral
4105 * @brief Return the TIM Base state
4106 * @param htim : TIM handle
4109 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4115 * @brief Return the TIM OC state
4116 * @param htim: TIM Ouput Compare handle
4119 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4125 * @brief Return the TIM PWM state
4126 * @param htim : TIM handle
4129 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4135 * @brief Return the TIM Input Capture state
4136 * @param htim : TIM handle
4139 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4145 * @brief Return the TIM One Pulse Mode state
4146 * @param htim: TIM OPM handle
4149 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4155 * @brief Return the TIM Encoder Mode state
4156 * @param htim : TIM handle
4159 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4167 * @brief TIM DMA error callback
4168 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4169 * the configuration information for the specified DMA module.
4172 void TIM_DMAError(DMA_HandleTypeDef *hdma)
4174 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4176 htim->State= HAL_TIM_STATE_READY;
4178 HAL_TIM_ErrorCallback(htim);
4182 * @brief TIM DMA Delay Pulse complete callback.
4183 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
4184 * the configuration information for the specified DMA module.
4187 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4189 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4191 htim->State= HAL_TIM_STATE_READY;
4193 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4195 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4197 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4199 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4201 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4203 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4205 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4207 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4209 HAL_TIM_PWM_PulseFinishedCallback(htim);
4211 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4214 * @brief TIM DMA Capture complete callback.
4215 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
4216 * the configuration information for the specified DMA module.
4219 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4221 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4223 htim->State= HAL_TIM_STATE_READY;
4225 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4227 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4229 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4231 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4233 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4235 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4237 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4239 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4242 HAL_TIM_IC_CaptureCallback(htim);
4244 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4255 /*************************************************************/
4256 /* Private functions */
4257 /*************************************************************/
4259 /** @defgroup TIM_Private_Functions TIM Private Functions
4263 * @brief TIM DMA Period Elapse complete callback.
4264 * @param hdma : pointer to DMA handle.
4267 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4269 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4271 htim->State= HAL_TIM_STATE_READY;
4273 HAL_TIM_PeriodElapsedCallback(htim);
4278 * @brief TIM DMA Trigger callback.
4279 * @param hdma : pointer to DMA handle.
4282 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4284 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4286 htim->State= HAL_TIM_STATE_READY;
4288 HAL_TIM_TriggerCallback(htim);
4292 * @brief Time Base configuration
4293 * @param TIMx : TIM peripheral
4294 * @param Structure : TIM Base configuration structure
4297 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4299 uint32_t tmpcr1 = 0;
4302 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4303 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
4305 /* Select the Counter Mode */
4306 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4307 tmpcr1 |= Structure->CounterMode;
4310 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
4312 /* Set the clock division */
4313 tmpcr1 &= ~TIM_CR1_CKD;
4314 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4319 /* Set the Autoreload value */
4320 TIMx->ARR = (uint32_t)Structure->Period ;
4322 /* Set the Prescaler value */
4323 TIMx->PSC = (uint32_t)Structure->Prescaler;
4325 /* Generate an update event to reload the Prescaler value immediatly */
4326 TIMx->EGR = TIM_EGR_UG;
4330 * @brief Time Ouput Compare 1 configuration
4331 * @param TIMx to select the TIM peripheral
4332 * @param OC_Config: The ouput configuration structure
4335 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4337 uint32_t tmpccmrx = 0;
4338 uint32_t tmpccer = 0;
4339 uint32_t tmpcr2 = 0;
4341 /* Disable the Channel 1: Reset the CC1E Bit */
4342 TIMx->CCER &= ~TIM_CCER_CC1E;
4344 /* Get the TIMx CCER register value */
4345 tmpccer = TIMx->CCER;
4346 /* Get the TIMx CR2 register value */
4349 /* Get the TIMx CCMR1 register value */
4350 tmpccmrx = TIMx->CCMR1;
4352 /* Reset the Output Compare Mode Bits */
4353 tmpccmrx &= ~TIM_CCMR1_OC1M;
4354 tmpccmrx &= ~TIM_CCMR1_CC1S;
4355 /* Select the Output Compare Mode */
4356 tmpccmrx |= OC_Config->OCMode;
4358 /* Reset the Output Polarity level */
4359 tmpccer &= ~TIM_CCER_CC1P;
4360 /* Set the Output Compare Polarity */
4361 tmpccer |= OC_Config->OCPolarity;
4363 /* Write to TIMx CR2 */
4366 /* Write to TIMx CCMR1 */
4367 TIMx->CCMR1 = tmpccmrx;
4369 /* Set the Capture Compare Register value */
4370 TIMx->CCR1 = OC_Config->Pulse;
4372 /* Write to TIMx CCER */
4373 TIMx->CCER = tmpccer;
4377 * @brief Time Ouput Compare 2 configuration
4378 * @param TIMx to select the TIM peripheral
4379 * @param OC_Config: The ouput configuration structure
4382 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4384 uint32_t tmpccmrx = 0;
4385 uint32_t tmpccer = 0;
4386 uint32_t tmpcr2 = 0;
4388 /* Disable the Channel 2: Reset the CC2E Bit */
4389 TIMx->CCER &= ~TIM_CCER_CC2E;
4391 /* Get the TIMx CCER register value */
4392 tmpccer = TIMx->CCER;
4393 /* Get the TIMx CR2 register value */
4396 /* Get the TIMx CCMR1 register value */
4397 tmpccmrx = TIMx->CCMR1;
4399 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4400 tmpccmrx &= ~TIM_CCMR1_OC2M;
4401 tmpccmrx &= ~TIM_CCMR1_CC2S;
4403 /* Select the Output Compare Mode */
4404 tmpccmrx |= (OC_Config->OCMode << 8);
4406 /* Reset the Output Polarity level */
4407 tmpccer &= ~TIM_CCER_CC2P;
4408 /* Set the Output Compare Polarity */
4409 tmpccer |= (OC_Config->OCPolarity << 4);
4411 /* Write to TIMx CR2 */
4414 /* Write to TIMx CCMR1 */
4415 TIMx->CCMR1 = tmpccmrx;
4417 /* Set the Capture Compare Register value */
4418 TIMx->CCR2 = OC_Config->Pulse;
4420 /* Write to TIMx CCER */
4421 TIMx->CCER = tmpccer;
4425 * @brief Time Ouput Compare 3 configuration
4426 * @param TIMx to select the TIM peripheral
4427 * @param OC_Config: The ouput configuration structure
4430 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4432 uint32_t tmpccmrx = 0;
4433 uint32_t tmpccer = 0;
4434 uint32_t tmpcr2 = 0;
4436 /* Disable the Channel 3: Reset the CC2E Bit */
4437 TIMx->CCER &= ~TIM_CCER_CC3E;
4439 /* Get the TIMx CCER register value */
4440 tmpccer = TIMx->CCER;
4441 /* Get the TIMx CR2 register value */
4444 /* Get the TIMx CCMR2 register value */
4445 tmpccmrx = TIMx->CCMR2;
4447 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4448 tmpccmrx &= ~TIM_CCMR2_OC3M;
4449 tmpccmrx &= ~TIM_CCMR2_CC3S;
4450 /* Select the Output Compare Mode */
4451 tmpccmrx |= OC_Config->OCMode;
4453 /* Reset the Output Polarity level */
4454 tmpccer &= ~TIM_CCER_CC3P;
4455 /* Set the Output Compare Polarity */
4456 tmpccer |= (OC_Config->OCPolarity << 8);
4458 /* Write to TIMx CR2 */
4461 /* Write to TIMx CCMR2 */
4462 TIMx->CCMR2 = tmpccmrx;
4464 /* Set the Capture Compare Register value */
4465 TIMx->CCR3 = OC_Config->Pulse;
4467 /* Write to TIMx CCER */
4468 TIMx->CCER = tmpccer;
4472 * @brief Time Ouput Compare 4 configuration
4473 * @param TIMx to select the TIM peripheral
4474 * @param OC_Config: The ouput configuration structure
4477 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4479 uint32_t tmpccmrx = 0;
4480 uint32_t tmpccer = 0;
4481 uint32_t tmpcr2 = 0;
4483 /* Disable the Channel 4: Reset the CC4E Bit */
4484 TIMx->CCER &= ~TIM_CCER_CC4E;
4486 /* Get the TIMx CCER register value */
4487 tmpccer = TIMx->CCER;
4488 /* Get the TIMx CR2 register value */
4491 /* Get the TIMx CCMR2 register value */
4492 tmpccmrx = TIMx->CCMR2;
4494 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4495 tmpccmrx &= ~TIM_CCMR2_OC4M;
4496 tmpccmrx &= ~TIM_CCMR2_CC4S;
4498 /* Select the Output Compare Mode */
4499 tmpccmrx |= (OC_Config->OCMode << 8);
4501 /* Reset the Output Polarity level */
4502 tmpccer &= ~TIM_CCER_CC4P;
4503 /* Set the Output Compare Polarity */
4504 tmpccer |= (OC_Config->OCPolarity << 12);
4506 /* Write to TIMx CR2 */
4509 /* Write to TIMx CCMR2 */
4510 TIMx->CCMR2 = tmpccmrx;
4512 /* Set the Capture Compare Register value */
4513 TIMx->CCR4 = OC_Config->Pulse;
4515 /* Write to TIMx CCER */
4516 TIMx->CCER = tmpccer;
4520 * @brief Configure the TI1 as Input.
4521 * @param TIMx to select the TIM peripheral.
4522 * @param TIM_ICPolarity : The Input Polarity.
4523 * This parameter can be one of the following values:
4524 * @arg TIM_ICPolarity_Rising
4525 * @arg TIM_ICPolarity_Falling
4526 * @arg TIM_ICPolarity_BothEdge
4527 * @param TIM_ICSelection: specifies the input to be used.
4528 * This parameter can be one of the following values:
4529 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
4530 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
4531 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
4532 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4533 * This parameter must be a value between 0x00 and 0x0F.
4536 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4537 uint32_t TIM_ICFilter)
4539 uint32_t tmpccmr1 = 0;
4540 uint32_t tmpccer = 0;
4542 /* Disable the Channel 1: Reset the CC1E Bit */
4543 TIMx->CCER &= ~TIM_CCER_CC1E;
4544 tmpccmr1 = TIMx->CCMR1;
4545 tmpccer = TIMx->CCER;
4547 /* Select the Input */
4548 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4550 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4551 tmpccmr1 |= TIM_ICSelection;
4555 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4556 tmpccmr1 |= TIM_CCMR1_CC1S_0;
4559 /* Set the filter */
4560 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4561 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
4563 /* Select the Polarity and set the CC1E Bit */
4564 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4565 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
4567 /* Write to TIMx CCMR1 and CCER registers */
4568 TIMx->CCMR1 = tmpccmr1;
4569 TIMx->CCER = tmpccer;
4573 * @brief Configure the Polarity and Filter for TI1.
4574 * @param TIMx to select the TIM peripheral.
4575 * @param TIM_ICPolarity : The Input Polarity.
4576 * This parameter can be one of the following values:
4577 * @arg TIM_ICPolarity_Rising
4578 * @arg TIM_ICPolarity_Falling
4579 * @arg TIM_ICPolarity_BothEdge
4580 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4581 * This parameter must be a value between 0x00 and 0x0F.
4584 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4586 uint32_t tmpccmr1 = 0;
4587 uint32_t tmpccer = 0;
4589 /* Disable the Channel 1: Reset the CC1E Bit */
4590 tmpccer = TIMx->CCER;
4591 TIMx->CCER &= ~TIM_CCER_CC1E;
4592 tmpccmr1 = TIMx->CCMR1;
4594 /* Set the filter */
4595 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4596 tmpccmr1 |= (TIM_ICFilter << 4);
4598 /* Select the Polarity and set the CC1E Bit */
4599 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4600 tmpccer |= TIM_ICPolarity;
4602 /* Write to TIMx CCMR1 and CCER registers */
4603 TIMx->CCMR1 = tmpccmr1;
4604 TIMx->CCER = tmpccer;
4608 * @brief Configure the TI2 as Input.
4609 * @param TIMx to select the TIM peripheral
4610 * @param TIM_ICPolarity : The Input Polarity.
4611 * This parameter can be one of the following values:
4612 * @arg TIM_ICPolarity_Rising
4613 * @arg TIM_ICPolarity_Falling
4614 * @arg TIM_ICPolarity_BothEdge
4615 * @param TIM_ICSelection: specifies the input to be used.
4616 * This parameter can be one of the following values:
4617 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
4618 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
4619 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
4620 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4621 * This parameter must be a value between 0x00 and 0x0F.
4624 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4625 uint32_t TIM_ICFilter)
4627 uint32_t tmpccmr1 = 0;
4628 uint32_t tmpccer = 0;
4630 /* Disable the Channel 2: Reset the CC2E Bit */
4631 TIMx->CCER &= ~TIM_CCER_CC2E;
4632 tmpccmr1 = TIMx->CCMR1;
4633 tmpccer = TIMx->CCER;
4635 /* Select the Input */
4636 tmpccmr1 &= ~TIM_CCMR1_CC2S;
4637 tmpccmr1 |= (TIM_ICSelection << 8);
4639 /* Set the filter */
4640 tmpccmr1 &= ~TIM_CCMR1_IC2F;
4641 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
4643 /* Select the Polarity and set the CC2E Bit */
4644 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4645 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
4647 /* Write to TIMx CCMR1 and CCER registers */
4648 TIMx->CCMR1 = tmpccmr1 ;
4649 TIMx->CCER = tmpccer;
4653 * @brief Configure the Polarity and Filter for TI2.
4654 * @param TIMx to select the TIM peripheral.
4655 * @param TIM_ICPolarity : The Input Polarity.
4656 * This parameter can be one of the following values:
4657 * @arg TIM_ICPolarity_Rising
4658 * @arg TIM_ICPolarity_Falling
4659 * @arg TIM_ICPolarity_BothEdge
4660 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4661 * This parameter must be a value between 0x00 and 0x0F.
4664 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4666 uint32_t tmpccmr1 = 0;
4667 uint32_t tmpccer = 0;
4669 /* Disable the Channel 2: Reset the CC2E Bit */
4670 TIMx->CCER &= ~TIM_CCER_CC2E;
4671 tmpccmr1 = TIMx->CCMR1;
4672 tmpccer = TIMx->CCER;
4674 /* Set the filter */
4675 tmpccmr1 &= ~TIM_CCMR1_IC2F;
4676 tmpccmr1 |= (TIM_ICFilter << 12);
4678 /* Select the Polarity and set the CC2E Bit */
4679 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4680 tmpccer |= (TIM_ICPolarity << 4);
4682 /* Write to TIMx CCMR1 and CCER registers */
4683 TIMx->CCMR1 = tmpccmr1 ;
4684 TIMx->CCER = tmpccer;
4688 * @brief Configure the TI3 as Input.
4689 * @param TIMx to select the TIM peripheral
4690 * @param TIM_ICPolarity : The Input Polarity.
4691 * This parameter can be one of the following values:
4692 * @arg TIM_ICPolarity_Rising
4693 * @arg TIM_ICPolarity_Falling
4694 * @arg TIM_ICPolarity_BothEdge
4695 * @param TIM_ICSelection: specifies the input to be used.
4696 * This parameter can be one of the following values:
4697 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
4698 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
4699 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
4700 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4701 * This parameter must be a value between 0x00 and 0x0F.
4704 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4705 uint32_t TIM_ICFilter)
4707 uint32_t tmpccmr2 = 0;
4708 uint32_t tmpccer = 0;
4710 /* Disable the Channel 3: Reset the CC3E Bit */
4711 TIMx->CCER &= ~TIM_CCER_CC3E;
4712 tmpccmr2 = TIMx->CCMR2;
4713 tmpccer = TIMx->CCER;
4715 /* Select the Input */
4716 tmpccmr2 &= ~TIM_CCMR2_CC3S;
4717 tmpccmr2 |= TIM_ICSelection;
4719 /* Set the filter */
4720 tmpccmr2 &= ~TIM_CCMR2_IC3F;
4721 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
4723 /* Select the Polarity and set the CC3E Bit */
4724 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
4725 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
4727 /* Write to TIMx CCMR2 and CCER registers */
4728 TIMx->CCMR2 = tmpccmr2;
4729 TIMx->CCER = tmpccer;
4733 * @brief Configure the TI4 as Input.
4734 * @param TIMx to select the TIM peripheral
4735 * @param TIM_ICPolarity : The Input Polarity.
4736 * This parameter can be one of the following values:
4737 * @arg TIM_ICPolarity_Rising
4738 * @arg TIM_ICPolarity_Falling
4739 * @arg TIM_ICPolarity_BothEdge
4740 * @param TIM_ICSelection: specifies the input to be used.
4741 * This parameter can be one of the following values:
4742 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
4743 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
4744 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
4745 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4746 * This parameter must be a value between 0x00 and 0x0F.
4749 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4750 uint32_t TIM_ICFilter)
4752 uint32_t tmpccmr2 = 0;
4753 uint32_t tmpccer = 0;
4755 /* Disable the Channel 4: Reset the CC4E Bit */
4756 TIMx->CCER &= ~TIM_CCER_CC4E;
4757 tmpccmr2 = TIMx->CCMR2;
4758 tmpccer = TIMx->CCER;
4760 /* Select the Input */
4761 tmpccmr2 &= ~TIM_CCMR2_CC4S;
4762 tmpccmr2 |= (TIM_ICSelection << 8);
4764 /* Set the filter */
4765 tmpccmr2 &= ~TIM_CCMR2_IC4F;
4766 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
4768 /* Select the Polarity and set the CC4E Bit */
4769 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
4770 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
4772 /* Write to TIMx CCMR2 and CCER registers */
4773 TIMx->CCMR2 = tmpccmr2;
4774 TIMx->CCER = tmpccer ;
4778 * @brief Selects the Input Trigger source
4779 * @param TIMx to select the TIM peripheral
4780 * @param InputTriggerSource: The Input Trigger source.
4781 * This parameter can be one of the following values:
4782 * @arg TIM_TS_ITR0: Internal Trigger 0
4783 * @arg TIM_TS_ITR1: Internal Trigger 1
4784 * @arg TIM_TS_ITR2: Internal Trigger 2
4785 * @arg TIM_TS_ITR3: Internal Trigger 3
4786 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
4787 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
4788 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
4789 * @arg TIM_TS_ETRF: External Trigger input
4792 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
4794 uint32_t tmpsmcr = 0;
4796 /* Get the TIMx SMCR register value */
4797 tmpsmcr = TIMx->SMCR;
4798 /* Reset the TS Bits */
4799 tmpsmcr &= ~TIM_SMCR_TS;
4800 /* Set the Input Trigger source and the slave mode*/
4801 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
4802 /* Write to TIMx SMCR */
4803 TIMx->SMCR = tmpsmcr;
4806 * @brief Configures the TIMx External Trigger (ETR).
4807 * @param TIMx to select the TIM peripheral
4808 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
4809 * This parameter can be one of the following values:
4810 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
4811 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
4812 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
4813 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
4814 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
4815 * This parameter can be one of the following values:
4816 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
4817 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
4818 * @param ExtTRGFilter: External Trigger Filter.
4819 * This parameter must be a value between 0x00 and 0x0F
4822 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
4823 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
4825 uint32_t tmpsmcr = 0;
4827 tmpsmcr = TIMx->SMCR;
4829 /* Reset the ETR Bits */
4830 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4832 /* Set the Prescaler, the Filter value and the Polarity */
4833 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
4835 /* Write to TIMx SMCR */
4836 TIMx->SMCR = tmpsmcr;
4840 * @brief Enables or disables the TIM Capture Compare Channel x.
4841 * @param TIMx to select the TIM peripheral
4842 * @param Channel: specifies the TIM Channel
4843 * This parameter can be one of the following values:
4844 * @arg TIM_Channel_1: TIM Channel 1
4845 * @arg TIM_Channel_2: TIM Channel 2
4846 * @arg TIM_Channel_3: TIM Channel 3
4847 * @arg TIM_Channel_4: TIM Channel 4
4848 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
4849 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
4852 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
4856 /* Check the parameters */
4857 assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel));
4859 tmp = TIM_CCER_CC1E << Channel;
4861 /* Reset the CCxE Bit */
4864 /* Set or reset the CCxE Bit */
4865 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
4868 * @brief Set the slave timer configuration.
4869 * @param htim : TIM handle
4870 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4871 * contains the selected trigger (internal trigger input, filtered
4872 * timer input or external trigger input) and the ) and the Slave
4873 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4876 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
4877 TIM_SlaveConfigTypeDef * sSlaveConfig)
4879 uint32_t tmpsmcr = 0;
4880 uint32_t tmpccmr1 = 0;
4881 uint32_t tmpccer = 0;
4883 /* Get the TIMx SMCR register value */
4884 tmpsmcr = htim->Instance->SMCR;
4886 /* Reset the Trigger Selection Bits */
4887 tmpsmcr &= ~TIM_SMCR_TS;
4888 /* Set the Input Trigger source */
4889 tmpsmcr |= sSlaveConfig->InputTrigger;
4891 /* Reset the slave mode Bits */
4892 tmpsmcr &= ~TIM_SMCR_SMS;
4893 /* Set the slave mode */
4894 tmpsmcr |= sSlaveConfig->SlaveMode;
4896 /* Write to TIMx SMCR */
4897 htim->Instance->SMCR = tmpsmcr;
4899 /* Configure the trigger prescaler, filter, and polarity */
4900 switch (sSlaveConfig->InputTrigger)
4904 /* Check the parameters */
4905 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
4906 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
4907 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4908 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4909 /* Configure the ETR Trigger source */
4910 TIM_ETR_SetConfig(htim->Instance,
4911 sSlaveConfig->TriggerPrescaler,
4912 sSlaveConfig->TriggerPolarity,
4913 sSlaveConfig->TriggerFilter);
4917 case TIM_TS_TI1F_ED:
4919 /* Check the parameters */
4920 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4921 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4923 /* Disable the Channel 1: Reset the CC1E Bit */
4924 tmpccer = htim->Instance->CCER;
4925 htim->Instance->CCER &= ~TIM_CCER_CC1E;
4926 tmpccmr1 = htim->Instance->CCMR1;
4928 /* Set the filter */
4929 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4930 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
4932 /* Write to TIMx CCMR1 and CCER registers */
4933 htim->Instance->CCMR1 = tmpccmr1;
4934 htim->Instance->CCER = tmpccer;
4941 /* Check the parameters */
4942 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4943 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4944 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4946 /* Configure TI1 Filter and Polarity */
4947 TIM_TI1_ConfigInputStage(htim->Instance,
4948 sSlaveConfig->TriggerPolarity,
4949 sSlaveConfig->TriggerFilter);
4955 /* Check the parameters */
4956 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4957 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4958 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4960 /* Configure TI2 Filter and Polarity */
4961 TIM_TI2_ConfigInputStage(htim->Instance,
4962 sSlaveConfig->TriggerPolarity,
4963 sSlaveConfig->TriggerFilter);
4969 /* Check the parameter */
4970 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4976 /* Check the parameter */
4977 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4983 /* Check the parameter */
4984 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4990 /* Check the parameter */
4991 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5012 #endif /* HAL_TIM_MODULE_ENABLED */
5020 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/