2 ******************************************************************************
3 * @file stm32l0xx_hal_tim.h
4 * @author MCD Application Team
6 * @date 06-February-2015
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
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18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L0xx_HAL_TIM_H
40 #define __STM32L0xx_HAL_TIM_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l0xx_hal_def.h"
49 /** @addtogroup STM32L0xx_HAL_Driver
53 /** @defgroup TIM TIM (Timer)
57 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup TIM_Exported_Types TIM Exported Types
63 /** @defgroup TIM_Base_Configuration TIM base configuration structure
67 * @brief TIM Time base Configuration Structure definition
71 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
74 uint32_t CounterMode; /*!< Specifies the counter mode.
75 This parameter can be a value of @ref TIM_Counter_Mode */
77 uint32_t Period; /*!< Specifies the period value to be loaded into the active
78 Auto-Reload Register at the next update event.
79 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
81 uint32_t ClockDivision; /*!< Specifies the clock division.
82 This parameter can be a value of @ref TIM_ClockDivision */
83 } TIM_Base_InitTypeDef;
88 /** @defgroup TIM_Output_Configuration TIM output compare configuration structure
93 * @brief TIM Output Compare Configuration Structure definition
98 uint32_t OCMode; /*!< Specifies the TIM mode.
99 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
101 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
102 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
104 uint32_t OCPolarity; /*!< Specifies the output polarity.
105 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
107 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
108 This parameter can be a value of @ref TIM_Output_Fast_State
109 @note This parameter is valid only in PWM1 and PWM2 mode. */
111 } TIM_OC_InitTypeDef;
116 /** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure
120 * @brief TIM One Pulse Mode Configuration Structure definition
124 uint32_t OCMode; /*!< Specifies the TIM mode.
125 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
127 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
128 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
130 uint32_t OCPolarity; /*!< Specifies the output polarity.
131 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
137 uint32_t ICSelection; /*!< Specifies the input.
138 This parameter can be a value of @ref TIM_Input_Capture_Selection */
140 uint32_t ICFilter; /*!< Specifies the input capture filter.
141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
142 } TIM_OnePulse_InitTypeDef;
147 /** @defgroup TIM_Input_Capture TIM input capture configuration structure
151 * @brief TIM Input Capture Configuration Structure definition
156 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
157 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
159 uint32_t ICSelection; /*!< Specifies the input.
160 This parameter can be a value of @ref TIM_Input_Capture_Selection */
162 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
163 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
165 uint32_t ICFilter; /*!< Specifies the input capture filter.
166 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
167 } TIM_IC_InitTypeDef;
172 /** @defgroup TIM_Encoder TIM encoder configuration structure
176 * @brief TIM Encoder Configuration Structure definition
181 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
182 This parameter can be a value of @ref TIM_Encoder_Mode */
184 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
185 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
187 uint32_t IC1Selection; /*!< Specifies the input.
188 This parameter can be a value of @ref TIM_Input_Capture_Selection */
190 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
191 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
193 uint32_t IC1Filter; /*!< Specifies the input capture filter.
194 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
196 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
197 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
199 uint32_t IC2Selection; /*!< Specifies the input.
200 This parameter can be a value of @ref TIM_Input_Capture_Selection */
202 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
203 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
205 uint32_t IC2Filter; /*!< Specifies the input capture filter.
206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
207 } TIM_Encoder_InitTypeDef;
212 /** @defgroup TIM_Clock_Configuration TIM clock configuration structure
216 * @brief Clock Configuration Handle Structure definition
220 uint32_t ClockSource; /*!< TIM clock sources.
221 This parameter can be a value of @ref TIM_Clock_Source */
222 uint32_t ClockPolarity; /*!< TIM clock polarity.
223 This parameter can be a value of @ref TIM_Clock_Polarity */
224 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
225 This parameter can be a value of @ref TIM_Clock_Prescaler */
226 uint32_t ClockFilter; /*!< TIM clock filter.
227 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
228 }TIM_ClockConfigTypeDef;
233 /** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure
237 * @brief Clear Input Configuration Handle Structure definition
241 uint32_t ClearInputState; /*!< TIM clear Input state.
242 This parameter can be ENABLE or DISABLE */
243 uint32_t ClearInputSource; /*!< TIM clear Input sources.
244 This parameter can be a value of @ref TIM_ClearInput_Source */
245 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
246 This parameter can be a value of @ref TIM_ClearInput_Polarity */
247 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
248 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
249 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
250 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
251 }TIM_ClearInputConfigTypeDef;
256 /** @defgroup TIM_Slave_Configuratio TIM slave configuration structure
260 * @brief TIM Slave configuration Structure definition
263 uint32_t SlaveMode; /*!< Slave mode selection.
264 This parameter can be a value of @ref TIM_Slave_Mode */
265 uint32_t InputTrigger; /*!< Input Trigger source.
266 This parameter can be a value of @ref TIM_Trigger_Selection */
267 uint32_t TriggerPolarity; /*!< Input Trigger polarity.
268 This parameter can be a value of @ref TIM_Trigger_Polarity */
269 uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
270 This parameter can be a value of @ref TIM_Trigger_Prescaler */
271 uint32_t TriggerFilter; /*!< Input trigger filter.
272 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
274 }TIM_SlaveConfigTypeDef;
279 /** @defgroup TIM_State_Definition TIM state definition
283 * @brief HAL State structures definition
287 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
288 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
289 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
290 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
291 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
292 }HAL_TIM_StateTypeDef;
297 /** @defgroup TIM_Active_Channel TIM active channel definition
301 * @brief HAL Active channel structures definition
305 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
306 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
307 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
308 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
309 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
310 }HAL_TIM_ActiveChannel;
315 /** @defgroup TIM_Handle TIM handler
319 * @brief TIM Time Base Handle Structure definition
323 TIM_TypeDef *Instance; /*!< Register base address */
324 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
325 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
326 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
327 This array is accessed by a @ref DMA_Handle_index */
328 HAL_LockTypeDef Lock; /*!< Locking object */
329 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
338 /* Exported constants --------------------------------------------------------*/
339 /** @defgroup TIM_Exported_Constants TIM Exported Constants
344 #define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFF)
346 #define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
349 /** @defgroup TIM_Input_Channel_Polarity Input channel polarity
352 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
353 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
354 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
359 /** @defgroup TIM_ETR_Polarity ETR polarity
362 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
363 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
368 /** @defgroup TIM_ETR_Prescaler ETR prescaler
371 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
372 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
373 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
374 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
379 /** @defgroup TIM_Counter_Mode Counter mode
382 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
383 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
384 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
385 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
386 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
390 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
391 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
392 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
393 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
394 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
399 /** @defgroup TIM_ClockDivision Clock division
402 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
403 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
404 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
408 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
409 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
410 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
413 /** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes
416 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
417 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
418 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
419 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
420 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
421 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
422 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
423 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
428 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
429 ((__MODE__) == TIM_OCMODE_PWM2))
431 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
432 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
433 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
434 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
435 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
436 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
439 /** @defgroup TIM_Output_Compare_State Output compare state
442 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
443 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
448 /** @defgroup TIM_Output_Fast_State Output fast state
451 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
452 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
456 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
457 ((__STATE__) == TIM_OCFAST_ENABLE))
459 /** @defgroup TIM_Output_Compare_N_State Output compare N state
462 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
463 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
468 /** @defgroup TIM_Output_Compare_Polarity Output compare polarity
471 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
472 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
476 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
477 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
479 /** @defgroup TIM_Channel TIM channels
482 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
483 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
484 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
485 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
486 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
491 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
492 ((__CHANNEL__) == TIM_CHANNEL_2) || \
493 ((__CHANNEL__) == TIM_CHANNEL_3) || \
494 ((__CHANNEL__) == TIM_CHANNEL_4) || \
495 ((__CHANNEL__) == TIM_CHANNEL_ALL))
497 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
498 ((__CHANNEL__) == TIM_CHANNEL_2))
501 /** @defgroup TIM_Input_Capture_Polarity Input capture polarity
504 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
505 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
506 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
510 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
511 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
512 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
515 /** @defgroup TIM_Input_Capture_Selection Input capture selection
518 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
519 connected to IC1, IC2, IC3 or IC4, respectively */
520 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
521 connected to IC2, IC1, IC4 or IC3, respectively */
522 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
524 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
525 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
526 ((__SELECTION__) == TIM_ICSELECTION_TRC))
531 /** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler
534 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
535 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
536 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
537 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
541 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
542 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
543 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
544 ((__PRESCALER__) == TIM_ICPSC_DIV8))
546 /** @defgroup TIM_One_Pulse_Mode One pulse mode
549 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
550 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
554 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
555 ((__MODE__) == TIM_OPMODE_REPETITIVE))
557 /** @defgroup TIM_Encoder_Mode Encoder_Mode
560 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
561 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
562 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
566 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
567 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
568 ((__MODE__) == TIM_ENCODERMODE_TI12))
570 /** @defgroup TIM_Interrupt_definition Interrupt definition
573 #define TIM_IT_UPDATE (TIM_DIER_UIE)
574 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
575 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
576 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
577 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
578 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
582 #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFFA0) == 0x00000000) && ((__IT__) != 0x00000000))
584 #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \
585 ((__IT__) == TIM_IT_CC1) || \
586 ((__IT__) == TIM_IT_CC2) || \
587 ((__IT__) == TIM_IT_CC3) || \
588 ((__IT__) == TIM_IT_CC4) || \
589 ((__IT__) == TIM_IT_TRIGGER))
592 /** @defgroup TIM_DMA_sources DMA sources
595 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
596 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
597 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
598 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
599 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
600 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
604 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
608 /** @defgroup TIM_Event_Source Event sources
611 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
612 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
613 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
614 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
615 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
616 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
620 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0) == 0x00000000) && ((__SOURCE__) != 0x00000000))
623 /** @defgroup TIM_Flag_definition Flag definition
626 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
627 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
628 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
629 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
630 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
631 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
632 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
633 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
634 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
635 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
639 #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
640 ((__FLAG__) == TIM_FLAG_CC1) || \
641 ((__FLAG__) == TIM_FLAG_CC2) || \
642 ((__FLAG__) == TIM_FLAG_CC3) || \
643 ((__FLAG__) == TIM_FLAG_CC4) || \
644 ((__FLAG__) == TIM_FLAG_TRIGGER) || \
645 ((__FLAG__) == TIM_FLAG_CC1OF) || \
646 ((__FLAG__) == TIM_FLAG_CC2OF) || \
647 ((__FLAG__) == TIM_FLAG_CC3OF) || \
648 ((__FLAG__) == TIM_FLAG_CC4OF))
651 /** @defgroup TIM_Clock_Source Clock source
654 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
655 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
656 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
657 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
658 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
659 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
660 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
661 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
662 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
663 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
668 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
669 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
670 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
671 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
672 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
673 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
674 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
675 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
676 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
677 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
680 /** @defgroup TIM_Clock_Polarity Clock polarity
683 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
684 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
685 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
686 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
687 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
691 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
692 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
693 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
694 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
695 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
697 /** @defgroup TIM_Clock_Prescaler Clock prescaler
700 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
701 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
702 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
703 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
707 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
708 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
709 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
710 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
713 /* Check clock filter */
714 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
716 /** @defgroup TIM_ClearInput_Source Clear input source
719 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
720 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
725 #define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) || \
726 ((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR))
729 /** @defgroup TIM_ClearInput_Polarity Clear input polarity
732 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
733 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
737 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
738 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
741 /** @defgroup TIM_ClearInput_Prescaler Clear input prescaler
744 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
745 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
746 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
747 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
751 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
752 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
753 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
754 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
757 /* Check IC filter */
758 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
761 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
764 #define TIM_TRGO_RESET ((uint32_t)0x0000)
765 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
766 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
767 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
768 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
769 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
770 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
771 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
775 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
776 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
777 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
778 ((__SOURCE__) == TIM_TRGO_OC1) || \
779 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
780 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
781 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
782 ((__SOURCE__) == TIM_TRGO_OC4REF))
786 /** @defgroup TIM_Slave_Mode Slave mode
789 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
790 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
791 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
792 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
793 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
797 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
798 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
799 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
800 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
801 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
803 /** @defgroup TIM_Master_Slave_Mode Master slave mode
807 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
808 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
812 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
813 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
815 /** @defgroup TIM_Trigger_Selection Trigger selection
818 #define TIM_TS_ITR0 ((uint32_t)0x0000)
819 #define TIM_TS_ITR1 ((uint32_t)0x0010)
820 #define TIM_TS_ITR2 ((uint32_t)0x0020)
821 #define TIM_TS_ITR3 ((uint32_t)0x0030)
822 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
823 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
824 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
825 #define TIM_TS_ETRF ((uint32_t)0x0070)
826 #define TIM_TS_NONE ((uint32_t)0xFFFF)
830 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
831 ((__SELECTION__) == TIM_TS_ITR1) || \
832 ((__SELECTION__) == TIM_TS_ITR2) || \
833 ((__SELECTION__) == TIM_TS_ITR3) || \
834 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
835 ((__SELECTION__) == TIM_TS_TI1FP1) || \
836 ((__SELECTION__) == TIM_TS_TI2FP2) || \
837 ((__SELECTION__) == TIM_TS_ETRF))
838 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
839 ((__SELECTION__) == TIM_TS_ITR1) || \
840 ((__SELECTION__) == TIM_TS_ITR2) || \
841 ((__SELECTION__) == TIM_TS_ITR3) || \
842 ((__SELECTION__) == TIM_TS_NONE))
845 /** @defgroup TIM_Trigger_Polarity Trigger polarity
848 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
849 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
850 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
851 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
852 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
856 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
857 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
858 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
859 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
860 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
863 /** @defgroup TIM_Trigger_Prescaler Trigger prescaler
866 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
867 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
868 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
869 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
873 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
874 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
875 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
876 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
879 /* Check trigger filter */
880 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
883 /** @defgroup TIM_TI1_Selection TI1 selection
886 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
887 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
891 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
892 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
895 /** @defgroup TIM_DMA_Base_address DMA base address
898 #define TIM_DMABASE_CR1 (0x00000000)
899 #define TIM_DMABASE_CR2 (0x00000001)
900 #define TIM_DMABASE_SMCR (0x00000002)
901 #define TIM_DMABASE_DIER (0x00000003)
902 #define TIM_DMABASE_SR (0x00000004)
903 #define TIM_DMABASE_EGR (0x00000005)
904 #define TIM_DMABASE_CCMR1 (0x00000006)
905 #define TIM_DMABASE_CCMR2 (0x00000007)
906 #define TIM_DMABASE_CCER (0x00000008)
907 #define TIM_DMABASE_CNT (0x00000009)
908 #define TIM_DMABASE_PSC (0x0000000A)
909 #define TIM_DMABASE_ARR (0x0000000B)
910 #define TIM_DMABASE_CCR1 (0x0000000D)
911 #define TIM_DMABASE_CCR2 (0x0000000E)
912 #define TIM_DMABASE_CCR3 (0x0000000F)
913 #define TIM_DMABASE_CCR4 (0x00000010)
914 #define TIM_DMABASE_DCR (0x00000012)
915 #define TIM_DMABASE_OR (0x00000013)
919 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
920 ((__BASE__) == TIM_DMABASE_CR2) || \
921 ((__BASE__) == TIM_DMABASE_SMCR) || \
922 ((__BASE__) == TIM_DMABASE_DIER) || \
923 ((__BASE__) == TIM_DMABASE_SR) || \
924 ((__BASE__) == TIM_DMABASE_EGR) || \
925 ((__BASE__) == TIM_DMABASE_CCMR1) || \
926 ((__BASE__) == TIM_DMABASE_CCMR2 ) || \
927 ((__BASE__) == TIM_DMABASE_CCER) || \
928 ((__BASE__) == TIM_DMABASE_CNT) || \
929 ((__BASE__) == TIM_DMABASE_PSC) || \
930 ((__BASE__) == TIM_DMABASE_ARR) || \
931 ((__BASE__) == TIM_DMABASE_CCR1) || \
932 ((__BASE__) == TIM_DMABASE_CCR2) || \
933 ((__BASE__) == TIM_DMABASE_CCR3) || \
934 ((__BASE__) == TIM_DMABASE_CCR4) || \
935 ((__BASE__) == TIM_DMABASE_DCR) || \
936 ((__BASE__) == TIM_DMABASE_OR))
939 /** @defgroup TIM_DMA_Burst_Length DMA burst length
942 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
943 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
944 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
945 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
946 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
947 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
948 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
949 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
950 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
951 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
952 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
953 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
954 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
955 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
956 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
957 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
958 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
959 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
963 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) || \
964 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
965 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
966 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
967 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
968 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
969 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
970 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
971 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) || \
972 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
973 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) || \
974 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
975 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
976 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
977 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
978 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
979 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
980 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS ))
983 /* Check IC filter */
984 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
986 /** @defgroup DMA_Handle_index DMA handle index
989 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
990 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
991 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
992 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
993 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
994 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5) /*!< Index of the DMA handle used for Trigger DMA requests */
999 /** @defgroup Channel_CC_State Channel state
1002 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
1003 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
1012 /* Exported macro ------------------------------------------------------------*/
1013 /** @defgroup TIM_Exported_Macro TIM Exported Macro
1017 /** @brief Reset UART handle state
1018 * @param __HANDLE__ : TIM handle
1021 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1024 * @brief Enable the TIM peripheral.
1025 * @param __HANDLE__ : TIM handle
1028 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1030 /* The counter of a timer instance is disabled only if all the CCx channels have
1032 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1035 * @brief Disable the TIM peripheral.
1036 * @param __HANDLE__ : TIM handle
1039 #define __HAL_TIM_DISABLE(__HANDLE__) \
1041 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
1043 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1047 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1048 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1049 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1050 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1051 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1052 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1054 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1055 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1057 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1058 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1060 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1061 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1062 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
1063 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1064 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
1066 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1067 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1068 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1069 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1070 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1072 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1073 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1074 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
1075 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
1076 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
1078 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1079 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1080 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1081 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1082 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
1085 * @brief Sets the TIM Capture Compare Register value on runtime without
1086 * calling another time ConfigChannel function.
1087 * @param __HANDLE__ : TIM handle.
1088 * @param __CHANNEL__ : TIM Channels to be configured.
1089 * This parameter can be one of the following values:
1090 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1091 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1092 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1093 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1094 * @param __COMPARE__: specifies the Capture Compare register new value.
1097 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1098 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
1101 * @brief Gets the TIM Capture Compare Register value on runtime
1102 * @param __HANDLE__ : TIM handle.
1103 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
1104 * This parameter can be one of the following values:
1105 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1106 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1107 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1108 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1111 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1112 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
1115 * @brief Sets the TIM Counter Register value on runtime.
1116 * @param __HANDLE__ : TIM handle.
1117 * @param __COUNTER__: specifies the Counter register new value.
1120 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1123 * @brief Gets the TIM Counter Register value on runtime.
1124 * @param __HANDLE__ : TIM handle.
1127 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1130 * @brief Sets the TIM Autoreload Register value on runtime without calling
1131 * another time any Init function.
1132 * @param __HANDLE__ : TIM handle.
1133 * @param __AUTORELOAD__: specifies the Counter register new value.
1136 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1138 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1139 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1142 * @brief Gets the TIM Autoreload Register value on runtime
1143 * @param __HANDLE__ : TIM handle.
1146 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1149 * @brief Sets the TIM Clock Division value on runtime without calling
1150 * another time any Init function.
1151 * @param __HANDLE__ : TIM handle.
1152 * @param __CKD__: specifies the clock division value.
1153 * This parameter can be one of the following value:
1154 * @arg TIM_CLOCKDIVISION_DIV1
1155 * @arg TIM_CLOCKDIVISION_DIV2
1156 * @arg TIM_CLOCKDIVISION_DIV4
1159 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1161 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1162 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1163 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1166 * @brief Gets the TIM Clock Division value on runtime
1167 * @param __HANDLE__ : TIM handle.
1170 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1173 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1174 * another time HAL_TIM_IC_ConfigChannel() function.
1175 * @param __HANDLE__ : TIM handle.
1176 * @param __CHANNEL__ : TIM Channels to be configured.
1177 * This parameter can be one of the following values:
1178 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1179 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1180 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1181 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1182 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1183 * This parameter can be one of the following values:
1184 * @arg TIM_ICPSC_DIV1: no prescaler
1185 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1186 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1187 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1190 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1192 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1193 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1197 * @brief Gets the TIM Input Capture prescaler on runtime
1198 * @param __HANDLE__ : TIM handle.
1199 * @param __CHANNEL__ : TIM Channels to be configured.
1200 * This parameter can be one of the following values:
1201 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1202 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1203 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1204 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1207 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1208 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1209 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1210 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1211 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1215 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
1216 * @param __HANDLE__: TIM handle.
1217 * @note When the URS bit of the TIMx_CR1 register is set, only counter
1218 * overflow/underflow generates an update interrupt or DMA request (if
1222 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1223 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1226 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
1227 * @param __HANDLE__: TIM handle.
1228 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
1229 * following events generate an update interrupt or DMA request (if
1231 *
\96 Counter overflow/underflow
1232 *
\96 Setting the UG bit
1233 *
\96 Update generation through the slave mode controller
1236 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1237 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1240 * @brief Sets the TIM Capture x input polarity on runtime.
1241 * @param __HANDLE__: TIM handle.
1242 * @param __CHANNEL__: TIM Channels to be configured.
1243 * This parameter can be one of the following values:
1244 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1245 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1246 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1247 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1248 * @param __POLARITY__: Polarity for TIx source
1249 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1250 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1251 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1252 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
1255 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1257 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1258 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1265 /* Include TIM HAL Extension module */
1266 #include "stm32l0xx_hal_tim_ex.h"
1268 /* Exported functions --------------------------------------------------------*/
1269 /** @defgroup TIM_Exported_Functions TIM Exported Functions
1273 /* Exported functions --------------------------------------------------------*/
1274 /* Time Base functions ********************************************************/
1276 /** @defgroup TIM_Exported_Functions_Group1 Timer Base functions
1277 * @brief Time Base functions
1280 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1281 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1282 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1283 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1284 /* Blocking mode: Polling */
1285 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1286 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1287 /* Non-Blocking mode: Interrupt */
1288 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1289 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1290 /* Non-Blocking mode: DMA */
1291 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1292 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1299 /* Timer Output Compare functions **********************************************/
1301 /** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions
1302 * @brief Timer Output Compare functions
1306 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1307 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1308 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1309 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1310 /* Blocking mode: Polling */
1311 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1312 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1313 /* Non-Blocking mode: Interrupt */
1314 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1315 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1316 /* Non-Blocking mode: DMA */
1317 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1318 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1324 /* Timer PWM functions *********************************************************/
1326 /** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions
1327 * @brief Timer PWM functions
1330 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1331 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1332 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1333 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1334 /* Blocking mode: Polling */
1335 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1336 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1337 /* Non-Blocking mode: Interrupt */
1338 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1339 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1340 /* Non-Blocking mode: DMA */
1341 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1342 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1347 /* Timer Input Capture functions ***********************************************/
1349 /** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions
1350 * @brief Timer Input Capture functions
1353 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1354 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1355 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1356 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1357 /* Blocking mode: Polling */
1358 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1359 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1360 /* Non-Blocking mode: Interrupt */
1361 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1362 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1363 /* Non-Blocking mode: DMA */
1364 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1365 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1370 /* Timer One Pulse functions ***************************************************/
1372 /** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions
1373 * @brief Timer One Pulse functions
1376 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1377 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1378 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1379 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1380 /* Blocking mode: Polling */
1381 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1382 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1384 /* Non-Blocking mode: Interrupt */
1385 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1386 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1392 /* Timer Encoder functions *****************************************************/
1394 /** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions
1395 * @brief Timer Encoder functions
1398 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1399 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1400 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1401 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1402 /* Blocking mode: Polling */
1403 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1404 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1405 /* Non-Blocking mode: Interrupt */
1406 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1407 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1408 /* Non-Blocking mode: DMA */
1409 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1410 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1416 /* Interrupt Handler functions **********************************************/
1418 /** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management
1419 * @brief Interrupt Handler functions
1422 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1427 /* Control functions *********************************************************/
1429 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
1430 * @brief Control functions
1433 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1434 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1435 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1436 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1437 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1438 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1439 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1440 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1441 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1442 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1443 uint32_t *BurstBuffer, uint32_t BurstLength);
1444 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1445 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1446 uint32_t *BurstBuffer, uint32_t BurstLength);
1447 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1448 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1449 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1455 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1457 /** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions
1458 * @brief Callback functions
1461 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1462 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1463 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1464 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1465 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1466 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1472 /* Peripheral State functions **************************************************/
1474 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
1475 * @brief Peripheral State functions
1478 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1479 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1480 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1481 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1482 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1483 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1484 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1485 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1486 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1508 #endif /* __STM32L0xx_HAL_TIM_H */
1510 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/