2 ******************************************************************************
4 * @author MCD Application Team
6 * @date 5-September-2014
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32L1xx devices.
12 * - Data structures and the address mapping for all peripherals
13 * - Peripheral's registers declarations and bits definition
14 * - Macros to access peripheral
\92s registers hardware
16 ******************************************************************************
19 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ******************************************************************************
50 /** @addtogroup stm32l152xc
54 #ifndef __STM32L152xC_H
55 #define __STM32L152xC_H
62 /** @addtogroup Configuration_section_for_CMSIS
66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
68 #define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
69 #define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */
70 #define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */
71 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
77 /** @addtogroup Peripheral_interrupt_number_definition
82 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
83 * in @ref Library_configuration_section
86 /*!< Interrupt Number Definition */
89 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
92 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
93 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
94 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
96 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
97 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
99 /****** STM32L specific Interrupt Numbers ***********************************************************/
100 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
101 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
102 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
103 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
104 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
105 RCC_IRQn = 5, /*!< RCC global Interrupt */
106 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
107 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
108 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
109 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
110 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
111 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
112 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
113 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
114 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
115 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
116 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
117 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
118 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
119 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
120 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
121 DAC_IRQn = 21, /*!< DAC Interrupt */
122 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
123 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
124 LCD_IRQn = 24, /*!< LCD Interrupt */
125 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
126 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
127 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
128 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
129 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
130 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
131 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
132 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
133 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
134 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
135 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
136 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
137 USART1_IRQn = 37, /*!< USART1 global Interrupt */
138 USART2_IRQn = 38, /*!< USART2 global Interrupt */
139 USART3_IRQn = 39, /*!< USART3 global Interrupt */
140 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
141 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
142 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
143 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
144 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
145 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
146 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
147 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
148 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
149 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
150 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
151 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
152 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
159 #include "core_cm3.h"
160 #include "system_stm32l1xx.h"
163 /** @addtogroup Peripheral_registers_structures
168 * @brief Analog to Digital Converter
173 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
174 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
175 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
176 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
177 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
178 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
188 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
189 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
190 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
191 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
192 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
193 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
194 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
195 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
196 uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */
201 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
202 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
203 } ADC_Common_TypeDef;
211 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
215 * @brief CRC calculation unit
220 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
221 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
222 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
226 * @brief Digital to Analog Converter
231 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
232 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
233 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
234 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
235 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
236 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
237 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
238 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
239 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
240 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
241 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
242 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
243 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
244 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
253 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
254 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
255 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
256 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
260 * @brief DMA Controller
265 __IO uint32_t CCR; /*!< DMA channel x configuration register */
266 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
267 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
268 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
269 } DMA_Channel_TypeDef;
273 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
274 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
278 * @brief External Interrupt/Event Controller
283 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
284 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
285 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
286 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
287 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
288 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
292 * @brief FLASH Registers
296 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
297 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
298 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
299 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
300 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
301 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
302 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
303 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
304 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
305 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
306 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
310 * @brief Option Bytes Registers
314 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
315 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
316 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
317 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
318 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
319 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
323 * @brief Operational Amplifier (OPAMP)
327 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
328 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
329 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
333 * @brief General Purpose IO
338 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
339 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
340 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
341 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
342 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
343 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
344 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
345 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
346 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
347 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
351 * @brief SysTem Configuration
356 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
357 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
358 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
362 * @brief Inter-integrated Circuit Interface
367 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
368 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
369 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
370 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
371 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
372 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
373 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
374 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
375 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
379 * @brief Independent WATCHDOG
384 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
385 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
386 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
387 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
396 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
397 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
398 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
399 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
400 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
401 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
405 * @brief Power Control
410 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
411 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
415 * @brief Reset and Clock Control
420 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
421 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
422 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
423 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
424 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
425 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
426 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
427 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
428 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
429 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
430 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
431 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
432 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
433 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
437 * @brief Routing Interface
442 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
443 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
444 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
445 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
446 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
447 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
448 uint32_t RESERVED1; /*!< Reserved, 0x18 */
449 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
450 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
451 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
452 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
453 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
454 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
455 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
456 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
457 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
461 * @brief Real-Time Clock
465 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
466 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
467 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
468 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
469 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
470 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
471 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
472 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
473 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
474 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
475 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
476 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
477 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
478 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
479 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
480 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
481 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
482 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
483 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
484 uint32_t RESERVED7; /*!< Reserved, 0x4C */
485 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
486 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
487 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
488 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
489 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
490 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
491 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
492 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
493 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
494 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
495 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
496 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
497 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
498 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
499 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
500 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
501 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
502 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
503 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
504 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
505 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
506 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
507 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
508 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
509 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
510 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
511 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
512 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
513 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
514 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
515 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
516 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
520 * @brief Serial Peripheral Interface
525 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
526 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
527 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
528 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
529 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
530 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
531 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
532 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
533 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
541 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
542 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
543 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
544 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
545 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
546 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
547 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
548 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
549 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
550 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
551 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
552 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
553 uint32_t RESERVED12; /*!< Reserved, 0x30 */
554 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
555 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
556 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
557 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
558 uint32_t RESERVED17; /*!< Reserved, 0x44 */
559 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
560 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
561 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
564 * @brief Universal Synchronous Asynchronous Receiver Transmitter
569 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
570 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
571 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
572 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
573 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
574 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
575 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
579 * @brief Universal Serial Bus Full Speed Device
584 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
585 __IO uint16_t RESERVED0; /*!< Reserved */
586 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
587 __IO uint16_t RESERVED1; /*!< Reserved */
588 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
589 __IO uint16_t RESERVED2; /*!< Reserved */
590 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
591 __IO uint16_t RESERVED3; /*!< Reserved */
592 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
593 __IO uint16_t RESERVED4; /*!< Reserved */
594 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
595 __IO uint16_t RESERVED5; /*!< Reserved */
596 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
597 __IO uint16_t RESERVED6; /*!< Reserved */
598 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
599 __IO uint16_t RESERVED7[17]; /*!< Reserved */
600 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
601 __IO uint16_t RESERVED8; /*!< Reserved */
602 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
603 __IO uint16_t RESERVED9; /*!< Reserved */
604 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
605 __IO uint16_t RESERVEDA; /*!< Reserved */
606 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
607 __IO uint16_t RESERVEDB; /*!< Reserved */
608 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
609 __IO uint16_t RESERVEDC; /*!< Reserved */
613 * @brief Window WATCHDOG
617 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
618 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
619 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
623 * @brief Universal Serial Bus Full Speed Device
629 /** @addtogroup Peripheral_memory_map
633 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
634 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */
635 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
636 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
637 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
638 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
639 #define FLASH_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH address for Cat3 */
640 #define FLASH_EEPROM_END ((uint32_t)0x08081FFF) /*!< FLASH EEPROM end address (8KB) */
642 /*!< Peripheral memory map */
643 #define APB1PERIPH_BASE PERIPH_BASE
644 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
645 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
647 /*!< APB1 peripherals */
648 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
649 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
650 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
651 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00)
652 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
653 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
654 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400)
655 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
656 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
657 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
658 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
659 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
660 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
661 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
662 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
663 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
666 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
667 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
669 /* USB device FS SRAM */
670 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
671 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400)
672 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00)
673 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04)
674 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C)
676 /*!< APB2 peripherals */
677 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
678 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
679 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800)
680 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00)
681 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000)
682 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400)
683 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700)
684 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
685 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
687 /*!< AHB peripherals */
688 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000)
689 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400)
690 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800)
691 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00)
692 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000)
693 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400)
694 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
695 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800)
696 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */
697 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
698 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000)
699 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
700 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
701 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
702 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
703 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
704 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
705 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
706 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400)
707 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
708 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
709 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
710 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
711 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
712 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
718 /** @addtogroup Peripheral_declaration
722 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
723 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
724 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
725 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
726 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
727 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
728 #define LCD ((LCD_TypeDef *) LCD_BASE)
729 #define RTC ((RTC_TypeDef *) RTC_BASE)
730 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
731 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
732 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
733 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
734 #define USART2 ((USART_TypeDef *) USART2_BASE)
735 #define USART3 ((USART_TypeDef *) USART3_BASE)
736 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
737 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
739 #define USB ((USB_TypeDef *) USB_BASE)
740 /* USB device FS SRAM */
741 #define PWR ((PWR_TypeDef *) PWR_BASE)
742 #define DAC ((DAC_TypeDef *) DAC_BASE)
743 #define COMP ((COMP_TypeDef *) COMP_BASE)
744 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
745 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
746 #define RI ((RI_TypeDef *) RI_BASE)
747 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
748 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
749 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
750 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
751 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
752 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
753 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
754 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
755 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
756 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
757 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
758 #define USART1 ((USART_TypeDef *) USART1_BASE)
759 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
760 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
761 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
762 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
763 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
764 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
765 #define CRC ((CRC_TypeDef *) CRC_BASE)
766 #define RCC ((RCC_TypeDef *) RCC_BASE)
767 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
768 #define OB ((OB_TypeDef *) OB_BASE)
769 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
770 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
771 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
772 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
773 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
774 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
775 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
776 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
777 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
778 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
779 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
780 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
781 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
782 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
783 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
789 /** @addtogroup Exported_constants
793 /** @addtogroup Peripheral_Registers_Bits_Definition
797 /******************************************************************************/
798 /* Peripheral Registers Bits Definition */
799 /******************************************************************************/
800 /******************************************************************************/
802 /* Analog to Digital Converter (ADC) */
804 /******************************************************************************/
806 /******************** Bit definition for ADC_SR register ********************/
807 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
808 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
809 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
810 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
811 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
812 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
813 #define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
814 #define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
815 #define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
817 /******************* Bit definition for ADC_CR1 register ********************/
818 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
819 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
820 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
821 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
822 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
823 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
825 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
826 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
827 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
828 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
829 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
830 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
831 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
832 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
834 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
835 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
836 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
837 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
839 #define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
840 #define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
842 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
843 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
845 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
846 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
847 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
849 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
851 /******************* Bit definition for ADC_CR2 register ********************/
852 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
853 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
854 #define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
856 #define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
857 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
858 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
859 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
861 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
862 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
863 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
864 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
866 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
867 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
868 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
869 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
870 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
872 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
873 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
874 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
876 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
878 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
879 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
880 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
881 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
882 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
884 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
885 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
886 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
888 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
890 /****************** Bit definition for ADC_SMPR1 register *******************/
891 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
892 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
893 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
894 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
896 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
897 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
898 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
899 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
901 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
902 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
903 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
904 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
906 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
907 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
908 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
909 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
911 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
912 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
913 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
914 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
916 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
917 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
918 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
919 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
921 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
922 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
923 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
924 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
926 #define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
927 #define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
928 #define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
929 #define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
931 #define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
932 #define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
933 #define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
934 #define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
936 #define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
937 #define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
938 #define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
939 #define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
941 /****************** Bit definition for ADC_SMPR2 register *******************/
942 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
943 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
944 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
945 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
947 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
948 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
949 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
950 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
952 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
953 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
954 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
955 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
957 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
958 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
959 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
960 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
962 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
963 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
964 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
965 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
967 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
968 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
969 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
970 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
972 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
973 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
974 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
975 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
977 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
978 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
979 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
980 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
982 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
983 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
984 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
985 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
987 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
988 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
989 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
990 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
992 /****************** Bit definition for ADC_SMPR3 register *******************/
993 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
994 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
995 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
996 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
998 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
999 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
1000 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
1001 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
1003 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
1004 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1005 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1006 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
1008 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
1009 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
1010 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
1011 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
1013 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
1014 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1015 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1016 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
1018 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
1019 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1020 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1021 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1023 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
1024 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1025 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1026 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1028 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
1029 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
1030 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
1031 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
1033 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
1034 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1035 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1036 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1038 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
1039 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
1040 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
1041 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
1043 /****************** Bit definition for ADC_JOFR1 register *******************/
1044 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
1046 /****************** Bit definition for ADC_JOFR2 register *******************/
1047 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
1049 /****************** Bit definition for ADC_JOFR3 register *******************/
1050 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
1052 /****************** Bit definition for ADC_JOFR4 register *******************/
1053 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
1055 /******************* Bit definition for ADC_HTR register ********************/
1056 #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
1058 /******************* Bit definition for ADC_LTR register ********************/
1059 #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
1061 /******************* Bit definition for ADC_SQR1 register *******************/
1062 #define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */
1063 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1064 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1065 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1066 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1067 #define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1069 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
1070 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1071 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1072 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1073 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1074 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1076 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
1077 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1078 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1079 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1080 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1081 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1083 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
1084 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1085 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1086 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1087 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1088 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1090 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
1091 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1092 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1093 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1094 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1095 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1097 /******************* Bit definition for ADC_SQR2 register *******************/
1098 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
1099 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1100 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1101 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1102 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1103 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1105 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
1106 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1107 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1108 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1109 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1110 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1112 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
1113 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1114 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1115 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1116 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1117 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1119 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
1120 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1121 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1122 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1123 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1124 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1126 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
1127 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1128 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1129 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1130 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1131 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1133 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
1134 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1135 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1136 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1137 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1138 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1140 /******************* Bit definition for ADC_SQR3 register *******************/
1141 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
1142 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1143 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1144 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1145 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1146 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1148 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
1149 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1150 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1151 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1152 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1153 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1155 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
1156 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1157 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1158 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1159 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1160 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1162 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
1163 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1164 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1165 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1166 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1167 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1169 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
1170 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1171 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1172 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1173 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1174 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1176 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
1177 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1178 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1179 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1180 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1181 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1183 /******************* Bit definition for ADC_SQR4 register *******************/
1184 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
1185 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1186 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1187 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1188 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1189 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1191 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
1192 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1193 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1194 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1195 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1196 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1198 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
1199 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1200 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1201 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1202 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1203 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1205 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
1206 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1207 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1208 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1209 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1210 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1212 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
1213 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1214 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1215 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1216 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1217 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1219 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
1220 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1221 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1222 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1223 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1224 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1226 /******************* Bit definition for ADC_SQR5 register *******************/
1227 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
1228 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1229 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1230 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1231 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1232 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1234 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
1235 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1236 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1237 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1238 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1239 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1241 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
1242 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1243 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1244 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1245 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1246 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1248 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
1249 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1250 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1251 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1252 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1253 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1255 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
1256 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1257 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1258 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1259 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1260 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1262 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
1263 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1264 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1265 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1266 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1267 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1270 /******************* Bit definition for ADC_JSQR register *******************/
1271 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
1272 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1273 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1274 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1275 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1276 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1278 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
1279 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1280 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1281 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1282 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1283 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1285 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
1286 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1287 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1288 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1289 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1290 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1292 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
1293 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1294 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1295 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1296 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1297 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1299 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
1300 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1301 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1303 /******************* Bit definition for ADC_JDR1 register *******************/
1304 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1306 /******************* Bit definition for ADC_JDR2 register *******************/
1307 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1309 /******************* Bit definition for ADC_JDR3 register *******************/
1310 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1312 /******************* Bit definition for ADC_JDR4 register *******************/
1313 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1315 /******************** Bit definition for ADC_DR register ********************/
1316 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
1318 /******************* Bit definition for ADC_CSR register ********************/
1319 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
1320 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
1321 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
1322 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
1323 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
1324 #define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
1325 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
1327 /******************* Bit definition for ADC_CCR register ********************/
1328 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
1329 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1330 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1331 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
1333 /******************************************************************************/
1335 /* Analog Comparators (COMP) */
1337 /******************************************************************************/
1339 /****************** Bit definition for COMP_CSR register ********************/
1340 #define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
1341 #define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
1342 #define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
1343 #define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
1344 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
1345 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
1347 #define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
1348 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
1349 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
1350 #define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
1351 #define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
1352 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1353 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1354 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1355 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
1356 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
1357 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
1358 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
1360 #define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
1361 #define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
1362 #define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
1364 #define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
1365 #define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
1366 #define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
1368 /******************************************************************************/
1370 /* Operational Amplifier (OPAMP) */
1372 /******************************************************************************/
1373 /******************* Bit definition for OPAMP_CSR register ******************/
1374 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
1375 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
1376 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
1377 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
1378 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
1379 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
1380 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
1381 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
1382 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
1383 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
1384 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
1385 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
1386 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
1387 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
1388 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
1389 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
1390 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
1391 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
1392 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
1393 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
1394 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
1395 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
1397 /******************* Bit definition for OPAMP_OTR register ******************/
1398 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
1399 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
1400 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
1401 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
1402 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
1404 /******************* Bit definition for OPAMP_LPOTR register ****************/
1405 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
1406 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
1407 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
1408 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
1410 /******************************************************************************/
1412 /* CRC calculation unit (CRC) */
1414 /******************************************************************************/
1416 /******************* Bit definition for CRC_DR register *********************/
1417 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
1419 /******************* Bit definition for CRC_IDR register ********************/
1420 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
1422 /******************** Bit definition for CRC_CR register ********************/
1423 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
1425 /******************************************************************************/
1427 /* Digital to Analog Converter (DAC) */
1429 /******************************************************************************/
1431 /******************** Bit definition for DAC_CR register ********************/
1432 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
1433 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
1434 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
1436 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
1437 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1438 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1439 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1441 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1442 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1443 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1445 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1446 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1447 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1448 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1449 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1451 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
1452 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Interrupt enable */
1453 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
1454 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
1455 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
1457 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1458 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
1459 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
1460 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
1462 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1463 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
1464 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
1466 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1467 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1468 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1469 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1470 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1472 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
1473 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
1474 /***************** Bit definition for DAC_SWTRIGR register ******************/
1475 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
1476 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
1478 /***************** Bit definition for DAC_DHR12R1 register ******************/
1479 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
1481 /***************** Bit definition for DAC_DHR12L1 register ******************/
1482 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
1484 /****************** Bit definition for DAC_DHR8R1 register ******************/
1485 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
1487 /***************** Bit definition for DAC_DHR12R2 register ******************/
1488 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!<DAC channel2 12-bit Right aligned data */
1490 /***************** Bit definition for DAC_DHR12L2 register ******************/
1491 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!<DAC channel2 12-bit Left aligned data */
1493 /****************** Bit definition for DAC_DHR8R2 register ******************/
1494 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!<DAC channel2 8-bit Right aligned data */
1496 /***************** Bit definition for DAC_DHR12RD register ******************/
1497 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
1498 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
1500 /***************** Bit definition for DAC_DHR12LD register ******************/
1501 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
1502 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
1504 /****************** Bit definition for DAC_DHR8RD register ******************/
1505 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
1506 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!<DAC channel2 8-bit Right aligned data */
1508 /******************* Bit definition for DAC_DOR1 register *******************/
1509 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
1511 /******************* Bit definition for DAC_DOR2 register *******************/
1512 #define DAC_DOR2_DACC2DOR ((uint_t)0x00000FFF) /*!<DAC channel2 data output */
1514 /******************** Bit definition for DAC_SR register ********************/
1515 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
1516 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
1518 /******************************************************************************/
1520 /* Debug MCU (DBGMCU) */
1522 /******************************************************************************/
1524 /**************** Bit definition for DBGMCU_IDCODE register *****************/
1525 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
1527 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
1528 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1529 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1530 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
1531 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
1532 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
1533 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
1534 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
1535 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
1536 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
1537 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
1538 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
1539 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
1540 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
1541 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
1542 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
1543 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
1545 /****************** Bit definition for DBGMCU_CR register *******************/
1546 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
1547 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
1548 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
1549 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
1551 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
1552 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1553 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1555 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
1557 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
1558 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
1559 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
1560 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
1561 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
1562 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
1563 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
1564 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
1565 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
1566 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
1567 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
1569 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
1571 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
1572 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
1573 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
1575 /******************************************************************************/
1577 /* DMA Controller (DMA) */
1579 /******************************************************************************/
1581 /******************* Bit definition for DMA_ISR register ********************/
1582 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
1583 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
1584 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
1585 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
1586 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
1587 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
1588 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
1589 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
1590 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
1591 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
1592 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
1593 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
1594 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
1595 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
1596 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
1597 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
1598 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
1599 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
1600 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
1601 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
1602 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
1603 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
1604 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
1605 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
1606 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
1607 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
1608 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
1609 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
1611 /******************* Bit definition for DMA_IFCR register *******************/
1612 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
1613 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
1614 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
1615 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
1616 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
1617 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
1618 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
1619 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
1620 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
1621 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
1622 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
1623 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
1624 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
1625 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
1626 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
1627 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
1628 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
1629 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
1630 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
1631 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
1632 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
1633 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
1634 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
1635 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
1636 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
1637 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
1638 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
1639 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
1641 /******************* Bit definition for DMA_CCR register *******************/
1642 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable*/
1643 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
1644 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
1645 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
1646 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
1647 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
1648 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
1649 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
1651 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
1652 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1653 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1655 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
1656 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1657 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1659 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
1660 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1661 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1663 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
1665 /****************** Bit definition for DMA_CNDTR1 register ******************/
1666 #define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1668 /****************** Bit definition for DMA_CNDTR2 register ******************/
1669 #define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1671 /****************** Bit definition for DMA_CNDTR3 register ******************/
1672 #define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1674 /****************** Bit definition for DMA_CNDTR4 register ******************/
1675 #define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1677 /****************** Bit definition for DMA_CNDTR5 register ******************/
1678 #define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1680 /****************** Bit definition for DMA_CNDTR6 register ******************/
1681 #define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1683 /****************** Bit definition for DMA_CNDTR7 register ******************/
1684 #define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1686 /****************** Bit definition for DMA_CPAR1 register *******************/
1687 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1689 /****************** Bit definition for DMA_CPAR2 register *******************/
1690 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1692 /****************** Bit definition for DMA_CPAR3 register *******************/
1693 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1696 /****************** Bit definition for DMA_CPAR4 register *******************/
1697 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1699 /****************** Bit definition for DMA_CPAR5 register *******************/
1700 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1702 /****************** Bit definition for DMA_CPAR6 register *******************/
1703 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1706 /****************** Bit definition for DMA_CPAR7 register *******************/
1707 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1709 /****************** Bit definition for DMA_CMAR1 register *******************/
1710 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1712 /****************** Bit definition for DMA_CMAR2 register *******************/
1713 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1715 /****************** Bit definition for DMA_CMAR3 register *******************/
1716 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1719 /****************** Bit definition for DMA_CMAR4 register *******************/
1720 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1722 /****************** Bit definition for DMA_CMAR5 register *******************/
1723 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1725 /****************** Bit definition for DMA_CMAR6 register *******************/
1726 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1728 /****************** Bit definition for DMA_CMAR7 register *******************/
1729 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1731 /******************************************************************************/
1733 /* External Interrupt/Event Controller (EXTI) */
1735 /******************************************************************************/
1737 /******************* Bit definition for EXTI_IMR register *******************/
1738 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
1739 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
1740 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
1741 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
1742 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
1743 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
1744 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
1745 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
1746 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
1747 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
1748 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
1749 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
1750 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
1751 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
1752 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
1753 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
1754 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
1755 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
1756 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
1757 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
1758 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
1759 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
1760 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
1761 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
1763 /******************* Bit definition for EXTI_EMR register *******************/
1764 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
1765 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
1766 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
1767 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
1768 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
1769 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
1770 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
1771 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
1772 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
1773 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
1774 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
1775 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
1776 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
1777 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
1778 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
1779 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
1780 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
1781 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
1782 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
1783 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
1784 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
1785 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
1786 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
1787 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
1789 /****************** Bit definition for EXTI_RTSR register *******************/
1790 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
1791 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
1792 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
1793 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
1794 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
1795 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
1796 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
1797 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
1798 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
1799 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
1800 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
1801 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
1802 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
1803 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
1804 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
1805 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
1806 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
1807 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
1808 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
1809 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
1810 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
1811 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
1812 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
1813 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
1815 /****************** Bit definition for EXTI_FTSR register *******************/
1816 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
1817 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
1818 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
1819 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
1820 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
1821 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
1822 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
1823 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
1824 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
1825 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
1826 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
1827 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
1828 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
1829 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
1830 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
1831 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
1832 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
1833 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
1834 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
1835 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
1836 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
1837 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
1838 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
1839 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
1841 /****************** Bit definition for EXTI_SWIER register ******************/
1842 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
1843 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
1844 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
1845 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
1846 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
1847 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
1848 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
1849 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
1850 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
1851 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
1852 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
1853 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
1854 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
1855 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
1856 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
1857 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
1858 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
1859 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
1860 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
1861 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
1862 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
1863 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
1864 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
1865 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
1867 /******************* Bit definition for EXTI_PR register ********************/
1868 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
1869 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
1870 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
1871 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
1872 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
1873 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
1874 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
1875 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
1876 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
1877 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
1878 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
1879 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
1880 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
1881 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
1882 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
1883 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
1884 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
1885 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
1886 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
1887 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
1888 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
1889 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
1890 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
1891 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
1893 /******************************************************************************/
1895 /* FLASH, DATA EEPROM and Option Bytes Registers */
1896 /* (FLASH, DATA_EEPROM, OB) */
1898 /******************************************************************************/
1900 /******************* Bit definition for FLASH_ACR register ******************/
1901 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
1902 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
1903 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
1904 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
1905 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
1907 /******************* Bit definition for FLASH_PECR register ******************/
1908 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
1909 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
1910 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
1911 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
1912 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
1913 #define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
1914 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
1915 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
1916 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
1917 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
1918 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
1920 /****************** Bit definition for FLASH_PDKEYR register ******************/
1921 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1923 /****************** Bit definition for FLASH_PEKEYR register ******************/
1924 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1926 /****************** Bit definition for FLASH_PRGKEYR register ******************/
1927 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
1929 /****************** Bit definition for FLASH_OPTKEYR register ******************/
1930 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
1932 /****************** Bit definition for FLASH_SR register *******************/
1933 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
1934 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
1935 #define FLASH_SR_ENDHV ((uint32_t)0x00000004) /*!< End of high voltage */
1936 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
1938 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
1939 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
1940 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
1941 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
1942 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
1943 #define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
1945 /****************** Bit definition for FLASH_OBR register *******************/
1946 #define FLASH_OBR_RDPRT ((uint32_t)0x000000FF) /*!< Read Protection */
1947 #define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPRi bits */
1948 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
1949 #define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
1950 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
1951 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
1952 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
1954 /****************** Bit definition for FLASH_WRPR register ******************/
1955 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
1956 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
1958 /******************************************************************************/
1960 /* General Purpose I/O */
1962 /******************************************************************************/
1963 /****************** Bits definition for GPIO_MODER register *****************/
1964 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
1965 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
1966 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
1968 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
1969 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
1970 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
1972 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
1973 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
1974 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
1976 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
1977 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
1978 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
1980 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
1981 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
1982 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
1984 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
1985 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
1986 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
1988 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
1989 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
1990 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
1992 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
1993 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
1994 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
1996 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
1997 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
1998 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
2000 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
2001 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
2002 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
2004 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
2005 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
2006 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
2008 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
2009 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
2010 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
2012 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
2013 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
2014 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
2016 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
2017 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
2018 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
2020 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
2021 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
2022 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
2024 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
2025 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
2026 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
2028 /****************** Bits definition for GPIO_OTYPER register ****************/
2029 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
2030 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
2031 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
2032 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
2033 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
2034 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
2035 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
2036 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
2037 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
2038 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
2039 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
2040 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
2041 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
2042 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
2043 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
2044 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
2046 /****************** Bits definition for GPIO_OSPEEDR register ***************/
2047 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
2048 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
2049 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
2051 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
2052 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
2053 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
2055 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
2056 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
2057 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
2059 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
2060 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
2061 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
2063 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
2064 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
2065 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
2067 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
2068 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
2069 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
2071 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
2072 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
2073 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
2075 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
2076 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
2077 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
2079 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
2080 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
2081 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
2083 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
2084 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
2085 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
2087 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
2088 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
2089 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
2091 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
2092 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
2093 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
2095 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
2096 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
2097 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
2099 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
2100 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
2101 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
2103 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
2104 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
2105 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
2107 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
2108 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
2109 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
2111 /****************** Bits definition for GPIO_PUPDR register *****************/
2112 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
2113 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
2114 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
2116 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
2117 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
2118 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
2120 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
2121 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
2122 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
2124 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
2125 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
2126 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
2128 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
2129 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
2130 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
2132 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
2133 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
2134 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
2136 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
2137 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
2138 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
2140 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
2141 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
2142 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
2144 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
2145 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
2146 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
2148 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
2149 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
2150 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
2152 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
2153 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
2154 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
2156 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
2157 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
2158 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
2160 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
2161 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
2162 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
2164 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
2165 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
2166 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
2168 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
2169 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
2170 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
2171 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
2172 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
2173 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
2175 /****************** Bits definition for GPIO_IDR register *******************/
2176 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
2177 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
2178 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
2179 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
2180 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
2181 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
2182 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
2183 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
2184 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
2185 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
2186 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
2187 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
2188 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
2189 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
2190 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
2191 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
2193 /****************** Bits definition for GPIO_ODR register *******************/
2194 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
2195 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
2196 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
2197 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
2198 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
2199 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
2200 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
2201 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
2202 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
2203 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
2204 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
2205 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
2206 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
2207 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
2208 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
2209 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
2211 /****************** Bits definition for GPIO_BSRR register ******************/
2212 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
2213 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
2214 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
2215 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
2216 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
2217 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
2218 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
2219 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
2220 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
2221 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
2222 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
2223 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
2224 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
2225 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
2226 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
2227 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
2228 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
2229 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
2230 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
2231 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
2232 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
2233 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
2234 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
2235 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
2236 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
2237 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
2238 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
2239 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
2240 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
2241 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
2242 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
2243 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
2245 /****************** Bit definition for GPIO_LCKR register ********************/
2246 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
2247 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
2248 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
2249 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
2250 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
2251 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
2252 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
2253 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
2254 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
2255 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
2256 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
2257 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
2258 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
2259 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
2260 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
2261 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
2262 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
2264 /****************** Bit definition for GPIO_AFRL register ********************/
2265 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
2266 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
2267 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
2268 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
2269 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
2270 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
2271 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
2272 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
2274 /****************** Bit definition for GPIO_AFRH register ********************/
2275 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
2276 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
2277 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
2278 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
2279 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
2280 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
2281 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
2282 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
2284 /****************** Bit definition for GPIO_BRR register *********************/
2285 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
2286 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
2287 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
2288 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
2289 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
2290 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
2291 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
2292 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
2293 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
2294 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
2295 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
2296 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
2297 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
2298 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
2299 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
2300 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
2303 /******************************************************************************/
2305 /* Inter-integrated Circuit Interface (I2C) */
2307 /******************************************************************************/
2309 /******************* Bit definition for I2C_CR1 register ********************/
2310 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
2311 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
2312 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
2313 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
2314 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
2315 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
2316 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
2317 #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
2318 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
2319 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
2320 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
2321 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
2322 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
2323 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
2325 /******************* Bit definition for I2C_CR2 register ********************/
2326 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
2327 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2328 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2329 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
2330 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
2331 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
2332 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
2334 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
2335 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
2336 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
2337 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
2338 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
2340 /******************* Bit definition for I2C_OAR1 register *******************/
2341 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
2342 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
2344 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
2345 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
2346 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
2347 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
2348 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
2349 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
2350 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
2351 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
2352 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
2353 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
2355 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
2357 /******************* Bit definition for I2C_OAR2 register *******************/
2358 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
2359 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
2361 /******************** Bit definition for I2C_DR register ********************/
2362 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!< 8-bit Data Register */
2364 /******************* Bit definition for I2C_SR1 register ********************/
2365 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
2366 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
2367 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
2368 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
2369 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
2370 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
2371 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
2372 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
2373 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
2374 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
2375 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
2376 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
2377 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
2378 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
2380 /******************* Bit definition for I2C_SR2 register ********************/
2381 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
2382 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
2383 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
2384 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
2385 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
2386 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
2387 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
2388 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
2390 /******************* Bit definition for I2C_CCR register ********************/
2391 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
2392 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
2393 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
2395 /****************** Bit definition for I2C_TRISE register *******************/
2396 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
2398 /******************************************************************************/
2400 /* Independent WATCHDOG (IWDG) */
2402 /******************************************************************************/
2404 /******************* Bit definition for IWDG_KR register ********************/
2405 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
2407 /******************* Bit definition for IWDG_PR register ********************/
2408 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
2409 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2410 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2411 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
2413 /******************* Bit definition for IWDG_RLR register *******************/
2414 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
2416 /******************* Bit definition for IWDG_SR register ********************/
2417 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
2418 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
2420 /******************************************************************************/
2422 /* LCD Controller (LCD) */
2424 /******************************************************************************/
2426 /******************* Bit definition for LCD_CR register *********************/
2427 #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
2428 #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
2430 #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
2431 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
2432 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
2433 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
2435 #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
2436 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
2437 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
2439 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
2441 /******************* Bit definition for LCD_FCR register ********************/
2442 #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
2443 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
2444 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
2446 #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
2447 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2448 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2449 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
2451 #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
2452 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
2453 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
2454 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
2456 #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
2457 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
2458 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
2459 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
2461 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
2462 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
2463 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
2464 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
2466 #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
2467 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2468 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2470 #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
2471 #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
2473 /******************* Bit definition for LCD_SR register *********************/
2474 #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
2475 #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
2476 #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
2477 #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
2478 #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
2479 #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
2481 /******************* Bit definition for LCD_CLR register ********************/
2482 #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
2483 #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
2485 /******************* Bit definition for LCD_RAM register ********************/
2486 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
2488 /******************************************************************************/
2490 /* Power Control (PWR) */
2492 /******************************************************************************/
2494 /******************** Bit definition for PWR_CR register ********************/
2495 #define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
2496 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
2497 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
2498 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
2499 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
2501 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
2502 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2503 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2504 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
2506 /*!< PVD level configuration */
2507 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
2508 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
2509 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
2510 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
2511 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
2512 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
2513 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
2514 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
2516 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
2517 #define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
2518 #define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
2520 #define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
2521 #define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2522 #define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2523 #define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
2525 /******************* Bit definition for PWR_CSR register ********************/
2526 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
2527 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
2528 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
2529 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
2530 #define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
2531 #define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
2533 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
2534 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
2535 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
2537 /******************************************************************************/
2539 /* Reset and Clock Control (RCC) */
2541 /******************************************************************************/
2542 /******************** Bit definition for RCC_CR register ********************/
2543 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
2544 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
2546 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
2547 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
2549 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
2550 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
2551 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
2553 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
2554 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
2555 #define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
2557 #define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
2558 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
2559 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
2561 /******************** Bit definition for RCC_ICSCR register *****************/
2562 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
2563 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
2565 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
2566 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
2567 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
2568 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
2569 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
2570 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
2571 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
2572 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
2573 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
2574 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
2576 /******************** Bit definition for RCC_CFGR register ******************/
2577 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
2578 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2579 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2581 /*!< SW configuration */
2582 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
2583 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
2584 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
2585 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
2587 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
2588 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2589 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2591 /*!< SWS configuration */
2592 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
2593 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
2594 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
2595 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
2597 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
2598 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2599 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2600 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
2601 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
2603 /*!< HPRE configuration */
2604 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
2605 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
2606 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
2607 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
2608 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
2609 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
2610 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
2611 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
2612 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
2614 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
2615 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2616 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2617 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2619 /*!< PPRE1 configuration */
2620 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2621 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
2622 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
2623 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
2624 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
2626 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
2627 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2628 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2629 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
2631 /*!< PPRE2 configuration */
2632 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2633 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
2634 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
2635 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
2636 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
2638 /*!< PLL entry clock source*/
2639 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
2641 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
2642 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
2645 /*!< PLLMUL configuration */
2646 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
2647 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2648 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2649 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
2650 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
2652 /*!< PLLMUL configuration */
2653 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
2654 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
2655 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
2656 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
2657 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
2658 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
2659 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
2660 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
2661 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
2663 /*!< PLLDIV configuration */
2664 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
2665 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
2666 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
2669 /*!< PLLDIV configuration */
2670 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
2671 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
2672 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
2673 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
2676 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
2677 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2678 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2679 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
2681 /*!< MCO configuration */
2682 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2683 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
2684 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
2685 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
2686 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
2687 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
2688 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
2689 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
2691 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
2692 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
2693 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
2694 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
2696 /*!< MCO Prescaler configuration */
2697 #define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
2698 #define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
2699 #define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
2700 #define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
2701 #define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
2703 /*!<****************** Bit definition for RCC_CIR register ********************/
2704 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
2705 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
2706 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
2707 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
2708 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
2709 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
2710 #define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */
2711 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
2713 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
2714 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
2715 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
2716 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
2717 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
2718 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
2719 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */
2721 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
2722 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
2723 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
2724 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
2725 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
2726 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
2727 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */
2728 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
2730 /***************** Bit definition for RCC_AHBRSTR register ******************/
2731 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
2732 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
2733 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
2734 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
2735 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
2736 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
2737 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
2738 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
2739 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
2740 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */
2742 /***************** Bit definition for RCC_APB2RSTR register *****************/
2743 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
2744 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
2745 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
2746 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
2747 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
2748 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
2749 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
2751 /***************** Bit definition for RCC_APB1RSTR register *****************/
2752 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
2753 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
2754 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
2755 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
2756 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
2757 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
2758 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
2759 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
2760 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
2761 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
2762 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
2763 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
2764 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
2765 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
2766 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
2767 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
2768 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
2769 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
2771 /****************** Bit definition for RCC_AHBENR register ******************/
2772 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
2773 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
2774 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
2775 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
2776 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
2777 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
2778 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
2779 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
2780 the Flash memory is in power down mode) */
2781 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
2782 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */
2784 /****************** Bit definition for RCC_APB2ENR register *****************/
2785 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
2786 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
2787 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
2788 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
2789 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
2790 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
2791 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
2793 /***************** Bit definition for RCC_APB1ENR register ******************/
2794 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
2795 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
2796 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
2797 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
2798 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
2799 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
2800 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
2801 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
2802 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
2803 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
2804 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
2805 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
2806 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
2807 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
2808 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
2809 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
2810 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
2811 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
2813 /****************** Bit definition for RCC_AHBLPENR register ****************/
2814 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
2815 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
2816 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
2817 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
2818 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
2819 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
2820 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
2821 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
2822 (has effect only when the Flash memory is
2823 in power down mode) */
2824 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
2825 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
2826 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */
2828 /****************** Bit definition for RCC_APB2LPENR register ***************/
2829 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
2830 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
2831 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
2832 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
2833 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
2834 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
2835 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
2837 /***************** Bit definition for RCC_APB1LPENR register ****************/
2838 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
2839 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
2840 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
2841 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */
2842 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
2843 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
2844 #define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
2845 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
2846 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
2847 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */
2848 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
2849 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
2850 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
2851 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
2852 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
2853 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
2854 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
2855 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
2857 /******************* Bit definition for RCC_CSR register ********************/
2858 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
2859 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
2861 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
2862 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
2863 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
2865 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */
2866 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */
2868 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
2869 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2870 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2872 /*!< RTC congiguration */
2873 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2874 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
2875 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
2876 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
2878 #define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
2879 #define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
2881 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
2882 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
2883 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
2884 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
2885 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
2886 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
2887 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
2888 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
2890 /******************************************************************************/
2892 /* Real-Time Clock (RTC) */
2894 /******************************************************************************/
2895 /******************** Bits definition for RTC_TR register *******************/
2896 #define RTC_TR_PM ((uint32_t)0x00400000)
2897 #define RTC_TR_HT ((uint32_t)0x00300000)
2898 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
2899 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
2900 #define RTC_TR_HU ((uint32_t)0x000F0000)
2901 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
2902 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
2903 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
2904 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
2905 #define RTC_TR_MNT ((uint32_t)0x00007000)
2906 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
2907 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
2908 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
2909 #define RTC_TR_MNU ((uint32_t)0x00000F00)
2910 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
2911 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
2912 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
2913 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
2914 #define RTC_TR_ST ((uint32_t)0x00000070)
2915 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
2916 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
2917 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
2918 #define RTC_TR_SU ((uint32_t)0x0000000F)
2919 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
2920 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
2921 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
2922 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
2924 /******************** Bits definition for RTC_DR register *******************/
2925 #define RTC_DR_YT ((uint32_t)0x00F00000)
2926 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
2927 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
2928 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
2929 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
2930 #define RTC_DR_YU ((uint32_t)0x000F0000)
2931 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
2932 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
2933 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
2934 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
2935 #define RTC_DR_WDU ((uint32_t)0x0000E000)
2936 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
2937 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
2938 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
2939 #define RTC_DR_MT ((uint32_t)0x00001000)
2940 #define RTC_DR_MU ((uint32_t)0x00000F00)
2941 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
2942 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
2943 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
2944 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
2945 #define RTC_DR_DT ((uint32_t)0x00000030)
2946 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
2947 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
2948 #define RTC_DR_DU ((uint32_t)0x0000000F)
2949 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
2950 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
2951 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
2952 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
2954 /******************** Bits definition for RTC_CR register *******************/
2955 #define RTC_CR_COE ((uint32_t)0x00800000)
2956 #define RTC_CR_OSEL ((uint32_t)0x00600000)
2957 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
2958 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
2959 #define RTC_CR_POL ((uint32_t)0x00100000)
2960 #define RTC_CR_COSEL ((uint32_t)0x00080000)
2961 #define RTC_CR_BCK ((uint32_t)0x00040000)
2962 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
2963 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
2964 #define RTC_CR_TSIE ((uint32_t)0x00008000)
2965 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
2966 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
2967 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
2968 #define RTC_CR_TSE ((uint32_t)0x00000800)
2969 #define RTC_CR_WUTE ((uint32_t)0x00000400)
2970 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
2971 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
2972 #define RTC_CR_DCE ((uint32_t)0x00000080)
2973 #define RTC_CR_FMT ((uint32_t)0x00000040)
2974 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
2975 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
2976 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
2977 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
2978 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
2979 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
2980 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
2982 /******************** Bits definition for RTC_ISR register ******************/
2983 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
2984 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
2985 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
2986 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
2987 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
2988 #define RTC_ISR_TSF ((uint32_t)0x00000800)
2989 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
2990 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
2991 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
2992 #define RTC_ISR_INIT ((uint32_t)0x00000080)
2993 #define RTC_ISR_INITF ((uint32_t)0x00000040)
2994 #define RTC_ISR_RSF ((uint32_t)0x00000020)
2995 #define RTC_ISR_INITS ((uint32_t)0x00000010)
2996 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
2997 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
2998 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
2999 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
3001 /******************** Bits definition for RTC_PRER register *****************/
3002 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
3003 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
3005 /******************** Bits definition for RTC_WUTR register *****************/
3006 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
3008 /******************** Bits definition for RTC_CALIBR register ***************/
3009 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
3010 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
3012 /******************** Bits definition for RTC_ALRMAR register ***************/
3013 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
3014 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
3015 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
3016 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
3017 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
3018 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
3019 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
3020 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
3021 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
3022 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
3023 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
3024 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
3025 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
3026 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
3027 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
3028 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
3029 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
3030 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
3031 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
3032 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
3033 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
3034 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
3035 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
3036 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
3037 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
3038 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
3039 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
3040 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
3041 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
3042 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
3043 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
3044 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
3045 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
3046 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
3047 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
3048 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
3049 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
3050 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
3051 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
3052 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
3054 /******************** Bits definition for RTC_ALRMBR register ***************/
3055 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
3056 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
3057 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
3058 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
3059 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
3060 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
3061 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
3062 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
3063 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
3064 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
3065 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
3066 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
3067 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
3068 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
3069 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
3070 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
3071 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
3072 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
3073 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
3074 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
3075 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
3076 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
3077 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
3078 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
3079 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
3080 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
3081 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
3082 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
3083 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
3084 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
3085 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
3086 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
3087 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
3088 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
3089 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
3090 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
3091 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
3092 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
3093 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
3094 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
3096 /******************** Bits definition for RTC_WPR register ******************/
3097 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
3099 /******************** Bits definition for RTC_SSR register ******************/
3100 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
3102 /******************** Bits definition for RTC_SHIFTR register ***************/
3103 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
3104 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
3106 /******************** Bits definition for RTC_TSTR register *****************/
3107 #define RTC_TSTR_PM ((uint32_t)0x00400000)
3108 #define RTC_TSTR_HT ((uint32_t)0x00300000)
3109 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
3110 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
3111 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
3112 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
3113 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
3114 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
3115 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
3116 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
3117 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
3118 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
3119 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
3120 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
3121 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
3122 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
3123 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
3124 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
3125 #define RTC_TSTR_ST ((uint32_t)0x00000070)
3126 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
3127 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
3128 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
3129 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
3130 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
3131 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
3132 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
3133 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
3135 /******************** Bits definition for RTC_TSDR register *****************/
3136 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
3137 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
3138 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
3139 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
3140 #define RTC_TSDR_MT ((uint32_t)0x00001000)
3141 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
3142 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
3143 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
3144 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
3145 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
3146 #define RTC_TSDR_DT ((uint32_t)0x00000030)
3147 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
3148 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
3149 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
3150 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
3151 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
3152 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
3153 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
3155 /******************** Bits definition for RTC_TSSSR register ****************/
3156 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
3158 /******************** Bits definition for RTC_CAL register *****************/
3159 #define RTC_CALR_CALP ((uint32_t)0x00008000)
3160 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
3161 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
3162 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
3163 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
3164 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
3165 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
3166 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
3167 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
3168 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
3169 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
3170 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
3171 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
3173 /******************** Bits definition for RTC_TAFCR register ****************/
3174 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
3175 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
3176 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
3177 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
3178 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
3179 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
3180 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
3181 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
3182 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
3183 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
3184 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
3185 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
3186 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
3187 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
3188 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
3189 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
3190 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
3191 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
3192 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
3193 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
3195 /******************** Bits definition for RTC_ALRMASSR register *************/
3196 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
3197 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
3198 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
3199 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
3200 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
3201 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
3203 /******************** Bits definition for RTC_ALRMBSSR register *************/
3204 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
3205 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
3206 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
3207 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
3208 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
3209 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
3211 /******************** Bits definition for RTC_BKP0R register ****************/
3212 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
3214 /******************** Bits definition for RTC_BKP1R register ****************/
3215 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
3217 /******************** Bits definition for RTC_BKP2R register ****************/
3218 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
3220 /******************** Bits definition for RTC_BKP3R register ****************/
3221 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
3223 /******************** Bits definition for RTC_BKP4R register ****************/
3224 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
3226 /******************** Bits definition for RTC_BKP5R register ****************/
3227 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
3229 /******************** Bits definition for RTC_BKP6R register ****************/
3230 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
3232 /******************** Bits definition for RTC_BKP7R register ****************/
3233 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
3235 /******************** Bits definition for RTC_BKP8R register ****************/
3236 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
3238 /******************** Bits definition for RTC_BKP9R register ****************/
3239 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
3241 /******************** Bits definition for RTC_BKP10R register ***************/
3242 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
3244 /******************** Bits definition for RTC_BKP11R register ***************/
3245 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
3247 /******************** Bits definition for RTC_BKP12R register ***************/
3248 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
3250 /******************** Bits definition for RTC_BKP13R register ***************/
3251 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
3253 /******************** Bits definition for RTC_BKP14R register ***************/
3254 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
3256 /******************** Bits definition for RTC_BKP15R register ***************/
3257 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
3259 /******************** Bits definition for RTC_BKP16R register ***************/
3260 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
3262 /******************** Bits definition for RTC_BKP17R register ***************/
3263 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
3265 /******************** Bits definition for RTC_BKP18R register ***************/
3266 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
3268 /******************** Bits definition for RTC_BKP19R register ***************/
3269 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
3271 /******************** Bits definition for RTC_BKP20R register ***************/
3272 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
3274 /******************** Bits definition for RTC_BKP21R register ***************/
3275 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
3277 /******************** Bits definition for RTC_BKP22R register ***************/
3278 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
3280 /******************** Bits definition for RTC_BKP23R register ***************/
3281 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
3283 /******************** Bits definition for RTC_BKP24R register ***************/
3284 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
3286 /******************** Bits definition for RTC_BKP25R register ***************/
3287 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
3289 /******************** Bits definition for RTC_BKP26R register ***************/
3290 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
3292 /******************** Bits definition for RTC_BKP27R register ***************/
3293 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
3295 /******************** Bits definition for RTC_BKP28R register ***************/
3296 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
3298 /******************** Bits definition for RTC_BKP29R register ***************/
3299 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
3301 /******************** Bits definition for RTC_BKP30R register ***************/
3302 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
3304 /******************** Bits definition for RTC_BKP31R register ***************/
3305 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
3307 /******************** Number of backup registers ******************************/
3308 #define RTC_BKP_NUMBER 32
3310 /******************************************************************************/
3312 /* Serial Peripheral Interface (SPI) */
3314 /******************************************************************************/
3316 /******************* Bit definition for SPI_CR1 register ********************/
3317 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
3318 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
3319 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
3321 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
3322 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
3323 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
3324 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
3326 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
3327 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
3328 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
3329 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
3330 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
3331 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
3332 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
3333 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
3334 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
3335 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
3337 /******************* Bit definition for SPI_CR2 register ********************/
3338 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
3339 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
3340 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
3341 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame format */
3342 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
3343 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
3344 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
3346 /******************** Bit definition for SPI_SR register ********************/
3347 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
3348 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
3349 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
3350 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
3351 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
3352 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
3353 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
3354 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
3355 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
3357 /******************** Bit definition for SPI_DR register ********************/
3358 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
3360 /******************* Bit definition for SPI_CRCPR register ******************/
3361 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
3363 /****************** Bit definition for SPI_RXCRCR register ******************/
3364 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
3366 /****************** Bit definition for SPI_TXCRCR register ******************/
3367 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
3369 /****************** Bit definition for SPI_I2SCFGR register *****************/
3370 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
3372 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
3373 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
3374 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
3376 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
3378 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
3379 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3380 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3382 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
3384 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
3385 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3386 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3388 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
3389 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
3391 /****************** Bit definition for SPI_I2SPR register *******************/
3392 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
3393 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
3394 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
3396 /******************************************************************************/
3398 /* System Configuration (SYSCFG) */
3400 /******************************************************************************/
3401 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
3402 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
3403 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3404 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3405 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */
3406 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3407 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3409 /***************** Bit definition for SYSCFG_PMC register *******************/
3410 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
3412 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
3413 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
3414 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
3415 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
3416 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
3419 * @brief EXTI0 configuration
3421 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
3422 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
3423 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
3424 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
3425 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
3426 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
3427 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006) /*!< PF[0] pin */
3428 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007) /*!< PG[0] pin */
3431 * @brief EXTI1 configuration
3433 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
3434 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
3435 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
3436 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
3437 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
3438 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
3439 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060) /*!< PF[1] pin */
3440 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070) /*!< PG[1] pin */
3443 * @brief EXTI2 configuration
3445 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
3446 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
3447 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
3448 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
3449 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
3450 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500) /*!< PH[2] pin */
3451 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600) /*!< PF[2] pin */
3452 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700) /*!< PG[2] pin */
3455 * @brief EXTI3 configuration
3457 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
3458 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
3459 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
3460 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
3461 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
3462 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000) /*!< PF[3] pin */
3463 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000) /*!< PG[3] pin */
3465 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
3466 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
3467 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
3468 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
3469 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
3472 * @brief EXTI4 configuration
3474 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
3475 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
3476 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
3477 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
3478 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
3479 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006) /*!< PF[4] pin */
3480 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007) /*!< PG[4] pin */
3483 * @brief EXTI5 configuration
3485 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
3486 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
3487 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
3488 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
3489 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
3490 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060) /*!< PF[5] pin */
3491 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070) /*!< PG[5] pin */
3494 * @brief EXTI6 configuration
3496 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
3497 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
3498 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
3499 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
3500 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
3501 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600) /*!< PF[6] pin */
3502 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700) /*!< PG[6] pin */
3505 * @brief EXTI7 configuration
3507 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
3508 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
3509 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
3510 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
3511 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
3512 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000) /*!< PF[7] pin */
3513 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000) /*!< PG[7] pin */
3515 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
3516 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
3517 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
3518 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
3519 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
3522 * @brief EXTI8 configuration
3524 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
3525 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
3526 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
3527 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
3528 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
3529 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006) /*!< PF[8] pin */
3530 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007) /*!< PG[8] pin */
3533 * @brief EXTI9 configuration
3535 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
3536 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
3537 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
3538 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
3539 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
3540 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060) /*!< PF[9] pin */
3541 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070) /*!< PG[9] pin */
3544 * @brief EXTI10 configuration
3546 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
3547 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
3548 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
3549 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
3550 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
3551 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600) /*!< PF[10] pin */
3552 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700) /*!< PG[10] pin */
3555 * @brief EXTI11 configuration
3557 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
3558 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
3559 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
3560 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
3561 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
3562 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000) /*!< PF[11] pin */
3563 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000) /*!< PG[11] pin */
3565 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
3566 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
3567 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
3568 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
3569 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
3572 * @brief EXTI12 configuration
3574 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
3575 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
3576 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
3577 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
3578 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
3579 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006) /*!< PF[12] pin */
3580 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007) /*!< PG[12] pin */
3583 * @brief EXTI13 configuration
3585 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
3586 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
3587 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
3588 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
3589 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
3590 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060) /*!< PF[13] pin */
3591 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070) /*!< PG[13] pin */
3594 * @brief EXTI14 configuration
3596 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
3597 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
3598 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
3599 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
3600 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
3601 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600) /*!< PF[14] pin */
3602 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700) /*!< PG[14] pin */
3605 * @brief EXTI15 configuration
3607 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
3608 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
3609 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
3610 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
3611 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
3612 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000) /*!< PF[15] pin */
3613 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000) /*!< PG[15] pin */
3615 /******************************************************************************/
3617 /* Routing Interface (RI) */
3619 /******************************************************************************/
3621 /******************** Bit definition for RI_ICR register ********************/
3622 #define RI_ICR_IC1OS ((uint32_t)0x0000000F) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
3623 #define RI_ICR_IC1OS_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3624 #define RI_ICR_IC1OS_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3625 #define RI_ICR_IC1OS_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3626 #define RI_ICR_IC1OS_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3628 #define RI_ICR_IC2OS ((uint32_t)0x000000F0) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
3629 #define RI_ICR_IC2OS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
3630 #define RI_ICR_IC2OS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
3631 #define RI_ICR_IC2OS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
3632 #define RI_ICR_IC2OS_3 ((uint32_t)0x00000080) /*!< Bit 3 */
3634 #define RI_ICR_IC3OS ((uint32_t)0x00000F00) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
3635 #define RI_ICR_IC3OS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3636 #define RI_ICR_IC3OS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3637 #define RI_ICR_IC3OS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
3638 #define RI_ICR_IC3OS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
3640 #define RI_ICR_IC4OS ((uint32_t)0x0000F000) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
3641 #define RI_ICR_IC4OS_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3642 #define RI_ICR_IC4OS_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3643 #define RI_ICR_IC4OS_2 ((uint32_t)0x00004000) /*!< Bit 2 */
3644 #define RI_ICR_IC4OS_3 ((uint32_t)0x00008000) /*!< Bit 3 */
3646 #define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
3647 #define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3648 #define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3650 #define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
3651 #define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
3652 #define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
3653 #define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
3655 /******************** Bit definition for RI_ASCR1 register ********************/
3656 #define RI_ASCR1_CH ((uint32_t)0x7BFDFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
3657 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3658 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3659 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3660 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3661 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3662 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3663 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3664 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3665 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3666 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3667 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3668 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3669 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3670 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3671 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3672 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3673 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */
3674 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
3675 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
3676 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
3677 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
3678 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
3679 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
3680 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
3681 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
3682 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
3683 #define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */
3684 #define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */
3685 #define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */
3686 #define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */
3687 #define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
3689 /******************** Bit definition for RI_ASCR2 register ********************/
3690 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
3691 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
3692 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
3693 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
3694 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
3695 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
3696 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
3697 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
3698 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
3699 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
3700 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
3701 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
3702 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
3703 #define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */
3704 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
3705 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
3707 /******************** Bit definition for RI_HYSCR1 register ********************/
3708 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
3709 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3710 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3711 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3712 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3713 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3714 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3715 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3716 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3717 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3718 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3719 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3720 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3721 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3722 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3723 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3724 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3726 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
3727 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3728 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3729 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3730 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3731 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3732 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
3733 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
3734 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
3735 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
3736 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
3737 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
3738 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
3739 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
3740 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
3741 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
3742 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
3744 /******************** Bit definition for RI_HYSCR2 register ********************/
3745 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
3746 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3747 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3748 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3749 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3750 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3751 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3752 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3753 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3754 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3755 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3756 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3757 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3758 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3759 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3760 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3761 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3763 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
3764 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3765 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3766 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3767 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3768 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3769 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
3770 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
3771 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
3772 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
3773 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
3774 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
3775 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
3776 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
3777 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
3778 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
3779 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
3781 /******************** Bit definition for RI_HYSCR3 register ********************/
3782 #define RI_HYSCR3_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
3783 #define RI_HYSCR3_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3784 #define RI_HYSCR3_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3785 #define RI_HYSCR3_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3786 #define RI_HYSCR3_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3787 #define RI_HYSCR3_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3788 #define RI_HYSCR3_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3789 #define RI_HYSCR3_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3790 #define RI_HYSCR3_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3791 #define RI_HYSCR3_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3792 #define RI_HYSCR3_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3793 #define RI_HYSCR3_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3794 #define RI_HYSCR3_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3795 #define RI_HYSCR3_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3796 #define RI_HYSCR3_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3797 #define RI_HYSCR3_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3798 #define RI_HYSCR3_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3800 /******************** Bit definition for RI_ASMR1 register ********************/
3801 #define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
3802 #define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3803 #define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3804 #define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3805 #define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3806 #define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3807 #define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3808 #define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3809 #define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3810 #define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3811 #define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3812 #define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3813 #define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3814 #define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3815 #define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3816 #define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3817 #define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3819 /******************** Bit definition for RI_CMR1 register ********************/
3820 #define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
3821 #define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3822 #define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3823 #define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3824 #define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3825 #define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3826 #define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3827 #define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3828 #define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3829 #define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3830 #define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3831 #define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3832 #define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3833 #define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3834 #define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3835 #define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3836 #define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3838 /******************** Bit definition for RI_CICR1 register ********************/
3839 #define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
3840 #define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3841 #define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3842 #define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3843 #define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3844 #define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3845 #define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3846 #define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3847 #define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3848 #define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3849 #define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3850 #define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3851 #define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3852 #define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3853 #define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3854 #define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3855 #define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3857 /******************** Bit definition for RI_ASMR2 register ********************/
3858 #define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
3859 #define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3860 #define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3861 #define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3862 #define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3863 #define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3864 #define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3865 #define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3866 #define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3867 #define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3868 #define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3869 #define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3870 #define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3871 #define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3872 #define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3873 #define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3874 #define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3876 /******************** Bit definition for RI_CMR2 register ********************/
3877 #define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
3878 #define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3879 #define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3880 #define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3881 #define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3882 #define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3883 #define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3884 #define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3885 #define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3886 #define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3887 #define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3888 #define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3889 #define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3890 #define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3891 #define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3892 #define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3893 #define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3895 /******************** Bit definition for RI_CICR2 register ********************/
3896 #define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
3897 #define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3898 #define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3899 #define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3900 #define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3901 #define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3902 #define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3903 #define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3904 #define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3905 #define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3906 #define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3907 #define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3908 #define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3909 #define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3910 #define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3911 #define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3912 #define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3914 /******************** Bit definition for RI_ASMR3 register ********************/
3915 #define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
3916 #define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3917 #define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3918 #define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3919 #define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3920 #define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3921 #define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3922 #define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3923 #define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3924 #define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3925 #define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3926 #define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3927 #define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3928 #define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3929 #define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3930 #define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3931 #define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3933 /******************** Bit definition for RI_CMR3 register ********************/
3934 #define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
3935 #define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3936 #define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3937 #define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3938 #define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3939 #define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3940 #define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3941 #define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3942 #define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3943 #define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3944 #define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3945 #define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3946 #define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3947 #define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3948 #define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3949 #define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3950 #define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3952 /******************** Bit definition for RI_CICR3 register ********************/
3953 #define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
3954 #define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3955 #define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3956 #define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3957 #define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3958 #define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3959 #define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3960 #define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3961 #define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3962 #define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3963 #define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3964 #define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3965 #define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3966 #define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3967 #define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3968 #define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3969 #define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3971 /******************************************************************************/
3975 /******************************************************************************/
3977 /******************* Bit definition for TIM_CR1 register ********************/
3978 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
3979 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
3980 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
3981 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
3982 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
3984 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
3985 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3986 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3988 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
3990 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
3991 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3992 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3994 /******************* Bit definition for TIM_CR2 register ********************/
3995 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
3997 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
3998 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3999 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4000 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4002 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
4004 /******************* Bit definition for TIM_SMCR register *******************/
4005 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
4006 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4007 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4008 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4010 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
4012 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
4013 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4014 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4015 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4017 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
4019 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
4020 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4021 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4022 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4023 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4025 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
4026 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4027 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4029 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
4030 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
4032 /******************* Bit definition for TIM_DIER register *******************/
4033 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
4034 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
4035 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
4036 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
4037 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
4038 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
4039 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
4040 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
4041 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
4042 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
4043 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
4044 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
4045 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
4047 /******************** Bit definition for TIM_SR register ********************/
4048 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
4049 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
4050 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
4051 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
4052 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
4053 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
4054 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
4055 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
4056 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
4057 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
4059 /******************* Bit definition for TIM_EGR register ********************/
4060 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
4061 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
4062 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
4063 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
4064 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
4065 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
4067 /****************** Bit definition for TIM_CCMR1 register *******************/
4068 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4069 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4070 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4072 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
4073 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
4075 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4076 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4077 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4078 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4080 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
4082 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4083 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4084 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4086 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
4087 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
4089 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4090 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4091 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4092 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4094 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
4096 /*----------------------------------------------------------------------------*/
4098 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4099 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4100 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4102 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4103 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4104 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4105 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4106 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4108 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4109 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4110 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4112 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4113 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4114 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4115 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4116 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
4118 /****************** Bit definition for TIM_CCMR2 register *******************/
4119 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4120 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4121 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4123 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
4124 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
4126 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4127 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4128 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4129 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4131 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
4133 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4134 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4135 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4137 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
4138 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
4140 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4141 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4142 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4143 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4145 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
4147 /*----------------------------------------------------------------------------*/
4149 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4150 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4151 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4153 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4154 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4155 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4156 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4157 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4159 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4160 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4161 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4163 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4164 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4165 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4166 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4167 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
4169 /******************* Bit definition for TIM_CCER register *******************/
4170 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
4171 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
4172 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
4173 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
4174 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
4175 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
4176 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
4177 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
4178 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
4179 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
4180 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
4181 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
4183 /******************* Bit definition for TIM_CNT register ********************/
4184 #define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
4186 /******************* Bit definition for TIM_PSC register ********************/
4187 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
4189 /******************* Bit definition for TIM_ARR register ********************/
4190 #define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
4192 /******************* Bit definition for TIM_CCR1 register *******************/
4193 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
4195 /******************* Bit definition for TIM_CCR2 register *******************/
4196 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
4198 /******************* Bit definition for TIM_CCR3 register *******************/
4199 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
4201 /******************* Bit definition for TIM_CCR4 register *******************/
4202 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
4204 /******************* Bit definition for TIM_DCR register ********************/
4205 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
4206 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4207 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4208 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4209 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4210 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4212 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
4213 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4214 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4215 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4216 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4217 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4219 /******************* Bit definition for TIM_DMAR register *******************/
4220 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
4222 /******************* Bit definition for TIM_OR register *********************/
4223 #define TIM_OR_TI1RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
4224 #define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4225 #define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4227 #define TIM_OR_ETR_RMP ((uint32_t)0x00000004) /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
4228 #define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008) /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
4230 /*----------------------------------------------------------------------------*/
4231 #define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004) /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
4233 /*----------------------------------------------------------------------------*/
4234 #define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001) /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
4236 /*----------------------------------------------------------------------------*/
4237 #define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001) /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
4239 /*----------------------------------------------------------------------------*/
4242 /******************************************************************************/
4244 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
4246 /******************************************************************************/
4248 /******************* Bit definition for USART_SR register *******************/
4249 #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
4250 #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
4251 #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
4252 #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
4253 #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
4254 #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
4255 #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
4256 #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
4257 #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
4258 #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
4260 /******************* Bit definition for USART_DR register *******************/
4261 #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
4263 /****************** Bit definition for USART_BRR register *******************/
4264 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
4265 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
4267 /****************** Bit definition for USART_CR1 register *******************/
4268 #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
4269 #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
4270 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
4271 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
4272 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
4273 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
4274 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
4275 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
4276 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
4277 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
4278 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
4279 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
4280 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
4281 #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
4282 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit mode */
4284 /****************** Bit definition for USART_CR2 register *******************/
4285 #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
4286 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
4287 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
4288 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
4289 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
4290 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
4291 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
4293 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
4294 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
4295 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
4297 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
4299 /****************** Bit definition for USART_CR3 register *******************/
4300 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
4301 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
4302 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
4303 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
4304 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
4305 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
4306 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
4307 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
4308 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
4309 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
4310 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
4311 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
4313 /****************** Bit definition for USART_GTPR register ******************/
4314 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
4315 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4316 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4317 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4318 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4319 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4320 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4321 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4322 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4324 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
4326 /******************************************************************************/
4328 /* Universal Serial Bus (USB) */
4330 /******************************************************************************/
4332 /*!<Endpoint-specific registers */
4334 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
4335 #define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
4336 #define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
4337 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
4338 #define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
4339 #define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
4340 #define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
4341 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
4344 #define USB_EP_CTR_RX ((uint32_t)0x00008000) /*!< EndPoint Correct TRansfer RX */
4345 #define USB_EP_DTOG_RX ((uint32_t)0x00004000) /*!< EndPoint Data TOGGLE RX */
4346 #define USB_EPRX_STAT ((uint32_t)0x00003000) /*!< EndPoint RX STATus bit field */
4347 #define USB_EP_SETUP ((uint32_t)0x00000800) /*!< EndPoint SETUP */
4348 #define USB_EP_T_FIELD ((uint32_t)0x00000600) /*!< EndPoint TYPE */
4349 #define USB_EP_KIND ((uint32_t)0x00000100) /*!< EndPoint KIND */
4350 #define USB_EP_CTR_TX ((uint32_t)0x00000080) /*!< EndPoint Correct TRansfer TX */
4351 #define USB_EP_DTOG_TX ((uint32_t)0x00000040) /*!< EndPoint Data TOGGLE TX */
4352 #define USB_EPTX_STAT ((uint32_t)0x00000030) /*!< EndPoint TX STATus bit field */
4353 #define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /*!< EndPoint ADDRess FIELD */
4355 /* EndPoint REGister MASK (no toggle fields) */
4356 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
4357 /*!< EP_TYPE[1:0] EndPoint TYPE */
4358 #define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /*!< EndPoint TYPE Mask */
4359 #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
4360 #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
4361 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
4362 #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
4363 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
4365 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
4366 /*!< STAT_TX[1:0] STATus for TX transfer */
4367 #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
4368 #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
4369 #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
4370 #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
4371 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
4372 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
4373 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
4374 /*!< STAT_RX[1:0] STATus for RX transfer */
4375 #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
4376 #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
4377 #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
4378 #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
4379 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
4380 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
4381 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
4383 /******************* Bit definition for USB_EP0R register *******************/
4384 #define USB_EP0R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4386 #define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4387 #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4388 #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4390 #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4391 #define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4392 #define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4394 #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4395 #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4396 #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4398 #define USB_EP0R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4400 #define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4401 #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4402 #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4404 #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4405 #define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4407 /******************* Bit definition for USB_EP1R register *******************/
4408 #define USB_EP1R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4410 #define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4411 #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4412 #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4414 #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4415 #define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4416 #define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4418 #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4419 #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4420 #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4422 #define USB_EP1R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4424 #define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4425 #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4426 #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4428 #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4429 #define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4431 /******************* Bit definition for USB_EP2R register *******************/
4432 #define USB_EP2R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4434 #define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4435 #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4436 #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4438 #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4439 #define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4440 #define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4442 #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4443 #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4444 #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4446 #define USB_EP2R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4448 #define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4449 #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4450 #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4452 #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4453 #define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4455 /******************* Bit definition for USB_EP3R register *******************/
4456 #define USB_EP3R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4458 #define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4459 #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4460 #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4462 #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4463 #define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4464 #define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4466 #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4467 #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4468 #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4470 #define USB_EP3R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4472 #define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4473 #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4474 #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4476 #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4477 #define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4479 /******************* Bit definition for USB_EP4R register *******************/
4480 #define USB_EP4R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4482 #define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4483 #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4484 #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4486 #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4487 #define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4488 #define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4490 #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4491 #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4492 #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4494 #define USB_EP4R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4496 #define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4497 #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4498 #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4500 #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4501 #define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4503 /******************* Bit definition for USB_EP5R register *******************/
4504 #define USB_EP5R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4506 #define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4507 #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4508 #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4510 #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4511 #define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4512 #define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4514 #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4515 #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4516 #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4518 #define USB_EP5R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4520 #define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4521 #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4522 #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4524 #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4525 #define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4527 /******************* Bit definition for USB_EP6R register *******************/
4528 #define USB_EP6R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4530 #define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4531 #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4532 #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4534 #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4535 #define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4536 #define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4538 #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4539 #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4540 #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4542 #define USB_EP6R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4544 #define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4545 #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4546 #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4548 #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4549 #define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4551 /******************* Bit definition for USB_EP7R register *******************/
4552 #define USB_EP7R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4554 #define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4555 #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4556 #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4558 #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4559 #define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4560 #define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4562 #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4563 #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4564 #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4566 #define USB_EP7R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4568 #define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4569 #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4570 #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4572 #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4573 #define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4575 /*!<Common registers */
4577 #define USB_CNTR (USB_BASE + 0x00000040) /*!< Control register */
4578 #define USB_ISTR (USB_BASE + 0x00000044) /*!< Interrupt status register */
4579 #define USB_FNR (USB_BASE + 0x00000048) /*!< Frame number register */
4580 #define USB_DADDR (USB_BASE + 0x0000004C) /*!< Device address register */
4581 #define USB_BTABLE (USB_BASE + 0x00000050) /*!< Buffer Table address register */
4585 /******************* Bit definition for USB_CNTR register *******************/
4586 #define USB_CNTR_FRES ((uint32_t)0x00000001) /*!<Force USB Reset */
4587 #define USB_CNTR_PDWN ((uint32_t)0x00000002) /*!<Power down */
4588 #define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /*!<Low-power mode */
4589 #define USB_CNTR_FSUSP ((uint32_t)0x00000008) /*!<Force suspend */
4590 #define USB_CNTR_RESUME ((uint32_t)0x00000010) /*!<Resume request */
4591 #define USB_CNTR_ESOFM ((uint32_t)0x00000100) /*!<Expected Start Of Frame Interrupt Mask */
4592 #define USB_CNTR_SOFM ((uint32_t)0x00000200) /*!<Start Of Frame Interrupt Mask */
4593 #define USB_CNTR_RESETM ((uint32_t)0x00000400) /*!<RESET Interrupt Mask */
4594 #define USB_CNTR_SUSPM ((uint32_t)0x00000800) /*!<Suspend mode Interrupt Mask */
4595 #define USB_CNTR_WKUPM ((uint32_t)0x00001000) /*!<Wakeup Interrupt Mask */
4596 #define USB_CNTR_ERRM ((uint32_t)0x00002000) /*!<Error Interrupt Mask */
4597 #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
4598 #define USB_CNTR_CTRM ((uint32_t)0x00008000) /*!<Correct Transfer Interrupt Mask */
4600 /******************* Bit definition for USB_ISTR register *******************/
4601 #define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /*!<Endpoint Identifier */
4602 #define USB_ISTR_DIR ((uint32_t)0x00000010) /*!<Direction of transaction */
4603 #define USB_ISTR_ESOF ((uint32_t)0x00000100) /*!<Expected Start Of Frame */
4604 #define USB_ISTR_SOF ((uint32_t)0x00000200) /*!<Start Of Frame */
4605 #define USB_ISTR_RESET ((uint32_t)0x00000400) /*!<USB RESET request */
4606 #define USB_ISTR_SUSP ((uint32_t)0x00000800) /*!<Suspend mode request */
4607 #define USB_ISTR_WKUP ((uint32_t)0x00001000) /*!<Wake up */
4608 #define USB_ISTR_ERR ((uint32_t)0x00002000) /*!<Error */
4609 #define USB_ISTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun */
4610 #define USB_ISTR_CTR ((uint32_t)0x00008000) /*!<Correct Transfer */
4612 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
4613 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
4614 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
4615 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
4616 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
4617 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
4618 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
4619 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
4622 /******************* Bit definition for USB_FNR register ********************/
4623 #define USB_FNR_FN ((uint32_t)0x000007FF) /*!<Frame Number */
4624 #define USB_FNR_LSOF ((uint32_t)0x00001800) /*!<Lost SOF */
4625 #define USB_FNR_LCK ((uint32_t)0x00002000) /*!<Locked */
4626 #define USB_FNR_RXDM ((uint32_t)0x00004000) /*!<Receive Data - Line Status */
4627 #define USB_FNR_RXDP ((uint32_t)0x00008000) /*!<Receive Data + Line Status */
4629 /****************** Bit definition for USB_DADDR register *******************/
4630 #define USB_DADDR_ADD ((uint32_t)0x0000007F) /*!<ADD[6:0] bits (Device Address) */
4631 #define USB_DADDR_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
4632 #define USB_DADDR_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
4633 #define USB_DADDR_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
4634 #define USB_DADDR_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
4635 #define USB_DADDR_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
4636 #define USB_DADDR_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
4637 #define USB_DADDR_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
4639 #define USB_DADDR_EF ((uint32_t)0x00000080) /*!<Enable Function */
4641 /****************** Bit definition for USB_BTABLE register ******************/
4642 #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /*!<Buffer Table */
4644 /*!< Buffer descriptor table */
4645 /***************** Bit definition for USB_ADDR0_TX register *****************/
4646 #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 0 */
4648 /***************** Bit definition for USB_ADDR1_TX register *****************/
4649 #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 1 */
4651 /***************** Bit definition for USB_ADDR2_TX register *****************/
4652 #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 2 */
4654 /***************** Bit definition for USB_ADDR3_TX register *****************/
4655 #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 3 */
4657 /***************** Bit definition for USB_ADDR4_TX register *****************/
4658 #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 4 */
4660 /***************** Bit definition for USB_ADDR5_TX register *****************/
4661 #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 5 */
4663 /***************** Bit definition for USB_ADDR6_TX register *****************/
4664 #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 6 */
4666 /***************** Bit definition for USB_ADDR7_TX register *****************/
4667 #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 7 */
4669 /*----------------------------------------------------------------------------*/
4671 /***************** Bit definition for USB_COUNT0_TX register ****************/
4672 #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 */
4674 /***************** Bit definition for USB_COUNT1_TX register ****************/
4675 #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 */
4677 /***************** Bit definition for USB_COUNT2_TX register ****************/
4678 #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 */
4680 /***************** Bit definition for USB_COUNT3_TX register ****************/
4681 #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 */
4683 /***************** Bit definition for USB_COUNT4_TX register ****************/
4684 #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 */
4686 /***************** Bit definition for USB_COUNT5_TX register ****************/
4687 #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 */
4689 /***************** Bit definition for USB_COUNT6_TX register ****************/
4690 #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 */
4692 /***************** Bit definition for USB_COUNT7_TX register ****************/
4693 #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 */
4695 /*----------------------------------------------------------------------------*/
4697 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
4698 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
4700 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
4701 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
4703 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
4704 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
4706 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
4707 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
4709 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
4710 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
4712 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
4713 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
4715 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
4716 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x0000000003FF) /*!< Transmission Byte Count 3 (low) */
4718 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
4719 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FF0000) /*!< Transmission Byte Count 3 (high) */
4721 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
4722 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
4724 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
4725 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
4727 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
4728 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
4730 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
4731 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
4733 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
4734 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
4736 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
4737 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
4739 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
4740 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
4742 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
4743 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
4745 /*----------------------------------------------------------------------------*/
4747 /***************** Bit definition for USB_ADDR0_RX register *****************/
4748 #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 0 */
4750 /***************** Bit definition for USB_ADDR1_RX register *****************/
4751 #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 1 */
4753 /***************** Bit definition for USB_ADDR2_RX register *****************/
4754 #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 2 */
4756 /***************** Bit definition for USB_ADDR3_RX register *****************/
4757 #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 3 */
4759 /***************** Bit definition for USB_ADDR4_RX register *****************/
4760 #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 4 */
4762 /***************** Bit definition for USB_ADDR5_RX register *****************/
4763 #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 5 */
4765 /***************** Bit definition for USB_ADDR6_RX register *****************/
4766 #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 6 */
4768 /***************** Bit definition for USB_ADDR7_RX register *****************/
4769 #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 7 */
4771 /*----------------------------------------------------------------------------*/
4773 /***************** Bit definition for USB_COUNT0_RX register ****************/
4774 #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4776 #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4777 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4778 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4779 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4780 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4781 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4783 #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4785 /***************** Bit definition for USB_COUNT1_RX register ****************/
4786 #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4788 #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4789 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4790 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4791 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4792 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4793 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4795 #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4797 /***************** Bit definition for USB_COUNT2_RX register ****************/
4798 #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4800 #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4801 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4802 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4803 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4804 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4805 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4807 #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4809 /***************** Bit definition for USB_COUNT3_RX register ****************/
4810 #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4812 #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4813 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4814 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4815 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4816 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4817 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4819 #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4821 /***************** Bit definition for USB_COUNT4_RX register ****************/
4822 #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4824 #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4825 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4826 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4827 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4828 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4829 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4831 #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4833 /***************** Bit definition for USB_COUNT5_RX register ****************/
4834 #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4836 #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4837 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4838 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4839 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4840 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4841 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4843 #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4845 /***************** Bit definition for USB_COUNT6_RX register ****************/
4846 #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4848 #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4849 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4850 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4851 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4852 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4853 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4855 #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4857 /***************** Bit definition for USB_COUNT7_RX register ****************/
4858 #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4860 #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4861 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4862 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4863 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4864 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4865 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4867 #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4869 /*----------------------------------------------------------------------------*/
4871 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
4872 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
4874 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
4875 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4876 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4877 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4878 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4879 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4881 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
4883 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
4884 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
4886 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
4887 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
4888 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
4889 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
4890 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
4891 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
4893 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
4895 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
4896 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
4898 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
4899 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4900 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4901 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4902 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4903 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4905 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
4907 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
4908 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
4910 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
4911 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
4912 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
4913 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
4914 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
4915 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
4917 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
4919 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
4920 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
4922 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
4923 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4924 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4925 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4926 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4927 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4929 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
4931 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
4932 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
4934 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
4935 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
4936 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
4937 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
4938 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
4939 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
4941 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
4943 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
4944 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
4946 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
4947 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4948 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4949 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4950 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4951 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4953 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
4955 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
4956 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
4958 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
4959 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
4960 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
4961 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
4962 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
4963 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
4965 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
4967 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
4968 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
4970 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
4971 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4972 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4973 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4974 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4975 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4977 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
4979 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
4980 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
4982 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
4983 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
4984 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
4985 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
4986 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
4987 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
4989 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
4991 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
4992 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
4994 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
4995 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4996 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4997 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4998 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4999 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5001 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5003 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
5004 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5006 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5007 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5008 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5009 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5010 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5011 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5013 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5015 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
5016 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5018 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5019 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5020 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5021 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5022 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5023 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5025 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5027 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
5028 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5030 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5031 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5032 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5033 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5034 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5035 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5037 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5039 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
5040 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5042 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5043 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5044 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5045 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5046 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5047 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5049 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5051 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
5052 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5054 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5055 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5056 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5057 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5058 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5059 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5061 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5063 /******************************************************************************/
5065 /* Window WATCHDOG (WWDG) */
5067 /******************************************************************************/
5069 /******************* Bit definition for WWDG_CR register ********************/
5070 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
5071 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
5072 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
5073 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
5074 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
5075 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
5076 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
5077 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
5079 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
5081 /******************* Bit definition for WWDG_CFR register *******************/
5082 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
5083 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
5084 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
5085 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
5086 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
5087 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
5088 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
5089 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
5091 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
5092 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
5093 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
5095 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
5097 /******************* Bit definition for WWDG_SR register ********************/
5098 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
5100 /******************************************************************************/
5102 /* SystemTick (SysTick) */
5104 /******************************************************************************/
5106 /***************** Bit definition for SysTick_CTRL register *****************/
5107 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
5108 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
5109 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
5110 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
5112 /***************** Bit definition for SysTick_LOAD register *****************/
5113 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
5115 /***************** Bit definition for SysTick_VAL register ******************/
5116 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
5118 /***************** Bit definition for SysTick_CALIB register ****************/
5119 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
5120 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
5121 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
5123 /******************************************************************************/
5125 /* Nested Vectored Interrupt Controller (NVIC) */
5127 /******************************************************************************/
5129 /****************** Bit definition for NVIC_ISER register *******************/
5130 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
5131 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
5132 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
5133 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
5134 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
5135 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
5136 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
5137 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
5138 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
5139 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
5140 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
5141 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
5142 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
5143 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
5144 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
5145 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
5146 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
5147 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
5148 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
5149 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
5150 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
5151 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
5152 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
5153 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
5154 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
5155 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
5156 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
5157 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
5158 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
5159 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
5160 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
5161 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
5162 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
5164 /****************** Bit definition for NVIC_ICER register *******************/
5165 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
5166 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
5167 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
5168 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
5169 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
5170 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
5171 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
5172 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
5173 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
5174 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
5175 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
5176 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
5177 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
5178 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
5179 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
5180 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
5181 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
5182 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
5183 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
5184 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
5185 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
5186 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
5187 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
5188 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
5189 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
5190 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
5191 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
5192 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
5193 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
5194 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
5195 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
5196 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
5197 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
5199 /****************** Bit definition for NVIC_ISPR register *******************/
5200 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
5201 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
5202 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
5203 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
5204 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
5205 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
5206 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
5207 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
5208 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
5209 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
5210 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
5211 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
5212 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
5213 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
5214 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
5215 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
5216 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
5217 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
5218 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
5219 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
5220 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
5221 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
5222 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
5223 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
5224 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
5225 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
5226 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
5227 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
5228 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
5229 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
5230 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
5231 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
5232 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
5234 /****************** Bit definition for NVIC_ICPR register *******************/
5235 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
5236 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
5237 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
5238 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
5239 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
5240 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
5241 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
5242 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
5243 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
5244 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
5245 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
5246 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
5247 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
5248 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
5249 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
5250 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
5251 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
5252 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
5253 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
5254 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
5255 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
5256 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
5257 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
5258 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
5259 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
5260 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
5261 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
5262 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
5263 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
5264 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
5265 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
5266 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
5267 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
5269 /****************** Bit definition for NVIC_IABR register *******************/
5270 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
5271 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
5272 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
5273 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
5274 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
5275 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
5276 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
5277 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
5278 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
5279 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
5280 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
5281 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
5282 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
5283 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
5284 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
5285 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
5286 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
5287 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
5288 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
5289 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
5290 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
5291 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
5292 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
5293 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
5294 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
5295 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
5296 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
5297 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
5298 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
5299 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
5300 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
5301 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
5302 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
5304 /****************** Bit definition for NVIC_PRI0 register *******************/
5305 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
5306 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
5307 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
5308 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
5310 /****************** Bit definition for NVIC_PRI1 register *******************/
5311 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
5312 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
5313 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
5314 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
5316 /****************** Bit definition for NVIC_PRI2 register *******************/
5317 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
5318 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
5319 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
5320 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
5322 /****************** Bit definition for NVIC_PRI3 register *******************/
5323 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
5324 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
5325 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
5326 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
5328 /****************** Bit definition for NVIC_PRI4 register *******************/
5329 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
5330 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
5331 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
5332 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
5334 /****************** Bit definition for NVIC_PRI5 register *******************/
5335 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
5336 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
5337 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
5338 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
5340 /****************** Bit definition for NVIC_PRI6 register *******************/
5341 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
5342 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
5343 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
5344 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
5346 /****************** Bit definition for NVIC_PRI7 register *******************/
5347 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
5348 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
5349 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
5350 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
5352 /****************** Bit definition for SCB_CPUID register *******************/
5353 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
5354 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
5355 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
5356 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
5357 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
5359 /******************* Bit definition for SCB_ICSR register *******************/
5360 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
5361 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
5362 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
5363 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
5364 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
5365 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
5366 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
5367 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
5368 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
5369 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
5371 /******************* Bit definition for SCB_VTOR register *******************/
5372 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
5373 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
5375 /*!<***************** Bit definition for SCB_AIRCR register *******************/
5376 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
5377 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
5378 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
5380 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
5381 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5382 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5383 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5385 /* prority group configuration */
5386 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
5387 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
5388 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
5389 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
5390 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
5391 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
5392 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
5393 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
5395 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
5396 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
5398 /******************* Bit definition for SCB_SCR register ********************/
5399 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
5400 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
5401 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
5403 /******************** Bit definition for SCB_CCR register *******************/
5404 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
5405 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
5406 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
5407 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
5408 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
5409 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
5411 /******************* Bit definition for SCB_SHPR register ********************/
5412 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
5413 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
5414 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
5415 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
5417 /****************** Bit definition for SCB_SHCSR register *******************/
5418 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
5419 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
5420 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
5421 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
5422 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
5423 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
5424 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
5425 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
5426 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
5427 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
5428 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
5429 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
5430 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
5431 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
5433 /******************* Bit definition for SCB_CFSR register *******************/
5435 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
5436 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
5437 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
5438 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
5439 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
5441 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
5442 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
5443 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
5444 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
5445 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
5446 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
5448 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
5449 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
5450 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
5451 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
5452 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
5453 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
5455 /******************* Bit definition for SCB_HFSR register *******************/
5456 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
5457 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
5458 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
5460 /******************* Bit definition for SCB_DFSR register *******************/
5461 #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
5462 #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
5463 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
5464 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
5465 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
5467 /******************* Bit definition for SCB_MMFAR register ******************/
5468 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
5470 /******************* Bit definition for SCB_BFAR register *******************/
5471 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
5473 /******************* Bit definition for SCB_afsr register *******************/
5474 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
5482 /** @addtogroup Exported_macro
5486 /****************************** ADC Instances *********************************/
5487 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
5489 /******************************** COMP Instances ******************************/
5490 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
5491 ((INSTANCE) == COMP2))
5493 /****************************** CRC Instances *********************************/
5494 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
5496 /****************************** DAC Instances *********************************/
5497 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
5499 /****************************** DMA Instances *********************************/
5500 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
5501 ((INSTANCE) == DMA1_Channel2) || \
5502 ((INSTANCE) == DMA1_Channel3) || \
5503 ((INSTANCE) == DMA1_Channel4) || \
5504 ((INSTANCE) == DMA1_Channel5) || \
5505 ((INSTANCE) == DMA1_Channel6) || \
5506 ((INSTANCE) == DMA1_Channel7) || \
5507 ((INSTANCE) == DMA2_Channel1) || \
5508 ((INSTANCE) == DMA2_Channel2) || \
5509 ((INSTANCE) == DMA2_Channel3) || \
5510 ((INSTANCE) == DMA2_Channel4) || \
5511 ((INSTANCE) == DMA2_Channel5))
5513 /******************************* GPIO Instances *******************************/
5514 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5515 ((INSTANCE) == GPIOB) || \
5516 ((INSTANCE) == GPIOC) || \
5517 ((INSTANCE) == GPIOD) || \
5518 ((INSTANCE) == GPIOE) || \
5519 ((INSTANCE) == GPIOH))
5521 /**************************** GPIO Lock Instances *****************************/
5522 /* On L1, all GPIO Bank support the Lock mechanism */
5523 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
5525 /******************************** I2C Instances *******************************/
5526 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
5527 ((INSTANCE) == I2C2))
5529 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5530 ((INSTANCE) == SPI2) || \
5531 ((INSTANCE) == SPI3))
5532 /****************************** IWDG Instances ********************************/
5533 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
5535 /****************************** OPAMP Instances *******************************/
5536 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
5537 ((INSTANCE) == OPAMP2))
5539 /****************************** RTC Instances *********************************/
5540 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
5542 /******************************** SPI Instances *******************************/
5543 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5544 ((INSTANCE) == SPI2) || \
5545 ((INSTANCE) == SPI3))
5547 /****************************** TIM Instances *********************************/
5548 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5549 ((INSTANCE) == TIM3) || \
5550 ((INSTANCE) == TIM4) || \
5551 ((INSTANCE) == TIM5) || \
5552 ((INSTANCE) == TIM6) || \
5553 ((INSTANCE) == TIM7) || \
5554 ((INSTANCE) == TIM9) || \
5555 ((INSTANCE) == TIM10) || \
5556 ((INSTANCE) == TIM11))
5558 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5559 ((INSTANCE) == TIM3) || \
5560 ((INSTANCE) == TIM4) || \
5561 ((INSTANCE) == TIM5) || \
5562 ((INSTANCE) == TIM9) || \
5563 ((INSTANCE) == TIM10) || \
5564 ((INSTANCE) == TIM11))
5566 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5567 ((INSTANCE) == TIM3) || \
5568 ((INSTANCE) == TIM4) || \
5569 ((INSTANCE) == TIM5) || \
5570 ((INSTANCE) == TIM9))
5572 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5573 ((INSTANCE) == TIM3) || \
5574 ((INSTANCE) == TIM4) || \
5575 ((INSTANCE) == TIM5))
5577 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5578 ((INSTANCE) == TIM3) || \
5579 ((INSTANCE) == TIM4) || \
5580 ((INSTANCE) == TIM5))
5582 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5583 ((INSTANCE) == TIM3) || \
5584 ((INSTANCE) == TIM4) || \
5585 ((INSTANCE) == TIM5) || \
5586 ((INSTANCE) == TIM9))
5588 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5589 ((INSTANCE) == TIM3) || \
5590 ((INSTANCE) == TIM4) || \
5591 ((INSTANCE) == TIM5) || \
5592 ((INSTANCE) == TIM9) || \
5593 ((INSTANCE) == TIM10) || \
5594 ((INSTANCE) == TIM11))
5596 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5597 ((INSTANCE) == TIM3) || \
5598 ((INSTANCE) == TIM4) || \
5599 ((INSTANCE) == TIM5) || \
5600 ((INSTANCE) == TIM9))
5602 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5603 ((INSTANCE) == TIM3) || \
5604 ((INSTANCE) == TIM4) || \
5605 ((INSTANCE) == TIM5) || \
5606 ((INSTANCE) == TIM9))
5608 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5609 ((INSTANCE) == TIM3) || \
5610 ((INSTANCE) == TIM4))
5612 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5613 ((INSTANCE) == TIM3) || \
5614 ((INSTANCE) == TIM4) || \
5615 ((INSTANCE) == TIM5))
5617 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5618 ((INSTANCE) == TIM3) || \
5619 ((INSTANCE) == TIM4) || \
5620 ((INSTANCE) == TIM5) || \
5621 ((INSTANCE) == TIM6) || \
5622 ((INSTANCE) == TIM7) || \
5623 ((INSTANCE) == TIM9))
5625 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5626 ((INSTANCE) == TIM3) || \
5627 ((INSTANCE) == TIM4) || \
5628 ((INSTANCE) == TIM5) || \
5629 ((INSTANCE) == TIM9))
5631 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
5633 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5634 ((INSTANCE) == TIM3) || \
5635 ((INSTANCE) == TIM4) || \
5636 ((INSTANCE) == TIM5))
5638 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
5639 ((((INSTANCE) == TIM2) && \
5640 (((CHANNEL) == TIM_CHANNEL_1) || \
5641 ((CHANNEL) == TIM_CHANNEL_2) || \
5642 ((CHANNEL) == TIM_CHANNEL_3) || \
5643 ((CHANNEL) == TIM_CHANNEL_4))) \
5645 (((INSTANCE) == TIM3) && \
5646 (((CHANNEL) == TIM_CHANNEL_1) || \
5647 ((CHANNEL) == TIM_CHANNEL_2) || \
5648 ((CHANNEL) == TIM_CHANNEL_3) || \
5649 ((CHANNEL) == TIM_CHANNEL_4))) \
5651 (((INSTANCE) == TIM4) && \
5652 (((CHANNEL) == TIM_CHANNEL_1) || \
5653 ((CHANNEL) == TIM_CHANNEL_2) || \
5654 ((CHANNEL) == TIM_CHANNEL_3) || \
5655 ((CHANNEL) == TIM_CHANNEL_4))) \
5657 (((INSTANCE) == TIM5) && \
5658 (((CHANNEL) == TIM_CHANNEL_1) || \
5659 ((CHANNEL) == TIM_CHANNEL_2) || \
5660 ((CHANNEL) == TIM_CHANNEL_3) || \
5661 ((CHANNEL) == TIM_CHANNEL_4))) \
5663 (((INSTANCE) == TIM9) && \
5664 (((CHANNEL) == TIM_CHANNEL_1) || \
5665 ((CHANNEL) == TIM_CHANNEL_2))) \
5667 (((INSTANCE) == TIM10) && \
5668 (((CHANNEL) == TIM_CHANNEL_1))) \
5670 (((INSTANCE) == TIM11) && \
5671 (((CHANNEL) == TIM_CHANNEL_1))))
5673 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5674 ((INSTANCE) == TIM3) || \
5675 ((INSTANCE) == TIM4) || \
5676 ((INSTANCE) == TIM5) || \
5677 ((INSTANCE) == TIM9) || \
5678 ((INSTANCE) == TIM10) || \
5679 ((INSTANCE) == TIM11))
5681 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5682 ((INSTANCE) == TIM3) || \
5683 ((INSTANCE) == TIM4) || \
5684 ((INSTANCE) == TIM5) || \
5685 ((INSTANCE) == TIM6) || \
5686 ((INSTANCE) == TIM7))
5688 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5689 ((INSTANCE) == TIM3) || \
5690 ((INSTANCE) == TIM4) || \
5691 ((INSTANCE) == TIM5))
5693 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5694 ((INSTANCE) == TIM3) || \
5695 ((INSTANCE) == TIM4) || \
5696 ((INSTANCE) == TIM5) || \
5697 ((INSTANCE) == TIM9))
5699 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5700 ((INSTANCE) == TIM3) || \
5701 ((INSTANCE) == TIM4) || \
5702 ((INSTANCE) == TIM5) || \
5703 ((INSTANCE) == TIM9))
5705 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5706 ((INSTANCE) == TIM3) || \
5707 ((INSTANCE) == TIM9) || \
5708 ((INSTANCE) == TIM10) || \
5709 ((INSTANCE) == TIM11))
5711 /******************** USART Instances : Synchronous mode **********************/
5712 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5713 ((INSTANCE) == USART2) || \
5714 ((INSTANCE) == USART3))
5716 /******************** UART Instances : Asynchronous mode **********************/
5717 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5718 ((INSTANCE) == USART2) || \
5719 ((INSTANCE) == USART3))
5721 /******************** UART Instances : Half-Duplex mode **********************/
5722 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5723 ((INSTANCE) == USART2) || \
5724 ((INSTANCE) == USART3))
5726 /******************** UART Instances : LIN mode **********************/
5727 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5728 ((INSTANCE) == USART2) || \
5729 ((INSTANCE) == USART3))
5731 /****************** UART Instances : Hardware Flow control ********************/
5732 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5733 ((INSTANCE) == USART2) || \
5734 ((INSTANCE) == USART3))
5736 /********************* UART Instances : Smard card mode ***********************/
5737 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5738 ((INSTANCE) == USART2) || \
5739 ((INSTANCE) == USART3))
5741 /*********************** UART Instances : IRDA mode ***************************/
5742 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5743 ((INSTANCE) == USART2) || \
5744 ((INSTANCE) == USART3))
5746 /***************** UART Instances : Multi-Processor mode **********************/
5747 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5748 ((INSTANCE) == USART2) || \
5749 ((INSTANCE) == USART3))
5751 /****************************** WWDG Instances ********************************/
5752 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
5755 /****************************** LCD Instances ********************************/
5756 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
5758 /****************************** USB Instances ********************************/
5759 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
5765 /******************************************************************************/
5766 /* For a painless codes migration between the STM32L1xx device product */
5767 /* lines, the aliases defined below are put in place to overcome the */
5768 /* differences in the interrupt handlers and IRQn definitions. */
5769 /* No need to update developed interrupt code when moving across */
5770 /* product lines within the same STM32L1 Family */
5771 /******************************************************************************/
5773 /* Aliases for __IRQn */
5775 /* Aliases for __IRQHandler */
5787 #endif /* __cplusplus */
5789 #endif /* __STM32L152xC_H */
5793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/