2 ******************************************************************************
3 * @file stm32l1xx_hal_rcc.h
4 * @author MCD Application Team
6 * @date 5-September-2014
7 * @brief Header file of RCC HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_HAL_RCC_H
40 #define __STM32L1xx_HAL_RCC_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx_hal_def.h"
49 /** @addtogroup STM32L1xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup RCC_Exported_Types RCC Exported Types
64 * @brief RCC PLL configuration structure definition
68 uint32_t PLLState; /*!< The new state of the PLL.
69 This parameter can be a value of @ref RCC_PLL_Config */
71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
74 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
75 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
77 uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
78 This parameter must be a value of @ref RCC_PLL_Division_Factor*/
82 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
86 uint32_t OscillatorType; /*!< The oscillators to be configured.
87 This parameter can be a value of @ref RCC_Oscillator_Type */
89 uint32_t HSEState; /*!< The new state of the HSE.
90 This parameter can be a value of @ref RCC_HSE_Config */
92 uint32_t LSEState; /*!< The new state of the LSE.
93 This parameter can be a value of @ref RCC_LSE_Config */
95 uint32_t HSIState; /*!< The new state of the HSI.
96 This parameter can be a value of @ref RCC_HSI_Config */
98 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
99 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
101 uint32_t LSIState; /*!< The new state of the LSI.
102 This parameter can be a value of @ref RCC_LSI_Config */
104 uint32_t MSIState; /*!< The new state of the MSI.
105 This parameter can be a value of @ref RCC_MSI_Config */
107 uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
108 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
110 uint32_t MSIClockRange; /*!< The MSI frequency range.
111 This parameter can be a value of @ref RCC_MSI_Clock_Range */
113 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
115 } RCC_OscInitTypeDef;
118 * @brief RCC System, AHB and APB busses clock configuration structure definition
122 uint32_t ClockType; /*!< The clock to be configured.
123 This parameter can be a value of @ref RCC_System_Clock_Type */
125 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
126 This parameter can be a value of @ref RCC_System_Clock_Source */
128 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
129 This parameter can be a value of @ref RCC_AHB_Clock_Source */
131 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
132 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
134 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
135 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
137 } RCC_ClkInitTypeDef;
143 /* Exported constants --------------------------------------------------------*/
144 /** @defgroup RCC_Exported_Constants RCC Exported Constants
147 #define DBP_TIMEOUT_VALUE ((uint32_t)100)
148 #define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
150 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
151 * @brief RCC registers bit address in the alias region
154 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
155 #define RCC_CR_OFFSET 0x00
156 #define RCC_CFGR_OFFSET 0x08
157 #define RCC_CIR_OFFSET 0x0C
158 #define RCC_CSR_OFFSET 0x34
159 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
160 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
161 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
162 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
164 /* --- CR Register ---*/
165 /* Alias word address of HSION bit */
166 #define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
167 #define CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
168 /* Alias word address of MSION bit */
169 #define MSION_BITNUMBER POSITION_VAL(RCC_CR_MSION)
170 #define CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4)))
171 /* Alias word address of HSEON bit */
172 #define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
173 #define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
174 /* Alias word address of CSSON bit */
175 #define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
176 #define CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
177 /* Alias word address of PLLON bit */
178 #define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
179 #define CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
181 /* --- CSR Register ---*/
182 /* Alias word address of LSION bit */
183 #define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
184 #define CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
186 /* Alias word address of LSEON bit */
187 #define LSEON_BITNUMBER POSITION_VAL(RCC_CSR_LSEON)
188 #define CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
190 /* Alias word address of LSEON bit */
191 #define LSEBYP_BITNUMBER POSITION_VAL(RCC_CSR_LSEBYP)
192 #define CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
194 /* Alias word address of RTCEN bit */
195 #define RTCEN_BITNUMBER POSITION_VAL(RCC_CSR_RTCEN)
196 #define CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
198 /* Alias word address of RTCRST bit */
199 #define RTCRST_BITNUMBER POSITION_VAL(RCC_CSR_RTCRST)
200 #define CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4)))
202 /* CR register byte 2 (Bits[23:16]) base address */
203 #define CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
205 /* CIR register byte 1 (Bits[15:8]) base address */
206 #define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
208 /* CIR register byte 2 (Bits[23:16]) base address */
209 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
215 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
219 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
220 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
222 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
223 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
228 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
231 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
232 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
233 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
234 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
235 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
236 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
238 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
239 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
240 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
241 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
242 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
243 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
248 /** @defgroup RCC_HSE_Config RCC HSE Config
251 #define RCC_HSE_OFF ((uint32_t)0x00000000)
252 #define RCC_HSE_ON ((uint32_t)0x00000001)
253 #define RCC_HSE_BYPASS ((uint32_t)0x00000005)
255 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
256 ((__HSE__) == RCC_HSE_BYPASS))
261 /** @defgroup RCC_LSE_Config RCC LSE Config
264 #define RCC_LSE_OFF ((uint32_t)0x00000000)
265 #define RCC_LSE_ON ((uint32_t)0x00000001)
266 #define RCC_LSE_BYPASS ((uint32_t)0x00000005)
268 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
269 ((__LSE__) == RCC_LSE_BYPASS))
274 /** @defgroup RCC_HSI_Config RCC HSI Config
277 #define RCC_HSI_OFF ((uint32_t)0x00000000)
278 #define RCC_HSI_ON ((uint32_t)0x00000001)
280 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
282 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
284 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
289 /** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
293 #define RCC_MSIRANGE_0 ((uint32_t)RCC_ICSCR_MSIRANGE_0) /*!< MSI = 65.536 KHz */
294 #define RCC_MSIRANGE_1 ((uint32_t)RCC_ICSCR_MSIRANGE_1) /*!< MSI = 131.072 KHz */
295 #define RCC_MSIRANGE_2 ((uint32_t)RCC_ICSCR_MSIRANGE_2) /*!< MSI = 262.144 KHz */
296 #define RCC_MSIRANGE_3 ((uint32_t)RCC_ICSCR_MSIRANGE_3) /*!< MSI = 524.288 KHz */
297 #define RCC_MSIRANGE_4 ((uint32_t)RCC_ICSCR_MSIRANGE_4) /*!< MSI = 1.048 MHz */
298 #define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /*!< MSI = 2.097 MHz */
299 #define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /*!< MSI = 4.194 MHz */
301 #define IS_RCC_MSIRANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
302 ((__RANGE__) == RCC_MSIRANGE_1) || \
303 ((__RANGE__) == RCC_MSIRANGE_2) || \
304 ((__RANGE__) == RCC_MSIRANGE_3) || \
305 ((__RANGE__) == RCC_MSIRANGE_4) || \
306 ((__RANGE__) == RCC_MSIRANGE_5) || \
307 ((__RANGE__) == RCC_MSIRANGE_6))
312 /** @defgroup RCC_LSI_Config RCC LSI Config
315 #define RCC_LSI_OFF ((uint32_t)0x00000000)
316 #define RCC_LSI_ON ((uint32_t)0x00000001)
318 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
324 /** @defgroup RCC_MSI_Config RCC MSI Config
327 #define RCC_MSI_OFF ((uint32_t)0x00000000)
328 #define RCC_MSI_ON ((uint32_t)0x00000001)
330 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
332 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */
338 /** @defgroup RCC_PLL_Config RCC PLL Config
341 #define RCC_PLL_NONE ((uint32_t)0x00000000)
342 #define RCC_PLL_OFF ((uint32_t)0x00000001)
343 #define RCC_PLL_ON ((uint32_t)0x00000002)
345 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
346 ((__PLL__) == RCC_PLL_ON))
351 /** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor
355 #define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
356 #define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
357 #define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
359 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
360 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
366 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
370 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
371 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
372 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
373 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
374 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
375 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
376 #define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
377 #define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
378 #define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
380 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \
381 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \
382 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
383 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
384 ((__MUL__) == RCC_PLL_MUL48))
389 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
392 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
393 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
394 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
395 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
397 #define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
402 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
405 #define RCC_SYSCLKSOURCE_MSI ((uint32_t)RCC_CFGR_SW_MSI)
406 #define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI)
407 #define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE)
408 #define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL)
410 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
411 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
412 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
413 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
418 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
421 #define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
422 #define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
423 #define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
424 #define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
425 #define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
426 #define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
427 #define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
428 #define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
429 #define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
431 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
432 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
433 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
434 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
435 ((__HCLK__) == RCC_SYSCLK_DIV512))
440 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
443 #define RCC_HCLK_DIV1 ((uint32_t)RCC_CFGR_PPRE1_DIV1)
444 #define RCC_HCLK_DIV2 ((uint32_t)RCC_CFGR_PPRE1_DIV2)
445 #define RCC_HCLK_DIV4 ((uint32_t)RCC_CFGR_PPRE1_DIV4)
446 #define RCC_HCLK_DIV8 ((uint32_t)RCC_CFGR_PPRE1_DIV8)
447 #define RCC_HCLK_DIV16 ((uint32_t)RCC_CFGR_PPRE1_DIV16)
449 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
450 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
451 ((__PCLK__) == RCC_HCLK_DIV16))
456 /** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source
459 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_CSR_RTCSEL_LSE)
460 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_CSR_RTCSEL_LSI)
461 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)RCC_CSR_RTCSEL_HSE)
462 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)(RCC_CR_RTCPRE_0 | RCC_CSR_RTCSEL_HSE))
463 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)(RCC_CR_RTCPRE_1 | RCC_CSR_RTCSEL_HSE))
464 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)(RCC_CR_RTCPRE | RCC_CSR_RTCSEL_HSE))
469 /** @defgroup RCC_MCO_Index RCC MCO Index
472 #define RCC_MCO1 ((uint32_t)0x00000000)
473 #define RCC_MCO RCC_MCO1
475 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
480 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
483 #define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)
484 #define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)
485 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)
486 #define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)
487 #define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)
489 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
490 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
491 ((__DIV__) == RCC_MCODIV_16))
496 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
499 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
500 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
501 #define RCC_MCO1SOURCE_MSI ((uint32_t)RCC_CFGR_MCO_MSI)
502 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
503 #define RCC_MCO1SOURCE_LSE ((uint32_t)RCC_CFGR_MCO_LSE)
504 #define RCC_MCO1SOURCE_LSI ((uint32_t)RCC_CFGR_MCO_LSI)
505 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
506 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL)
508 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
509 || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
510 || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
511 || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
516 /** @defgroup RCC_Interrupt RCC Interrupt
519 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
520 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
521 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
522 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
523 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
524 #define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF)
525 #define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSS)
526 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
531 /** @defgroup RCC_Flag RCC Flag
532 * Elements values convention: 0XXYYYYYb
533 * - YYYYY : Flag position in the register
534 * - XX : Register index
539 #define CR_REG_INDEX ((uint8_t)1)
540 #define CSR_REG_INDEX ((uint8_t)3)
542 /* Flags in the CR register */
543 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY)))
544 #define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY)))
545 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY)))
546 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY)))
548 /* Flags in the CSR register */
549 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))
550 #define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY)))
551 #define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD)))
552 #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_RMVF)))
553 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF)))
554 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))
555 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))
556 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))
557 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF)))
558 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF)))
559 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF)))
561 #define RCC_FLAG_MASK ((uint8_t)0x1F)
571 /* Exported macro ------------------------------------------------------------*/
573 /** @defgroup RCC_Exported_Macros RCC Exported Macros
577 /** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable
578 * @brief Enable or disable the AHB1 peripheral clock.
579 * @note After reset, the peripheral clock (used for registers read/write access)
580 * is disabled and the application software has to enable this clock before
584 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
585 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
586 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
587 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
588 #define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN))
590 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
591 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
592 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
594 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
595 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
596 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
597 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
598 #define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
600 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
601 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
602 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
604 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
605 * @note After reset, the peripheral clock (used for registers read/write access)
606 * is disabled and the application software has to enable this clock before
609 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
610 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
611 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
612 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
613 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
614 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
615 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
616 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
617 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
618 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
619 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
620 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
621 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
622 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
623 #define __COMP_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_COMPEN))
625 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
626 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
627 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
628 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
629 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
630 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
631 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
632 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
633 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
634 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
635 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
636 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
637 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
638 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
639 #define __COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
641 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
642 * @note After reset, the peripheral clock (used for registers read/write access)
643 * is disabled and the application software has to enable this clock before
646 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
647 #define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
648 #define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
649 #define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
650 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
651 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
652 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
654 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
655 #define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
656 #define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
657 #define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
658 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
659 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
660 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
666 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
667 * @brief Force or release AHB peripheral reset.
670 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
671 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
672 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
673 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
674 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
675 #define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
677 #define __CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
678 #define __FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))
679 #define __DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
681 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
682 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
683 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
684 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
685 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
686 #define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
688 #define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
689 #define __FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
690 #define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
692 /** @brief Force or release APB1 peripheral reset.
694 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
695 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
696 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
697 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
698 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
699 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
700 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
701 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
702 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
703 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
704 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
705 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
706 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
707 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
708 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
709 #define __COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))
711 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
712 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
713 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
714 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
715 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
716 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
717 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
718 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
719 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
720 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
721 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
722 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
723 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
724 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
725 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
726 #define __COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
728 /** @brief Force or release APB2 peripheral reset.
730 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
731 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
732 #define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
733 #define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
734 #define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
735 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
736 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
737 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
739 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
740 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
741 #define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
742 #define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
743 #define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
744 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
745 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
746 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
752 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
753 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
755 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
756 * @note By default, all peripheral clocks are enabled during SLEEP mode.
759 #define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN))
760 #define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN))
761 #define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN))
762 #define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN))
763 #define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN))
765 #define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN))
766 #define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN))
767 #define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN))
769 #define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
770 #define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
771 #define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
772 #define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
773 #define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
775 #define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
776 #define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
777 #define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
779 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
780 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
782 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
783 * @note By default, all peripheral clocks are enabled during SLEEP mode.
785 #define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
786 #define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
787 #define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
788 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
789 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
790 #define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
791 #define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
792 #define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
793 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
794 #define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
795 #define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
796 #define __USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN))
797 #define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
798 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
799 #define __COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN))
801 #define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
802 #define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
803 #define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
804 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
805 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
806 #define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
807 #define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
808 #define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
809 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
810 #define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
811 #define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
812 #define __USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
813 #define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
814 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
815 #define __COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
817 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
818 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
820 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
821 * @note By default, all peripheral clocks are enabled during SLEEP mode.
823 #define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
824 #define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
825 #define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
826 #define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
827 #define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
828 #define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
829 #define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
831 #define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
832 #define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
833 #define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
834 #define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
835 #define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
836 #define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
837 #define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
843 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
844 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
845 * @note HSI can not be stopped if it is used as system clock source. In this case,
846 * you have to select another source of the system clock then stop the HSI.
847 * @note After enabling the HSI, the application software should wait on HSIRDY
848 * flag to be set indicating that HSI clock is stable and can be used as
849 * system clock source.
850 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
853 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
854 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
856 /** @brief Macros to enable or disable the External High Speed oscillator (HSE).
857 * @param __HSE_STATE__: specifies the new state of the HSE.
858 * This parameter can be one of the following values:
859 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
860 * 6 HSE oscillator clock cycles.
861 * @arg RCC_HSE_ON: turn ON the HSE oscillator
862 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
864 #define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__HSE_STATE__))
866 /** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
867 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
868 * It is used (enabled by hardware) as system clock source after startup
869 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
870 * of the HSE used directly or indirectly as system clock (if the Clock
871 * Security System CSS is enabled).
872 * @note MSI can not be stopped if it is used as system clock source. In this case,
873 * you have to select another source of the system clock then stop the MSI.
874 * @note After enabling the MSI, the application software should wait on MSIRDY
875 * flag to be set indicating that MSI clock is stable and can be used as
876 * system clock source.
877 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
880 #define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) CR_MSION_BB = ENABLE)
881 #define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) CR_MSION_BB = DISABLE)
883 /** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
884 * @note The calibration is used to compensate for the variations in voltage
885 * and temperature that influence the frequency of the internal HSI RC.
886 * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
887 * (default is RCC_HSICALIBRATION_DEFAULT).
888 * This parameter must be a number between 0 and 0x1F.
890 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
891 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM)))
893 /** @brief macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
894 * @note The calibration is used to compensate for the variations in voltage
895 * and temperature that influence the frequency of the internal MSI RC.
896 * @param _MSICALIBRATIONVALUE_: specifies the calibration trimming value.
897 * (default is RCC_MSICALIBRATION_DEFAULT).
898 * This parameter must be a number between 0 and 0x1F.
900 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
901 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM)))
903 /* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
904 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is
905 * around 2.097 MHz. The MSI clock does not change after wake-up from
907 * @note The MSI clock range can be modified on the fly.
908 * @param _MSIRANGEVALUE_: specifies the MSI Clock range.
909 * This parameter must be one of the following values:
910 * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
911 * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
912 * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
913 * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
914 * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
915 * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
916 * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
918 #define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
921 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
922 * @note After enabling the LSI, the application software should wait on
923 * LSIRDY flag to be set indicating that LSI clock is stable and can
924 * be used to clock the IWDG and/or the RTC.
925 * @note LSI can not be disabled if the IWDG is running.
926 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
929 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
930 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
932 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
934 #define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
936 if ((__LSE_STATE__) == RCC_LSE_OFF) \
938 *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \
939 *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \
941 else if ((__LSE_STATE__) == RCC_LSE_ON) \
943 *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \
944 *(__IO uint32_t *) CSR_LSEON_BB = ENABLE; \
948 *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \
949 *(__IO uint32_t *) CSR_LSEBYP_BB = ENABLE; \
953 /** @brief Macros to enable or disable the the RTC clock.
954 * @note These macros must be used only after the RTC clock source was selected.
956 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = ENABLE)
957 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = DISABLE)
959 /** @brief Macros to force or release the Backup domain reset.
960 * @note This function resets the RTC peripheral (including the backup registers)
961 * and the RTC clock source selection in RCC_CSR register.
962 * @note The BKPSRAM is not affected by this reset.
964 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) CSR_RTCRST_BB = ENABLE)
965 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) CSR_RTCRST_BB = DISABLE)
968 /** @brief Macro to configures the RTC clock (RTCCLK).
969 * @note As the RTC clock configuration bits are in the Backup domain and write
970 * access is denied to this domain after reset, you have to enable write
971 * access using the Power Backup Access macro before to configure
972 * the RTC clock source (to be done once after reset).
973 * @note Once the RTC clock is configured it can't be changed unless the
974 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
975 * a Power On Reset (POR).
976 * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
978 * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
979 * This parameter can be one of the following values:
980 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
981 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
982 * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
983 * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
984 * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
985 * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
986 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
987 * work in STOP and STANDBY modes, and can be used as wakeup source.
988 * However, when the HSE clock is used as RTC clock source, the RTC
989 * cannot be used in STOP and STANDBY modes.
990 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
993 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
994 if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
996 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
1000 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
1001 __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
1002 RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
1005 /** @brief macros to get the RTC clock source.
1007 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
1009 /** @brief Macros to enable or disable the main PLL.
1010 * @note After enabling the main PLL, the application software should wait on
1011 * PLLRDY flag to be set indicating that PLL clock is stable and can
1012 * be used as system clock source.
1013 * @note The main PLL can not be disabled if it is used as system clock source
1014 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1016 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
1017 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
1019 /** @brief macros to configure the main PLL clock source, multiplication and division factors.
1020 * @note This function must be used only when the main PLL is disabled.
1022 * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
1023 * This parameter can be one of the following values:
1024 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
1025 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
1026 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
1027 * This parameter can be one of the following values:
1028 * @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3
1029 * @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
1030 * @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
1031 * @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
1032 * @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12
1033 * @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16
1034 * @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24
1035 * @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32
1036 * @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48
1037 * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
1038 * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
1041 * @param __PLLDIV__: specifies the division factor for PLL VCO input clock
1042 * This parameter can be one of the following values:
1043 * @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2
1044 * @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3
1045 * @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4
1048 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
1049 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
1051 /** @brief Macro to get the clock source used as system clock.
1052 * @retval The clock source used as system clock. The returned value can be one
1054 * @arg RCC_CFGR_SWS_MSI: MSI used as system clock
1055 * @arg RCC_CFGR_SWS_HSI: HSI used as system clock
1056 * @arg RCC_CFGR_SWS_HSE: HSE used as system clock
1057 * @arg RCC_CFGR_SWS_PLL: PLL used as system clock
1059 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
1061 /** @brief macros to manage the specified RCC Flags and interrupts.
1064 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
1065 * the selected interrupts.).
1066 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
1067 * This parameter can be any combination of the following values:
1068 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1069 * @arg RCC_IT_LSERDY: LSE ready interrupt
1070 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1071 * @arg RCC_IT_HSERDY: HSE ready interrupt
1072 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
1073 * @arg RCC_IT_MSIRDY: MSI ready interrupt
1074 * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
1076 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1078 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
1079 * the selected interrupts).
1080 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
1081 * This parameter can be any combination of the following values:
1082 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1083 * @arg RCC_IT_LSERDY: LSE ready interrupt
1084 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1085 * @arg RCC_IT_HSERDY: HSE ready interrupt
1086 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
1087 * @arg RCC_IT_MSIRDY: MSI ready interrupt
1088 * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
1090 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
1092 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
1093 * bits to clear the selected interrupt pending bits.
1094 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1095 * This parameter can be any combination of the following values:
1096 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1097 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1098 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1099 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1100 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1101 * @arg RCC_IT_MSIRDY: MSI ready interrupt.
1102 * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
1103 * @arg RCC_IT_CSS: Clock Security System interrupt
1105 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1107 /** @brief Check the RCC's interrupt has occurred or not.
1108 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
1109 * This parameter can be one of the following values:
1110 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1111 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1112 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1113 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1114 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1115 * @arg RCC_IT_MSIRDY: MSI ready interrupt.
1116 * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
1117 * @arg RCC_IT_CSS: Clock Security System interrupt
1118 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1120 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1122 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1123 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1125 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1127 /** @brief Check RCC flag is set or not.
1128 * @param __FLAG__: specifies the flag to check.
1129 * This parameter can be one of the following values:
1130 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
1131 * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready.
1132 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
1133 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
1134 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
1135 * @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*)
1136 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
1137 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
1138 * @arg RCC_FLAG_PINRST: Pin reset.
1139 * @arg RCC_FLAG_PORRST: POR/PDR reset.
1140 * @arg RCC_FLAG_SFTRST: Software reset.
1141 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
1142 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
1143 * @arg RCC_FLAG_LPWRRST: Low Power reset.
1144 * @note (*) This bit is available in high and medium+ density devices only.
1145 * @retval The new state of __FLAG__ (TRUE or FALSE).
1147 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
1150 /** @brief Get oscillator clock selected as PLL input clock
1151 * @retval The clock source used for PLL entry. The returned value can be one
1153 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock
1154 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
1156 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
1162 /* Include RCC HAL Extension module */
1163 #include "stm32l1xx_hal_rcc_ex.h"
1165 /* Exported functions --------------------------------------------------------*/
1166 /** @addtogroup RCC_Private_Functions
1170 /** @addtogroup RCC_Exported_Functions_Group1
1174 /* Initialization and de-initialization functions ******************************/
1175 void HAL_RCC_DeInit(void);
1176 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1177 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1183 /** @addtogroup RCC_Exported_Functions_Group2
1187 /* Peripheral Control functions ************************************************/
1188 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1189 void HAL_RCC_EnableCSS(void);
1190 void HAL_RCC_DisableCSS(void);
1191 uint32_t HAL_RCC_GetSysClockFreq(void);
1192 uint32_t HAL_RCC_GetHCLKFreq(void);
1193 uint32_t HAL_RCC_GetPCLK1Freq(void);
1194 uint32_t HAL_RCC_GetPCLK2Freq(void);
1195 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1196 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1198 /* CSS NMI IRQ handler */
1199 void HAL_RCC_NMI_IRQHandler(void);
1201 /* User Callbacks in non blocking mode (IT mode) */
1202 void HAL_RCC_CCSCallback(void);
1224 #endif /* __STM32L1xx_HAL_RCC_H */
1226 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/