2 ******************************************************************************
3 * @file stm32l1xx_hal_rcc_ex.c
4 * @author MCD Application Team
6 * @date 5-September-2014
7 * @brief Extended RCC HAL module driver.
9 * This file provides firmware functions to manage the following
10 * functionalities RCC extension peripheral:
11 * + Extended Peripheral Control functions
13 ******************************************************************************
16 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
18 * Redistribution and use in source and binary forms, with or without modification,
19 * are permitted provided that the following conditions are met:
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21 * this list of conditions and the following disclaimer.
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23 * this list of conditions and the following disclaimer in the documentation
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25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 ******************************************************************************
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32l1xx_hal.h"
46 /** @addtogroup STM32L1xx_HAL_Driver
50 /** @defgroup RCCEx RCCEx
51 * @brief RCC Extension HAL module driver
55 #ifdef HAL_RCC_MODULE_ENABLED
57 /* Private typedef -----------------------------------------------------------*/
58 /* Private define ------------------------------------------------------------*/
59 /* Private macro -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private function prototypes -----------------------------------------------*/
62 /* Private functions ---------------------------------------------------------*/
64 /** @defgroup RCCEx_Private_Functions RCCEx Exported Functions
68 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
69 * @brief Extended Peripheral Control functions
72 ===============================================================================
73 ##### Extended Peripheral Control functions #####
74 ===============================================================================
76 This subsection provides a set of functions allowing to control the RCC Clocks
79 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
80 select the RTC clock source; in this case the Backup domain will be reset in
81 order to modify the RTC Clock source, as consequence RTC registers (including
82 the backup registers) and RCC_BDCR register are set to their reset values.
89 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
90 * RCC_PeriphCLKInitTypeDef.
91 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
92 * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).
95 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
97 uint32_t tickstart = 0;
100 /* Check the parameters */
101 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
103 /*------------------------------- RTC/LCD Configuration ------------------------*/
104 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
105 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
106 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
107 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
108 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
110 || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
111 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
114 /* Enable Power Controller clock */
117 /* Enable write access to Backup domain */
118 SET_BIT(PWR->CR, PWR_CR_DBP);
120 /* Wait for Backup domain Write protection disable */
121 tickstart = HAL_GetTick();
123 while((PWR->CR & PWR_CR_DBP) == RESET)
125 if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
131 tmpreg = (RCC->CSR & RCC_CSR_RTCSEL);
132 /* Reset the Backup domain only if the RTC Clock source selection is modified */
133 if((tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
134 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
135 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
136 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
137 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
139 || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
140 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
143 /* Store the content of CSR register before the reset of Backup Domain */
144 tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
145 /* RTC Clock selection can be changed only if the Backup Domain is reset */
146 __HAL_RCC_BACKUPRESET_FORCE();
147 __HAL_RCC_BACKUPRESET_RELEASE();
148 /* Restore the Content of CSR register */
152 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
153 if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
154 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
155 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
156 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
157 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
159 || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE)
160 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
164 tickstart = HAL_GetTick();
166 /* Wait till LSE is ready */
167 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
169 if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
176 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
183 * @brief Get the PeriphClkInit according to the internal
184 * RCC configuration registers.
185 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
186 * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
189 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
193 /* Set all possible values for the extended clock type parameter------------*/
194 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
195 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
196 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
197 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
198 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
200 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
201 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
203 /* Get the RTC/LCD configuration -----------------------------------------------*/
204 srcclk = __HAL_RCC_GET_RTC_SOURCE();
205 if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
207 /* Source clock is LSE or LSI*/
208 PeriphClkInit->RTCClockSelection = srcclk;
212 /* Source clock is HSE. Need to get the prescaler value*/
213 PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
215 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
216 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
217 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
218 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
220 PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
221 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
224 #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
225 defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
226 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
227 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
230 * @brief Enables the LSE Clock Security System.
231 * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
232 * to the RTC but no hardware action is made to the registers.
233 * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
234 * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).
235 * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
236 * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with
237 * RTCSEL), or take any required action to secure the application.
238 * @note LSE CSS available only for high density and medium+ devices
241 void HAL_RCCEx_EnableLSECSS(void)
243 *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
247 * @brief Disables the LSE Clock Security System.
248 * @note Once enabled this bit cannot be disabled, except after an LSE failure detection
249 * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
250 * Reset by power on reset and RTC software reset (RTCRST bit).
251 * @note LSE CSS available only for high density and medium+ devices
254 void HAL_RCCEx_DisableLSECSS(void)
256 *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;
258 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
268 #endif /* HAL_RCC_MODULE_ENABLED */
277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/