2 ******************************************************************************
3 * @file stm32l1xx_hal_rcc_ex.h
4 * @author MCD Application Team
6 * @date 5-September-2014
7 * @brief Header file of RCC HAL Extension module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_HAL_RCC_EX_H
40 #define __STM32L1xx_HAL_RCC_EX_H
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx_hal_def.h"
49 /** @addtogroup STM32L1xx_HAL_Driver
57 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
64 * @brief RCC extended clocks structure definition
68 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
69 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
71 uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
72 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
74 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
75 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
76 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
77 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
80 uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
81 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
83 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
84 } RCC_PeriphCLKInitTypeDef;
90 /* Exported constants --------------------------------------------------------*/
92 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
96 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
99 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
101 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
102 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
103 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
104 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
107 #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002)
109 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
111 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
112 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
113 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
114 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
117 #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
119 #else /* Not LCD LINE */
121 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
123 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
128 #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
129 defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
130 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
131 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
133 /* Alias word address of LSECSSON bit */
134 #define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON)
135 #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4)))
137 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
143 /* Exported macro ------------------------------------------------------------*/
144 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
148 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
149 * @brief Enables or disables the AHB1 peripheral clock.
150 * @note After reset, the peripheral clock (used for registers read/write access)
151 * is disabled and the application software has to enable this clock before
155 #if defined (STM32L151xB) || defined (STM32L152xB) || \
156 defined (STM32L151xBA) || defined (STM32L152xBA) || \
157 defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
158 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
159 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
161 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
162 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
164 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
166 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
167 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
169 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
170 #define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN))
172 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
173 #define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
175 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
177 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
178 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
179 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
181 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
182 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
184 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
186 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
188 #define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_AESEN))
189 #define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
191 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
193 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
195 #define __FSMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FSMCEN))
196 #define __FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
198 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
200 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
201 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
202 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
203 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
206 #define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
207 #define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
209 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
211 /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
212 * @note After reset, the peripheral clock (used for registers read/write access)
213 * is disabled and the application software has to enable this clock before
216 #if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
217 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
218 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
220 #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
221 #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
223 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
225 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
226 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
227 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
229 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
230 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
232 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
234 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
235 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
237 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
238 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
240 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
241 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
243 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
245 #if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
247 #define __OPAMP_CLK_ENABLE() __COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */
248 #define __OPAMP_CLK_DISABLE() __COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */
250 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
252 /** @brief Enables or disables the High Speed APB (APB2) peripheral clock.
253 * @note After reset, the peripheral clock (used for registers read/write access)
254 * is disabled and the application software has to enable this clock before
257 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
259 #define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
260 #define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
262 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
269 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
270 * @brief Forces or releases AHB peripheral reset.
273 #if defined (STM32L151xB) || defined (STM32L152xB) || \
274 defined (STM32L151xBA) || defined (STM32L152xBA) || \
275 defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
276 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
277 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
279 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
280 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
282 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
284 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
285 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
287 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
288 #define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
290 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
291 #define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
293 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
295 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
296 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
297 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
299 #define __DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
300 #define __DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
302 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
304 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
306 #define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
307 #define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
309 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
311 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
313 #define __FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
314 #define __FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
316 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
318 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
319 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
320 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
321 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
324 #define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
325 #define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
327 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
329 /** @brief Forces or releases APB1 peripheral reset.
331 #if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
332 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
333 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
335 #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
336 #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
338 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
340 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
341 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
342 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
344 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
345 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
347 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
349 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
350 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
352 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
353 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
355 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
356 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
358 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
360 #if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
362 #define __OPAMP_FORCE_RESET() __COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
363 #define __OPAMP_RELEASE_RESET() __COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
365 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
367 /** @brief Forces or releases APB2 peripheral reset.
369 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
371 #define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
372 #define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
374 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
380 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
381 * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
382 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
384 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
385 * @note By default, all peripheral clocks are enabled during SLEEP mode.
388 #if defined (STM32L151xB) || defined (STM32L152xB) || \
389 defined (STM32L151xBA) || defined (STM32L152xBA) || \
390 defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
391 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
392 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
394 #define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
395 #define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
397 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
399 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
400 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
402 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
403 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
405 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
406 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
408 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
410 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
411 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
412 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
414 #define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
415 #define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
417 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
419 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
421 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
422 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
424 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
426 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
428 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
429 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
431 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
433 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
434 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
435 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
436 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
439 #define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
440 #define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
442 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
444 /** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
445 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
447 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
448 * @note By default, all peripheral clocks are enabled during SLEEP mode.
450 #if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
451 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
452 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
454 #define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
455 #define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
457 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
459 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
460 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
461 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
463 #define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
464 #define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
466 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
468 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
469 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
471 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
472 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
474 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
475 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
477 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
479 /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
480 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
482 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
483 * @note By default, all peripheral clocks are enabled during SLEEP mode.
485 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
487 #define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
488 #define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
490 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
496 #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
497 defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
498 defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
499 defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
503 /** @brief Macro to configures LCD clock (LCDCLK).
504 * @note LCD and RTC use the same configuration
505 * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
508 * @param __LCD_CLKSOURCE__: specifies the LCD clock source.
509 * This parameter can be one of the following values:
510 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
511 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
512 * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
513 * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
514 * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
515 * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
517 #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
519 /** @brief macros to get the LCD clock source.
521 #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
523 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
529 /* Exported functions --------------------------------------------------------*/
530 /** @addtogroup RCCEx_Private_Functions
534 /** @addtogroup RCCEx_Exported_Functions_Group1
538 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
539 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
541 #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
542 defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
543 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
544 defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
546 void HAL_RCCEx_EnableLSECSS(void);
547 void HAL_RCCEx_DisableLSECSS(void);
549 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
571 #endif /* __STM32L1xx_HAL_RCC_EX_H */
573 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/