2 ******************************************************************************
3 * @file stm32l1xx_ll_fsmc.c
4 * @author MCD Application Team
6 * @date 5-September-2014
7 * @brief FSMC Low Layer HAL module driver.
9 * This file provides firmware functions to manage the following
10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
11 * + Initialization/de-initialization functions
12 * + Peripheral Control functions
13 * + Peripheral State functions
16 =============================================================================
17 ##### FSMC peripheral features #####
18 =============================================================================
19 [..] The Flexible static memory controller (FSMC) includes following memory controllers:
20 (+) The NOR/PSRAM memory controller
22 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
23 memories and SDRAM memories. Its main purposes are:
24 (+) to translate AHB transactions into the appropriate external device protocol.
25 (+) to meet the access time requirements of the external memory devices.
27 [..] All external memories share the addresses, data and control signals with the controller.
28 Each external device is accessed by means of a unique Chip Select. The FSMC performs
29 only one access at a time to an external device.
30 The main features of the FSMC controller are the following:
31 (+) Interface with static-memory mapped devices including:
32 (++) Static random access memory (SRAM).
33 (++) NOR Flash memory.
34 (++) PSRAM (4 memory banks).
35 (+) Independent Chip Select control for each memory bank.
36 (+) Independent configuration for each memory bank.
38 =============================================================================
39 ##### How to use NORSRAM device driver #####
40 =============================================================================
43 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
44 to run the NORSRAM external devices.
46 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
47 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
48 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
49 (+) FSMC NORSRAM bank extended timing configuration using the function
50 FSMC_NORSRAM_Extended_Timing_Init()
51 (+) FSMC NORSRAM bank enable/disable write operation using the functions
52 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
55 ******************************************************************************
58 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
60 * Redistribution and use in source and binary forms, with or without modification,
61 * are permitted provided that the following conditions are met:
62 * 1. Redistributions of source code must retain the above copyright notice,
63 * this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright notice,
65 * this list of conditions and the following disclaimer in the documentation
66 * and/or other materials provided with the distribution.
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
68 * may be used to endorse or promote products derived from this software
69 * without specific prior written permission.
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 ******************************************************************************
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32l1xx_hal.h"
88 /** @addtogroup STM32L1xx_HAL_Driver
92 /** @defgroup FSMC_LL FSMC_LL
93 * @brief FSMC driver modules
97 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED)
99 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
101 /* Private typedef -----------------------------------------------------------*/
102 /* Private define ------------------------------------------------------------*/
103 /* Private macro -------------------------------------------------------------*/
104 /* Private variables ---------------------------------------------------------*/
105 /* Private function prototypes -----------------------------------------------*/
106 /* Private functions ---------------------------------------------------------*/
108 /** @defgroup FSMC_Exported_Functions FSMC Exported Functions
112 /** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions
113 * @brief Initialization and Configuration functions
116 ==============================================================================
117 ##### Initialization and de_initialization functions #####
118 ==============================================================================
120 This section provides functions allowing to:
121 (+) Initialize and configure the FSMC NORSRAM interface
122 (+) De-initialize the FSMC NORSRAM interface
123 (+) Configure the FSMC clock and associated GPIOs
130 * @brief Initialize the FSMC_NORSRAM device according to the specified
131 * control parameters in the FSMC_NORSRAM_InitTypeDef
132 * @param Device: Pointer to NORSRAM device instance
133 * @param Init: Pointer to NORSRAM Initialization structure
136 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef* Init)
140 /* Check the parameters */
141 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
142 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
143 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
144 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
145 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
146 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
147 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
148 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
149 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
150 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
151 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
152 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
153 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
155 /* Set NORSRAM device control parameters */
156 tmpr = (uint32_t)(Init->DataAddressMux |\
158 Init->MemoryDataWidth |\
159 Init->BurstAccessMode |\
160 Init->WaitSignalPolarity |\
162 Init->WaitSignalActive |\
163 Init->WriteOperation |\
165 Init->ExtendedMode |\
166 Init->AsynchronousWait |\
170 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
172 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
175 Device->BTCR[Init->NSBank] = tmpr;
182 * @brief DeInitialize the FSMC_NORSRAM peripheral
183 * @param Device: Pointer to NORSRAM device instance
184 * @param ExDevice: Pointer to NORSRAM extended mode device instance
185 * @param Bank: NORSRAM bank number
188 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank)
190 /* Check the parameters */
191 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
192 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
194 /* Disable the FSMC_NORSRAM device */
195 __FSMC_NORSRAM_DISABLE(Device, Bank);
197 /* De-initialize the FSMC_NORSRAM device */
198 /* FSMC_NORSRAM_BANK1 */
199 if(Bank == FSMC_BANK1_NORSRAM1)
201 Device->BTCR[Bank] = 0x000030DB;
203 /* FSMC_BANK1_NORSRAM2, FSMC_BANK1_NORSRAM3 or FSMC_BANK1_NORSRAM4 */
206 Device->BTCR[Bank] = 0x000030D2;
209 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
210 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
217 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
218 * parameters in the FSMC_NORSRAM_TimingTypeDef
219 * @param Device: Pointer to NORSRAM device instance
220 * @param Timing: Pointer to NORSRAM Timing structure
221 * @param Bank: NORSRAM bank number
224 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
228 /* Check the parameters */
229 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
230 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
231 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
232 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
233 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
234 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
235 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
237 /* Set FSMC_NORSRAM device timing parameters */
238 tmpr = (uint32_t)(Timing->AddressSetupTime |\
239 ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) |\
240 ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) |\
241 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) |\
242 (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) |\
243 (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BTRx_DATLAT)) |\
247 Device->BTCR[Bank + 1] = tmpr;
253 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
254 * parameters in the FSMC_NORSRAM_TimingTypeDef
255 * @param Device: Pointer to NORSRAM device instance
256 * @param Timing: Pointer to NORSRAM Timing structure
257 * @param Bank: NORSRAM bank number
258 * @param ExtendedMode: FSMC Extended Mode
259 * This parameter can be one of the following values:
260 * @arg FSMC_EXTENDED_MODE_DISABLE
261 * @arg FSMC_EXTENDED_MODE_ENABLE
264 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
266 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
267 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
269 /* Check the parameters */
270 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
271 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
272 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
273 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
274 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
276 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
277 ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) |\
278 ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) |\
279 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)) |\
280 (Timing->AccessMode));
284 Device->BWTR[Bank] = 0x0FFFFFFF;
296 /** @defgroup HAL_FSMC_NORSRAM_Group2 Control functions
297 * @brief management functions
300 ==============================================================================
301 ##### FSMC_NORSRAM Control functions #####
302 ==============================================================================
304 This subsection provides a set of functions allowing to control dynamically
305 the FSMC NORSRAM interface.
312 * @brief Enables dynamically FSMC_NORSRAM write operation.
313 * @param Device: Pointer to NORSRAM device instance
314 * @param Bank: NORSRAM bank number
317 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank)
319 /* Enable write operation */
320 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
326 * @brief Disables dynamically FSMC_NORSRAM write operation.
327 * @param Device: Pointer to NORSRAM device instance
328 * @param Bank: NORSRAM bank number
331 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank)
333 /* Disable write operation */
334 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
347 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
349 #endif /* HAL_FSMC_MODULE_ENABLED */
359 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/