1 ;/**************************************************************************//**
2 ; * @file core_ca_mmu.h
3 ; * @brief MMU Startup File for
4 ; * VE_A9_MP Device Series
6 ; * @date 25 March 2013
10 ; ******************************************************************************/
11 ;/* Copyright (c) 2012 ARM LIMITED
13 ; All rights reserved.
14 ; Redistribution and use in source and binary forms, with or without
15 ; modification, are permitted provided that the following conditions are met:
16 ; - Redistributions of source code must retain the above copyright
17 ; notice, this list of conditions and the following disclaimer.
18 ; - Redistributions in binary form must reproduce the above copyright
19 ; notice, this list of conditions and the following disclaimer in the
20 ; documentation and/or other materials provided with the distribution.
21 ; - Neither the name of ARM nor the names of its contributors may be used
22 ; to endorse or promote products derived from this software without
23 ; specific prior written permission.
25 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 ; POSSIBILITY OF SUCH DAMAGE.
36 ; ---------------------------------------------------------------------------*/
45 #define SECTION_DESCRIPTOR (0x2)
46 #define SECTION_MASK (0xFFFFFFFC)
48 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
49 #define SECTION_B_SHIFT (2)
50 #define SECTION_C_SHIFT (3)
51 #define SECTION_TEX0_SHIFT (12)
52 #define SECTION_TEX1_SHIFT (13)
53 #define SECTION_TEX2_SHIFT (14)
55 #define SECTION_XN_MASK (0xFFFFFFEF)
56 #define SECTION_XN_SHIFT (4)
58 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
59 #define SECTION_DOMAIN_SHIFT (5)
61 #define SECTION_P_MASK (0xFFFFFDFF)
62 #define SECTION_P_SHIFT (9)
64 #define SECTION_AP_MASK (0xFFFF73FF)
65 #define SECTION_AP_SHIFT (10)
66 #define SECTION_AP2_SHIFT (15)
68 #define SECTION_S_MASK (0xFFFEFFFF)
69 #define SECTION_S_SHIFT (16)
71 #define SECTION_NG_MASK (0xFFFDFFFF)
72 #define SECTION_NG_SHIFT (17)
74 #define SECTION_NS_MASK (0xFFF7FFFF)
75 #define SECTION_NS_SHIFT (19)
78 #define PAGE_L1_DESCRIPTOR (0x1)
79 #define PAGE_L1_MASK (0xFFFFFFFC)
81 #define PAGE_L2_4K_DESC (0x2)
82 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
84 #define PAGE_L2_64K_DESC (0x1)
85 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
87 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
88 #define PAGE_4K_B_SHIFT (2)
89 #define PAGE_4K_C_SHIFT (3)
90 #define PAGE_4K_TEX0_SHIFT (6)
91 #define PAGE_4K_TEX1_SHIFT (7)
92 #define PAGE_4K_TEX2_SHIFT (8)
94 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
95 #define PAGE_64K_B_SHIFT (2)
96 #define PAGE_64K_C_SHIFT (3)
97 #define PAGE_64K_TEX0_SHIFT (12)
98 #define PAGE_64K_TEX1_SHIFT (13)
99 #define PAGE_64K_TEX2_SHIFT (14)
101 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
102 #define PAGE_B_SHIFT (2)
103 #define PAGE_C_SHIFT (3)
104 #define PAGE_TEX_SHIFT (12)
106 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
107 #define PAGE_XN_4K_SHIFT (0)
108 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
109 #define PAGE_XN_64K_SHIFT (15)
112 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
113 #define PAGE_DOMAIN_SHIFT (5)
115 #define PAGE_P_MASK (0xFFFFFDFF)
116 #define PAGE_P_SHIFT (9)
118 #define PAGE_AP_MASK (0xFFFFFDCF)
119 #define PAGE_AP_SHIFT (4)
120 #define PAGE_AP2_SHIFT (9)
122 #define PAGE_S_MASK (0xFFFFFBFF)
123 #define PAGE_S_SHIFT (10)
125 #define PAGE_NG_MASK (0xFFFFF7FF)
126 #define PAGE_NG_SHIFT (11)
128 #define PAGE_NS_MASK (0xFFFFFFF7)
129 #define PAGE_NS_SHIFT (3)
131 #define OFFSET_1M (0x00100000)
132 #define OFFSET_64K (0x00010000)
133 #define OFFSET_4K (0x00001000)
135 #define DESCRIPTOR_FAULT (0x00000000)
137 /* ########################### MMU Function Access ########################### */
138 /** \ingroup MMU_FunctionInterface
139 \defgroup MMU_Functions MMU Functions Interface
143 /* Attributes enumerations */
145 /* Region size attributes */
151 } mmu_region_size_Type;
153 /* Region type attributes */
163 /* Region cacheability attributes */
170 } mmu_cacheability_Type;
172 /* Region parity check attributes */
177 } mmu_ecc_check_Type;
179 /* Region execution attributes */
186 /* Region global attributes */
193 /* Region shareability attributes */
200 /* Region security attributes */
207 /* Region access attributes */
215 /* Memory Region definition */
216 typedef struct RegionStruct {
217 mmu_region_size_Type rg_t;
218 mmu_memory_Type mem_t;
220 mmu_cacheability_Type inner_norm_t;
221 mmu_cacheability_Type outer_norm_t;
222 mmu_ecc_check_Type e_t;
223 mmu_execute_Type xn_t;
225 mmu_secure_Type sec_t;
226 mmu_access_Type priv_t;
227 mmu_access_Type user_t;
228 mmu_shared_Type sh_t;
230 } mmu_region_attributes_Type;
232 /** \brief Set section execution-never attribute
234 The function sets section execution-never attribute
236 \param [out] descriptor_l1 L1 descriptor.
237 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
241 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
243 *descriptor_l1 &= SECTION_XN_MASK;
244 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
248 /** \brief Set section domain
250 The function sets section domain
252 \param [out] descriptor_l1 L1 descriptor.
253 \param [in] domain Section domain
257 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
259 *descriptor_l1 &= SECTION_DOMAIN_MASK;
260 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
264 /** \brief Set section parity check
266 The function sets section parity check
268 \param [out] descriptor_l1 L1 descriptor.
269 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
273 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
275 *descriptor_l1 &= SECTION_P_MASK;
276 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
280 /** \brief Set section access privileges
282 The function sets section access privileges
284 \param [out] descriptor_l1 L1 descriptor.
285 \param [in] user User Level Access: NO_ACCESS, RW, READ
286 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
287 \param [in] afe Access flag enable
291 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
295 if (afe == 0) { //full access
296 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
297 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
298 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
299 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
300 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
301 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
304 else { //Simplified access
305 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
306 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
307 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
308 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
311 *descriptor_l1 &= SECTION_AP_MASK;
312 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
313 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
318 /** \brief Set section shareability
320 The function sets section shareability
322 \param [out] descriptor_l1 L1 descriptor.
323 \param [in] s_bit Section shareability: NON_SHARED, SHARED
327 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
329 *descriptor_l1 &= SECTION_S_MASK;
330 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
334 /** \brief Set section Global attribute
336 The function sets section Global attribute
338 \param [out] descriptor_l1 L1 descriptor.
339 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
343 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
345 *descriptor_l1 &= SECTION_NG_MASK;
346 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
350 /** \brief Set section Security attribute
352 The function sets section Global attribute
354 \param [out] descriptor_l1 L1 descriptor.
355 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
359 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
361 *descriptor_l1 &= SECTION_NS_MASK;
362 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
367 /** \brief Set 4k/64k page execution-never attribute
369 The function sets 4k/64k page execution-never attribute
371 \param [out] descriptor_l2 L2 descriptor.
372 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
373 \param [in] page Page size: PAGE_4k, PAGE_64k,
377 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
381 *descriptor_l2 &= PAGE_XN_4K_MASK;
382 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
386 *descriptor_l2 &= PAGE_XN_64K_MASK;
387 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
392 /** \brief Set 4k/64k page domain
394 The function sets 4k/64k page domain
396 \param [out] descriptor_l1 L1 descriptor.
397 \param [in] domain Page domain
401 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
403 *descriptor_l1 &= PAGE_DOMAIN_MASK;
404 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
408 /** \brief Set 4k/64k page parity check
410 The function sets 4k/64k page parity check
412 \param [out] descriptor_l1 L1 descriptor.
413 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
417 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
419 *descriptor_l1 &= SECTION_P_MASK;
420 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
424 /** \brief Set 4k/64k page access privileges
426 The function sets 4k/64k page access privileges
428 \param [out] descriptor_l2 L2 descriptor.
429 \param [in] user User Level Access: NO_ACCESS, RW, READ
430 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
431 \param [in] afe Access flag enable
435 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
439 if (afe == 0) { //full access
440 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
441 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
442 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
443 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
444 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
445 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
448 else { //Simplified access
449 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
450 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
451 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
452 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
455 *descriptor_l2 &= PAGE_AP_MASK;
456 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
457 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
462 /** \brief Set 4k/64k page shareability
464 The function sets 4k/64k page shareability
466 \param [out] descriptor_l2 L2 descriptor.
467 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
471 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
473 *descriptor_l2 &= PAGE_S_MASK;
474 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
478 /** \brief Set 4k/64k page Global attribute
480 The function sets 4k/64k page Global attribute
482 \param [out] descriptor_l2 L2 descriptor.
483 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
487 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
489 *descriptor_l2 &= PAGE_NG_MASK;
490 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
494 /** \brief Set 4k/64k page Security attribute
496 The function sets 4k/64k page Global attribute
498 \param [out] descriptor_l1 L1 descriptor.
499 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
503 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
505 *descriptor_l1 &= PAGE_NS_MASK;
506 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
511 /** \brief Set Section memory attributes
513 The function sets section memory attributes
515 \param [out] descriptor_l1 L1 descriptor.
516 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
517 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
518 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
522 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
524 *descriptor_l1 &= SECTION_TEXCB_MASK;
526 if (STRONGLY_ORDERED == mem)
530 else if (SHARED_DEVICE == mem)
532 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
534 else if (NON_SHARED_DEVICE == mem)
536 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
538 else if (NORMAL == mem)
540 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
546 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
549 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
552 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
560 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
563 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
566 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
574 /** \brief Set 4k/64k page memory attributes
576 The function sets 4k/64k page memory attributes
578 \param [out] descriptor_l2 L2 descriptor.
579 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
580 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
581 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
585 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
587 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
589 if (page == PAGE_64k)
592 __memory_section(descriptor_l2, mem, outer, inner);
596 if (STRONGLY_ORDERED == mem)
600 else if (SHARED_DEVICE == mem)
602 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
604 else if (NON_SHARED_DEVICE == mem)
606 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
608 else if (NORMAL == mem)
610 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
616 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
619 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
622 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
630 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
633 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
636 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
645 /** \brief Create a L1 section descriptor
647 The function creates a section descriptor.
650 - 16MB super sections not suported
651 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
652 - Functions always return 0
654 \param [out] descriptor L1 descriptor
655 \param [out] descriptor2 L2 descriptor
656 \param [in] reg Section attributes
660 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
664 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
665 __xn_section(descriptor,reg.xn_t);
666 __domain_section(descriptor, reg.domain);
667 __p_section(descriptor, reg.e_t);
668 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
669 __shared_section(descriptor,reg.sh_t);
670 __global_section(descriptor,reg.g_t);
671 __secure_section(descriptor,reg.sec_t);
672 *descriptor &= SECTION_MASK;
673 *descriptor |= SECTION_DESCRIPTOR;
680 /** \brief Create a L1 and L2 4k/64k page descriptor
682 The function creates a 4k/64k page descriptor.
684 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
685 - Functions always return 0
687 \param [out] descriptor L1 descriptor
688 \param [out] descriptor2 L2 descriptor
689 \param [in] reg 4k/64k page attributes
693 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
701 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
702 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
703 __domain_page(descriptor, reg.domain);
704 __p_page(descriptor, reg.e_t);
705 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
706 __shared_page(descriptor2,reg.sh_t);
707 __global_page(descriptor2,reg.g_t);
708 __secure_page(descriptor,reg.sec_t);
709 *descriptor &= PAGE_L1_MASK;
710 *descriptor |= PAGE_L1_DESCRIPTOR;
711 *descriptor2 &= PAGE_L2_4K_MASK;
712 *descriptor2 |= PAGE_L2_4K_DESC;
716 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
717 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
718 __domain_page(descriptor, reg.domain);
719 __p_page(descriptor, reg.e_t);
720 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
721 __shared_page(descriptor2,reg.sh_t);
722 __global_page(descriptor2,reg.g_t);
723 __secure_page(descriptor,reg.sec_t);
724 *descriptor &= PAGE_L1_MASK;
725 *descriptor |= PAGE_L1_DESCRIPTOR;
726 *descriptor2 &= PAGE_L2_64K_MASK;
727 *descriptor2 |= PAGE_L2_64K_DESC;
740 /** \brief Create a 1MB Section
742 \param [in] ttb Translation table base address
743 \param [in] base_address Section base address
744 \param [in] count Number of sections to create
745 \param [in] descriptor_l1 L1 descriptor (region attributes)
748 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
754 offset = base_address >> 20;
755 entry = (base_address & 0xFFF00000) | descriptor_l1;
760 for (i = 0; i < count; i++ )
768 /** \brief Create a 4k page entry
770 \param [in] ttb L1 table base address
771 \param [in] base_address 4k base address
772 \param [in] count Number of 4k pages to create
773 \param [in] descriptor_l1 L1 descriptor (region attributes)
774 \param [in] ttb_l2 L2 table base address
775 \param [in] descriptor_l2 L2 descriptor (region attributes)
778 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
781 uint32_t offset, offset2;
782 uint32_t entry, entry2;
786 offset = base_address >> 20;
787 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
794 offset2 = (base_address & 0xff000) >> 12;
796 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
797 for (i = 0; i < count; i++ )
805 /** \brief Create a 64k page entry
807 \param [in] ttb L1 table base address
808 \param [in] base_address 64k base address
809 \param [in] count Number of 64k pages to create
810 \param [in] descriptor_l1 L1 descriptor (region attributes)
811 \param [in] ttb_l2 L2 table base address
812 \param [in] descriptor_l2 L2 descriptor (region attributes)
815 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
817 uint32_t offset, offset2;
818 uint32_t entry, entry2;
822 offset = base_address >> 20;
823 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
830 offset2 = (base_address & 0xff000) >> 12;
832 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
833 for (i = 0; i < count; i++ )
836 for (j = 0; j < 16; j++)
839 entry2 += OFFSET_64K;
843 /*@} end of MMU_Functions */