1 /**************************************************************************//**
3 * @brief CMSIS Cortex-M Core Function Access Header File
5 * @date 25. February 2013
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
38 #ifndef __CORE_CMFUNC_H
39 #define __CORE_CMFUNC_H
42 /* ########################### Core Function Access ########################### */
43 /** \ingroup CMSIS_Core_FunctionInterface
44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
49 /* ARM armcc specific functions */
51 #if (__ARMCC_VERSION < 400677)
52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
55 /* intrinsic void __enable_irq(); */
56 /* intrinsic void __disable_irq(); */
58 /** \brief Get Control Register
60 This function returns the content of the Control Register.
62 \return Control Register value
64 __STATIC_INLINE uint32_t __get_CONTROL(void)
66 register uint32_t __regControl __ASM("control");
71 /** \brief Set Control Register
73 This function writes the given value to the Control Register.
75 \param [in] control Control Register value to set
77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
79 register uint32_t __regControl __ASM("control");
80 __regControl = control;
84 /** \brief Get IPSR Register
86 This function returns the content of the IPSR Register.
88 \return IPSR Register value
90 __STATIC_INLINE uint32_t __get_IPSR(void)
92 register uint32_t __regIPSR __ASM("ipsr");
97 /** \brief Get APSR Register
99 This function returns the content of the APSR Register.
101 \return APSR Register value
103 __STATIC_INLINE uint32_t __get_APSR(void)
105 register uint32_t __regAPSR __ASM("apsr");
110 /** \brief Get xPSR Register
112 This function returns the content of the xPSR Register.
114 \return xPSR Register value
116 __STATIC_INLINE uint32_t __get_xPSR(void)
118 register uint32_t __regXPSR __ASM("xpsr");
123 /** \brief Get Process Stack Pointer
125 This function returns the current value of the Process Stack Pointer (PSP).
127 \return PSP Register value
129 __STATIC_INLINE uint32_t __get_PSP(void)
131 register uint32_t __regProcessStackPointer __ASM("psp");
132 return(__regProcessStackPointer);
136 /** \brief Set Process Stack Pointer
138 This function assigns the given value to the Process Stack Pointer (PSP).
140 \param [in] topOfProcStack Process Stack Pointer value to set
142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
144 register uint32_t __regProcessStackPointer __ASM("psp");
145 __regProcessStackPointer = topOfProcStack;
149 /** \brief Get Main Stack Pointer
151 This function returns the current value of the Main Stack Pointer (MSP).
153 \return MSP Register value
155 __STATIC_INLINE uint32_t __get_MSP(void)
157 register uint32_t __regMainStackPointer __ASM("msp");
158 return(__regMainStackPointer);
162 /** \brief Set Main Stack Pointer
164 This function assigns the given value to the Main Stack Pointer (MSP).
166 \param [in] topOfMainStack Main Stack Pointer value to set
168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
170 register uint32_t __regMainStackPointer __ASM("msp");
171 __regMainStackPointer = topOfMainStack;
175 /** \brief Get Priority Mask
177 This function returns the current state of the priority mask bit from the Priority Mask Register.
179 \return Priority Mask value
181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
183 register uint32_t __regPriMask __ASM("primask");
184 return(__regPriMask);
188 /** \brief Set Priority Mask
190 This function assigns the given value to the Priority Mask Register.
192 \param [in] priMask Priority Mask
194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
196 register uint32_t __regPriMask __ASM("primask");
197 __regPriMask = (priMask);
201 #if (__CORTEX_M >= 0x03)
203 /** \brief Enable FIQ
205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
206 Can only be executed in Privileged modes.
208 #define __enable_fault_irq __enable_fiq
211 /** \brief Disable FIQ
213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
214 Can only be executed in Privileged modes.
216 #define __disable_fault_irq __disable_fiq
219 /** \brief Get Base Priority
221 This function returns the current value of the Base Priority register.
223 \return Base Priority register value
225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
227 register uint32_t __regBasePri __ASM("basepri");
228 return(__regBasePri);
232 /** \brief Set Base Priority
234 This function assigns the given value to the Base Priority register.
236 \param [in] basePri Base Priority value to set
238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
240 register uint32_t __regBasePri __ASM("basepri");
241 __regBasePri = (basePri & 0xff);
245 /** \brief Get Fault Mask
247 This function returns the current value of the Fault Mask register.
249 \return Fault Mask register value
251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
253 register uint32_t __regFaultMask __ASM("faultmask");
254 return(__regFaultMask);
258 /** \brief Set Fault Mask
260 This function assigns the given value to the Fault Mask register.
262 \param [in] faultMask Fault Mask value to set
264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
266 register uint32_t __regFaultMask __ASM("faultmask");
267 __regFaultMask = (faultMask & (uint32_t)1);
270 #endif /* (__CORTEX_M >= 0x03) */
273 #if (__CORTEX_M == 0x04)
277 This function returns the current value of the Floating Point Status/Control register.
279 \return Floating Point Status/Control register value
281 __STATIC_INLINE uint32_t __get_FPSCR(void)
283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
284 register uint32_t __regfpscr __ASM("fpscr");
294 This function assigns the given value to the Floating Point Status/Control register.
296 \param [in] fpscr Floating Point Status/Control value to set
298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
301 register uint32_t __regfpscr __ASM("fpscr");
302 __regfpscr = (fpscr);
306 #endif /* (__CORTEX_M == 0x04) */
309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
310 /* IAR iccarm specific functions */
312 #include <cmsis_iar.h>
315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
316 /* TI CCS specific functions */
318 #include <cmsis_ccs.h>
321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
322 /* GNU gcc specific functions */
324 /** \brief Enable IRQ Interrupts
326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
327 Can only be executed in Privileged modes.
329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
331 __ASM volatile ("cpsie i" : : : "memory");
335 /** \brief Disable IRQ Interrupts
337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
338 Can only be executed in Privileged modes.
340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
342 __ASM volatile ("cpsid i" : : : "memory");
346 /** \brief Get Control Register
348 This function returns the content of the Control Register.
350 \return Control Register value
352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
356 __ASM volatile ("MRS %0, control" : "=r" (result) );
361 /** \brief Set Control Register
363 This function writes the given value to the Control Register.
365 \param [in] control Control Register value to set
367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
373 /** \brief Get IPSR Register
375 This function returns the content of the IPSR Register.
377 \return IPSR Register value
379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
388 /** \brief Get APSR Register
390 This function returns the content of the APSR Register.
392 \return APSR Register value
394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
403 /** \brief Get xPSR Register
405 This function returns the content of the xPSR Register.
407 \return xPSR Register value
409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
418 /** \brief Get Process Stack Pointer
420 This function returns the current value of the Process Stack Pointer (PSP).
422 \return PSP Register value
424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
426 register uint32_t result;
428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
433 /** \brief Set Process Stack Pointer
435 This function assigns the given value to the Process Stack Pointer (PSP).
437 \param [in] topOfProcStack Process Stack Pointer value to set
439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
445 /** \brief Get Main Stack Pointer
447 This function returns the current value of the Main Stack Pointer (MSP).
449 \return MSP Register value
451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
453 register uint32_t result;
455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
460 /** \brief Set Main Stack Pointer
462 This function assigns the given value to the Main Stack Pointer (MSP).
464 \param [in] topOfMainStack Main Stack Pointer value to set
466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
472 /** \brief Get Priority Mask
474 This function returns the current state of the priority mask bit from the Priority Mask Register.
476 \return Priority Mask value
478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
487 /** \brief Set Priority Mask
489 This function assigns the given value to the Priority Mask Register.
491 \param [in] priMask Priority Mask
493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
499 #if (__CORTEX_M >= 0x03)
501 /** \brief Enable FIQ
503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
504 Can only be executed in Privileged modes.
506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
508 __ASM volatile ("cpsie f" : : : "memory");
512 /** \brief Disable FIQ
514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
515 Can only be executed in Privileged modes.
517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
519 __ASM volatile ("cpsid f" : : : "memory");
523 /** \brief Get Base Priority
525 This function returns the current value of the Base Priority register.
527 \return Base Priority register value
529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
538 /** \brief Set Base Priority
540 This function assigns the given value to the Base Priority register.
542 \param [in] basePri Base Priority value to set
544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
550 /** \brief Get Fault Mask
552 This function returns the current value of the Fault Mask register.
554 \return Fault Mask register value
556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
565 /** \brief Set Fault Mask
567 This function assigns the given value to the Fault Mask register.
569 \param [in] faultMask Fault Mask value to set
571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
576 #endif /* (__CORTEX_M >= 0x03) */
579 #if (__CORTEX_M == 0x04)
583 This function returns the current value of the Floating Point Status/Control register.
585 \return Floating Point Status/Control register value
587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
592 /* Empty asm statement works as a scheduling barrier */
594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
605 This function assigns the given value to the Floating Point Status/Control register.
607 \param [in] fpscr Floating Point Status/Control value to set
609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
612 /* Empty asm statement works as a scheduling barrier */
614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
619 #endif /* (__CORTEX_M == 0x04) */
622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
623 /* TASKING carm specific functions */
626 * The CMSIS functions have been implemented as intrinsics in the compiler.
627 * Please use "carm -?i" to get an up to date list of all instrinsics,
628 * Including the CMSIS ones.
633 /*@} end of CMSIS_Core_RegAccFunctions */
636 #endif /* __CORE_CMFUNC_H */